Message processing method and device based on network-on-chip, medium and product

Abstract

The embodiment of the invention provides a message processing method and device based on a network-on-chip, a medium and a product, and the method comprises the steps: receiving a request message of a processor core or a main node for accessing a memory, carrying out address state query according to the target address to obtain an address state query result, and under the condition that the address state query result indicates that the target address is not occupied, performing cache state query according to the target address to obtain a cache state query result in the first cache, and reading data from the first cache or the memory or writing data into the first cache or the memory according to the cache state query result and the type of the request message. And generating a response message of the request message. Through the embodiment of the invention, the message processing efficiency in the network-on-chip and the overall operation efficiency of the network-on-chip are improved, the load of the main node can be reduced, and the situation that the local temperature of the processor is too high in the operation process of the network-on-chip is avoided.

Description

Technical Field

[0001] The present invention relates to the field of processor technology, and in particular to a message processing method and device, medium and product based on an on-chip network. Background Art

[0002] System-on-Chip is a communication architecture applied to processors. It consists of basic units such as processor cores, home nodes (HN), slave nodes (SN), and memory. Each processor core can act as a request node (RN) to send a request message to the home node to request the home node to process the request transaction. When the request transaction involves a processing flow that requires access to memory, the home node interacts with the memory through the slave node and generates a corresponding response message to the request node.

[0003] In the related art, a method of adding a shared cache to the master node is adopted to improve the efficiency of processing request messages in the on-chip network. However, the master node needs to be responsible for maintaining the cache consistency between multiple processor cores in the process of processing request transactions. Adding a shared cache will greatly increase the functional complexity of the master node, and the load of the master node will be further increased, which will lead to the problem of local overheating of the processor during the operation of the on-chip network, affecting the performance and reliability of the processor. Summary of the invention

[0004] In view of the above problems, a method and device, medium, and product for processing messages based on a network on chip are proposed to overcome the above problems or at least partially solve the above problems, including: A message processing method based on a network on chip, the network on chip comprising a memory, a plurality of processor cores, at least one master node and at least one slave node, the slave node being provided with a first cache, the method comprising: receiving a request message from the processor core or the master node to access the memory; wherein the request message includes a target address of the memory to be accessed; Performing an address status query according to the target address to obtain an address status query result; When the address status query result indicates that the target address is not occupied, performing a cache status query according to the target address to obtain a cache status query result in the first cache; Reading data from the first cache or the memory, or writing data to the first cache or the memory according to the cache status query result and the type of the request message; Generate a response message to the request message.

[0005] Optionally, the type of the request message includes a read data request message or a write data request message, and the first cache stores a plurality of first data to be written into the memory and a first address corresponding to each of the first data and the memory; wherein, when the request message is the write data request message, the request message also includes second data; and performing a cache status query according to the target address to obtain a cache status query result in the first cache includes: If the target address exists in the plurality of first addresses, the cache status query result indicates a cache hit; If the target address does not exist in the plurality of first addresses, the cache status query result indicates a cache miss.

[0006] Optionally, the reading data from the first cache or the memory, or writing data to the first cache or the memory according to the cache status query result and the type of the request message includes: If the cache status query result indicates a cache hit, and the type of the request message is a write data request message, first target data corresponding to the target address is determined in the first cache, and the first target data is updated to the second data.

[0007] Optionally, the reading data from the first cache or the memory, or writing data to the first cache or the memory according to the cache status query result and the type of the request message, further includes: If the cache status query result indicates a cache hit, and the type of the request message is a read data request message, determining first target data corresponding to the target address in the first cache, and reading the first target data; The generating of a response message to the request message comprises: A response message to the request message is generated according to the first target data.

[0008] Optionally, the reading data from the first cache or the memory, or writing data to the first cache or the memory according to the cache status query result and the type of the request message, further includes: If the cache status query result indicates a cache miss, and the type of the request message is a write data request message, determining whether the first data reaches a storage threshold in the first cache; If the first data reaches the storage threshold in the first cache, second target data is determined from the plurality of first data; wherein the second target data is the data which has not been used for the longest time from the plurality of first data; Writing the second target data into the memory, and deleting the second target data in the first cache; The second data is written into the first cache.

[0009] Optionally, after determining whether the first data reaches a storage threshold in the first cache, the method further includes: If the first data does not reach the storage threshold in the first cache, an empty cache line is written to the first cache according to the target address.

[0010] Optionally, the reading data from the first cache or the memory, or writing data to the first cache or the memory according to the cache status query result and the type of the request message, further includes: If the cache status query result indicates a cache miss, and the type of the request message is a read data request message, reading third target data from the memory according to the target address; The generating of a response message to the request message comprises: A response message to the request message is generated according to the third target data.

[0011] Optionally, after receiving the request message for the processor core or the master node to access the memory, the method further includes: When the address status query result indicates that the target address is occupied, the request message is stored in a buffer flow.

[0012] Optionally, the input channel corresponding to the slave node includes a request channel and a data channel, both of which are used to receive the request message, and the priority of receiving the request message through the data channel is higher than the priority of receiving the request message through the request channel.

[0013] Optionally, the on-chip network further includes a memory control unit, the slave node is communicatively connected to the memory via the memory control unit, and the master node interacts with the memory via the slave node.

[0014] Optionally, the on-chip network further includes a cross switch, and the cross switch is communicatively connected with the master node, the slave node, and the plurality of processor cores.

[0015] Optionally, each of the processor cores is provided with a second cache.

[0016] An electronic device comprises a processor, a memory and a computer program stored in the memory and capable of running on the processor, wherein the computer program implements the above-mentioned message processing method based on on-chip network when executed by the processor.

[0017] A computer-readable storage medium storing a computer program, wherein the computer program is executed by a processor to implement the above-mentioned message processing method based on on-chip network A computer program product includes a computer program / instruction, wherein the computer program / instruction, when executed by a processor, implements the above-mentioned message processing method based on on-chip network.

[0018] The embodiment of the present invention has the following advantages: by receiving a request message for accessing a memory by a processor core or a master node, wherein the request message includes a target address that needs to access the memory, performing an address status query according to the target address to obtain an address status query result, and when the address status query result indicates that the target address is not occupied, performing a cache status query according to the target address to obtain a cache status query result in a first cache, and reading data from the first cache or the memory, or writing data to the first cache or the memory according to the cache status query result and the type of the request message, generating a response message to the request message, without setting a shared cache in the master node, but setting a first cache on a slave node with a lower functional complexity than the master node, the first cache is used to store first data (i.e., dirty data) that needs to be written to the memory and a first address corresponding to the first data, and when the target address is hit, the request transaction for the memory can be processed by the first target data without accessing the memory, which can not only improve the efficiency of processing messages in the on-chip network, but also improve the overall operation efficiency of the on-chip network, and can also reduce the load of the master node, and avoid the problem of excessive local temperature of the processor during the operation of the on-chip network. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solution of the present invention, the accompanying drawings required for use in the description of the present invention will be briefly introduced below. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative labor.

[0020] Figure 1 It is a flowchart of a method for processing messages based on a network on chip provided by an embodiment of the present invention; Figure 2 is a schematic diagram of an architecture of a network on chip provided by an embodiment of the present invention; Figure 3 It is a schematic diagram of a process for processing a write data request message provided by an embodiment of the present invention and comparing the present invention with a related art; Figure 4It is a flow chart of performing address status query and cache status query when processing a write data request message provided by an embodiment of the present invention; Figure 5 It is a flowchart of performing different processing according to the cache status query result when processing a write data request message provided by an embodiment of the present invention; Figure 6 It is a schematic diagram of a process for processing a read data request message provided by an embodiment of the present invention and comparing the present invention with a related art; Figure 7 It is a schematic diagram of a process for processing a read data request message provided by an embodiment of the present invention; Figure 8 It is another schematic diagram of a process for processing a read data request message provided by an embodiment of the present invention and comparing the present invention with a related art; Fig. 9 It is another schematic diagram of a process for processing a write data request message by comparing the present invention with a related art, provided by an embodiment of the present invention; Fig.10 It is a schematic diagram of a message processing pipeline architecture based on different clock cycles provided by an embodiment of the present invention; Fig.11 It is a schematic diagram of the structure of an electronic device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0021] In order to make the above-mentioned purposes, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0022] Reference Figure 1 , shows a flow chart of steps of a message processing method based on a network on chip provided by an embodiment of the present invention, wherein the network on chip includes a memory, a plurality of processor cores, at least one master node and at least one slave node, wherein the slave node is provided with a first cache, and the message processing method may specifically include the following steps: Step 101, receiving a request message from the processor core or the master node to access the memory; wherein the request message includes a target address of the memory to be accessed; In this embodiment, the processor may be a multi-core processor, and any core of the multi-core processor may send a request message, and the request message includes the cache data that the core needs to request to be processed and the cache address corresponding to the memory, that is, the target address. Through the request message, the core may request to perform transaction processing on the cache data of the target address, and these transactions may include changing the cache state of the core for the cache data, reading the cache data, or writing the cache data to the memory, etc.

[0023] The master node (HN node) is responsible for receiving the request message from the multi-core processor and then sending the request message to the slave node to access the memory.

[0024] The slave node (SN node) is equipped with a first cache, which can be a private cache and does not share data with other cores or nodes, so there is no need to maintain cache consistency. When the slave node receives a request message from the core or master node, it interacts with the memory.

[0025] In some embodiments of the present invention, the on-chip network further includes a memory control unit, the slave node is communicatively connected to the memory via the memory control unit, and the master node interacts with the memory via the slave node.

[0026] The memory control unit is used to manage memory access. When the master node needs to access the memory, it sends a request message to the slave node, and the slave node interacts with the memory through the memory control unit.

[0027] In some embodiments of the present invention, the on-chip network further includes a cross switch, and the cross switch is communicatively connected with the master node, the slave node, and the plurality of processor cores.

[0028] A crossbar is a network topology used to establish direct connections between multiple inputs and outputs. In an on-chip network, a crossbar is responsible for scheduling tasks within a cluster consisting of multiple processing cores, ensuring that only one message is sent to an HN node per clock cycle to prevent task conflicts.

[0029] For example, Figure 2 As shown, the crossbar switch communicates with the master node, the slave node, and multiple processor cores (core 1, core 2, core 3, core 4) respectively, and the slave node is responsible for interacting with the memory (DDR).

[0030] In some embodiments of the present invention, each of the processor cores is provided with a second cache.

[0031] The second cache refers to the shared cache of each processing core, which can be specifically a secondary cache. When processing the request message initiated by the core and the corresponding transaction, it is necessary to maintain cache consistency among multiple cores.

[0032] For example, Figure 2 As shown, core 1, core 2, core 3, and core 4 are all provided with a second cache.

[0033] In some embodiments of the present invention, the input channel corresponding to the slave node includes a request channel and a data channel, both of the request channel and the data channel are used to receive the request message, and the priority of receiving the request message through the data channel is higher than the priority of receiving the request message through the request channel.

[0034] In this embodiment, the input channel of the slave node includes a request channel and a data channel, both of which are used to receive request messages. In order to ensure processing efficiency, the priority of receiving request messages through the data channel is higher than the priority of receiving request messages through the request channel.

[0035] Step 102, performing an address status query according to the target address to obtain an address status query result; Address status query, check whether the target address is occupied by other request messages or transactions. If it is occupied, in order to avoid transaction conflicts, the request message needs to be temporarily suspended; if it is not occupied, the request message can be processed in the next step.

[0036] Exemplarily, the address status of each cache address may be maintained through a preset address table entry, and then the address status of the target address may be queried through the address table entry.

[0037] Step 103, when the address status query result indicates that the target address is not occupied, perform a cache status query according to the target address to obtain a cache status query result in the first cache; The cache status query is to query whether there is cache data corresponding to the target address in the first cache of the slave node. According to different cache status query results, the request message is processed differently.

[0038] In some embodiments of the present invention, the type of the request message includes a read data request message or a write data request message, and the first cache stores a plurality of first data to be written into the memory and a first address corresponding to each of the first data and the memory; wherein, when the request message is the write data request message, the request message also includes second data; and performing a cache status query according to the target address to obtain a cache status query result in the first cache includes: If the target address exists in the plurality of first addresses, the cache status query result indicates a cache hit; If the target address does not exist in the plurality of first addresses, the cache status query result indicates a cache miss.

[0039] In this embodiment, the first cache stores multiple first data that need to be written to the memory, that is, the first data is dirty data (data inconsistent with the data stored in the memory), and a first address, which can be a cache address corresponding to the first data and the memory.

[0040] The read data request message is a request message for a transaction involving reading data from the memory, and the write data request message is a request message for a transaction involving writing data into the memory. The second data is the data that needs to be written into the memory.

[0041] Specifically, by matching the target address with multiple first addresses, if the match is successful, the cache status query result indicates a cache hit, indicating that data corresponding to the target address is stored in the first cache; if the match is successful, the cache status query result indicates a cache miss, indicating that data corresponding to the target address is not stored in the first cache.

[0042] In some embodiments of the present invention, after receiving the request message for the processor core or the master node to access the memory, the method further includes: When the address status query result indicates that the target address is occupied, the request message is stored in a buffer flow.

[0043] Specifically, if the address status query result indicates that the target address is occupied, it means that other transactions are occupying the target address. In order to avoid transaction conflicts, the request message needs to be temporarily suspended. Therefore, the request message is placed in the buffer, and the request message and the corresponding transaction are taken out of the buffer after the target address is unoccupied.

[0044] Step 104: read data from the first cache or the memory, or write data to the first cache or the memory according to the cache status query result and the type of the request message; In this embodiment, different processing of writing or reading data is required according to different types of request messages; and different processing is required based on the first cache or the memory according to different cache status query results.

[0045] In this embodiment, by setting the first cache as a private cache in the slave node, when reading data from the first cache or writing data to the first cache, the efficiency of processing the request message is improved because the slave node does not need to interact with the memory. At the same time, there is no need to set up a shared cache in the master node to improve the message processing efficiency, which greatly reduces the load pressure on the master node.

[0046] In some embodiments of the present invention, reading data from the first cache or the memory, or writing data to the first cache or the memory according to the cache status query result and the type of the request message, includes: If the cache status query result indicates a cache hit, and the type of the request message is a write data request message, first target data corresponding to the target address is determined in the first cache, and the first target data is updated to the second data.

[0047] In this embodiment, when the type of the request message is a write data request message and the cache hits, it means that the second data is the latest data (dirty data) relative to the first data stored in the first cache, and the first data in the first cache can be updated to the second data.

[0048] In some embodiments, Figure 3 As shown, there are cores 0, 1, and 2, where cores 0 and 2 are in I state (invalid state), and core 1 is in SD state (Share Dirty, i.e. Figure 3 In the second shared state in the master node, when core 0 initiates a ReadShared (shared read request) transaction to the master node for the target address, since core 1 has dirty data, the master node sends a SnpShared (shared resource monitoring) request to core 1, and core 1 responds to the master node with SnpRespData_SC_PD (the state is SC (Share Clean, i.e. Figure 3 The response includes the dirty data that needs to be written to the memory.

[0049] Furthermore, the master node initiates a WriteNoSnpFull (write request transaction) to the slave node, and the slave node replies with a CompDBIDResp response (response data), stating that data can be written to the memory; then the master node initiates a NCBWrData (write data request message) to the slave node.

[0050] At this time, the slave node receives a write data request message (NCBWrData). In the related art, since the slave node does not have a cache, it needs to interact with the memory. The slave node initiates a Write_REQ (write operation) to the memory to write the dirty data into the memory.

[0051] In the example of the present invention ( Figure 3 In the direction indicated by the arrow in the middle), since the slave node is provided with a first cache, and assuming a cache hit, the cache data corresponding to the target address in the first cache is updated, and there is no need to write the dirty data into the memory (no write operation is performed), that is, the slave node does not need to interact with the memory, which greatly improves the processing efficiency of the request message.

[0052] Then, the master node responds to core 0 with CompData_SC (response data in the first shared state). After core 0 replies with CompAck (complete response), the cache states of core 0 and core 1 change to the first shared state, and the ReadShared transaction ends.

[0053] Step 105: Generate a response message to the request message.

[0054] In some embodiments of the present invention, reading data from the first cache or the memory, or writing data to the first cache or the memory according to the cache status query result and the type of the request message, further includes: If the cache status query result indicates a cache miss, and the type of the request message is a write data request message, determining whether the first data reaches a storage threshold in the first cache; If the first data reaches the storage threshold in the first cache, second target data is determined from the plurality of first data; wherein the second target data is the data which has not been used for the longest time from the plurality of first data; Writing the second target data into the memory, and deleting the second target data in the first cache; The second data is written into the first cache.

[0055] In this embodiment, when the type of the request message is a write data request message and the cache misses, it is necessary to determine whether the first data stored in the first cache reaches a storage threshold, that is, whether the first cache has been fully written.

[0056] Exemplarily, if the first cache is full, the second target data that has not been used for the longest time is determined based on the LRU (Least Recently Used) algorithm. Then, the second target data is written to the memory, and the second target data is deleted to release the storage space of the first cache. After the storage space of the first cache is released, the second data is written to the first cache.

[0057] In some embodiments of the present invention, after determining whether the first data reaches a storage threshold in the first cache, the method further includes: If the first data does not reach the storage threshold in the first cache, an empty cache line is written to the first cache according to the target address.

[0058] In this embodiment, when the first cache is not full, an empty cache line corresponding to the target address is written into the first cache to serve as a placeholder.

[0059] Exemplarily, after writing to the empty cache line, when the slave node receives a write data request for the target address again, a cache hit occurs, and the empty cache line is updated to the corresponding memory data that needs to be written.

[0060] In some examples, the write data request message can be processed based on the message processing pipeline. The message processing pipeline is a technology used in communication systems to efficiently process and transmit data. By dividing the data processing process into multiple stages, each stage can process different messages in parallel, thereby improving the throughput and efficiency of the system. The pipeline stages for processing the write data request message are as follows: In the message processing pipeline, such as Figure 4 As shown in the figure, after receiving the write data request message (write request) for the target address, the slave node enters the address query and cache status query processing stage. In this stage, it is determined whether the target address is occupied. If it is occupied, it waits for the target address to be released; if it is not occupied, it queries and records whether the first cache in the slave node hits, and after completion, it hits the message processing pipeline (Pipeline Bubble).

[0061] Further, it enters the stage of performing different processing according to the cache status query results, such as Figure 5 As shown: If the cache status query result indicates a cache hit, the cache data stored in the slave node is updated and the transaction ends; if it does not hit, the cache is checked to see if it is full: If the cache is full, the cache is replaced based on the LRU algorithm and the transaction ends; if it is not full, an empty cache line is written and the transaction ends.

[0062] In some embodiments of the present invention, reading data from the first cache or the memory, or writing data to the first cache or the memory according to the cache status query result and the type of the request message, further includes: If the cache status query result indicates a cache hit, and the type of the request message is a read data request message, determining first target data corresponding to the target address in the first cache, and reading the first target data; The generating of a response message to the request message comprises: A response message to the request message is generated according to the first target data.

[0063] In this embodiment, if the cache status query result indicates a cache hit, it means that the first target data corresponding to the target address is stored in the first cache of the slave node, and the first target data is directly obtained from the first cache, and a response message with the first target data is generated and returned to the initiator of the request message.

[0064] In some examples, such as Figure 6 As shown, there are core 0, core 1, and core 2, where core 0, core 1, and core 2 are all in I state. Core 0 initiates a request message of a ReadOnce transaction (the first read request transaction) for the target address. After receiving the message, the master node initiates a request message of a ReadNoSnp transaction (the second read request transaction) to the slave node.

[0065] At this time, the slave node receives a read data request message (ReadNoSnp). In the related technology, the slave node initiates a Read_REQ request (read request) to the memory, and the memory returns Data to the slave node. After receiving Data, the slave node returns CompData_I (i.e. Figure 6 The response data_invalid state in the response message refers to a response message with response data in the invalid state). The process of initiating a request from a node to a memory and reading data from the memory usually takes dozens of clock cycles, which prolongs the processing time of the request message.

[0066] In the example of the present invention ( Figure 6 In the direction indicated by the arrow in the middle), since the slave node sets the first cache and the cache hits, the first target data corresponding to the target address is directly read from the first cache (i.e. Figure 6 The slave node can directly return CompData_I to the master node without interacting with the memory. The setting of the first cache not only reduces the memory access frequency, but also improves the efficiency of the system in processing request messages.

[0067] Finally, the master node returns the CompData_I response message to core 0, and core 0 replies with CompAck (transaction completion response), and the processing of the message and transaction is completed.

[0068] In some embodiments of the present invention, reading data from the first cache or the memory, or writing data to the first cache or the memory according to the cache status query result and the type of the request message, further includes: If the cache status query result indicates a cache miss, and the type of the request message is a read data request message, reading third target data from the memory according to the target address; The generating of a response message to the request message comprises: A response message to the request message is generated according to the third target data.

[0069] In this embodiment, if the cache misses, it means that the first cache does not store data corresponding to the target address. It is necessary to read the third target data corresponding to the target address from the memory and generate a response message with the third target data to return to the initiator of the request message.

[0070] In some examples, such as Figure 7 As shown, the read data request message can be processed based on the message processing pipeline, as follows: In the message processing pipeline, when the slave node receives a read data request message (read request), it enters the address query and cache status query processing stage. In this stage, if the target address is occupied, wait for the target address to be released; if it is not occupied, enter the processing stage for different processing according to the cache status query result: If the cache status query result indicates a cache hit, the cache data is read from the first cache; if the cache status query result indicates a cache miss, the data is read from the memory.

[0071] Then, the request message is processed, and a response message is generated and returned according to the cache data read from the first cache or the data read from the memory, and the transaction ends.

[0072] In some embodiments of the present invention, the slave node can also receive request messages from the processor core without passing through the master node, further improving the efficiency of message processing, reducing the workload of the master node, achieving load balancing, and avoiding local overheating during system operation.

[0073] In some examples, such as Figure 8 As shown, there are core 0, core 1, and core 2, wherein core 0, core 1, and core 2 are all in I state, and core 0 initiates a request message of a ReadNoSnp transaction (a second read request transaction) for the target address.

[0074] In the related technology, after receiving ReadNoSnp, the master node needs to initiate a ReadNoSnp transaction (second read request transaction) request message to the slave node. The slave node needs to initiate a Read_REQ request (read request) to the memory, and the memory returns Data to the slave node. After receiving Data, the slave node returns CompData_I (i.e. Figure 8The response data_invalid state in the message refers to a response message with response data in the invalid state).

[0075] In the examples provided by the present invention (such as Figure 8 In the direction indicated by the arrow), core 0 can directly initiate a request message for the ReadNoSnp transaction to the slave node without going through the master node. If the cache hits at this time, the slave node directly returns CompData_I (that is, the first target data required by core 0) to core 0, and core 0 replies CompAck (transaction completion response), and the message and transaction processing are completed.

[0076] In some examples, such as Fig. 9 As shown, there are core 0, core 1, and core 2, wherein core 0, core 1, and core 2 are all in I state, and core 0 initiates WriteNoSnp (write request transaction) for the target address.

[0077] In the related technology, the master node needs to first reply CompDBIDResp (write request transaction response) to declare that data can be sent, and core 0 then initiates NCBWrData (write data request message) to the master node. The master node then sends WriteNoSnp (write request transaction) to the slave node. The slave node replies CompDBIDResp (response data), and the master node sends NCBWrData (write data request message) again. The slave node executes Write_REQ (write operation) from the memory.

[0078] In the examples provided by the present invention (such as Fig. 9 In the direction indicated by the arrow), the slave node directly receives the WriteNoSnp (write request transaction) of core 0 without going through the master node, and returns CompDBIDResp (write request transaction response) to core 0. Core 0 initiates NCBWrData (write data request message), and the cache hits at this time. The slave node updates the first cache without interacting with the memory.

[0079] In the above example, not only the interaction process between the slave node and the memory is saved, but also the interaction process related to the master node is saved. Not only the message processing efficiency is improved, but also the load pressure on the master node is reduced, avoiding local overheating of the on-chip network communication system.

[0080] In some examples of the present invention, a message processing pipeline may be established on the slave node based on different clock cycles to process the request message, such as Fig.10 As shown, the details are as follows: In clock cycle 0, the slave node receives the request message and loads the request message; In clock cycle 1, the slave node performs address status query and cache status query simultaneously; In clock cycle 2, the slave node performs different processing according to the result of the cache status query: if the cache hits, the data is read or written from the first cache; if the cache misses, the data is read or written from the memory; In clock cycle 3, the slave node processes the request message and generates a corresponding response message or data. If the request message is a read data request message and the cache hits, a corresponding data packet is generated based on the data read from the first cache without accessing the memory. If it is a write data request message, a corresponding response message is directly generated.

[0081] The embodiment of the present invention has the following advantages: by receiving a request message for accessing a memory by a processor core or a master node, wherein the request message includes a target address that needs to access the memory, performing an address status query according to the target address to obtain an address status query result, and when the address status query result indicates that the target address is not occupied, performing a cache status query according to the target address to obtain a cache status query result in a first cache, and reading data from the first cache or the memory, or writing data to the first cache or the memory according to the cache status query result and the type of the request message, generating a response message to the request message, without setting a shared cache in the master node, but setting a first cache on a slave node with a lower functional complexity than the master node, the first cache is used to store first data (i.e., dirty data) that needs to be written to the memory and a first address corresponding to the first data, and when the target address is hit, the request transaction for the memory can be processed by the first target data without accessing the memory, which can not only improve the efficiency of processing messages in the on-chip network, but also improve the overall operation efficiency of the on-chip network, and can also reduce the load of the master node, and avoid the problem of excessive local temperature of the processor during the operation of the on-chip network.

[0082] It should be noted that, for the sake of simplicity, the method embodiments are described as a series of action combinations, but those skilled in the art should be aware that the embodiments of the present invention are not limited by the order of the actions described, because according to the embodiments of the present invention, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all preferred embodiments, and the actions involved are not necessarily required by the embodiments of the present invention.

[0083] The embodiment of the present invention further provides an electronic device, such as Fig.11 As shown, it includes a processor 1101, a communication interface 1102, a memory 1103 and a communication bus 1104, wherein the processor 1101, the communication interface 1102, and the memory 1103 communicate with each other through the communication bus 1104. Memory 1103, used for storing computer programs; The processor 1101, when used to execute the program stored in the memory 1103, can implement the above-mentioned message processing method based on the on-chip network, wherein the on-chip network includes a memory, a plurality of processor cores, at least one master node and at least one slave node, wherein the slave node is provided with a first cache, and the specific steps are as follows: receiving a request message from the processor core or the master node to access the memory; wherein the request message includes a target address of the memory to be accessed; Performing an address status query according to the target address to obtain an address status query result; When the address status query result indicates that the target address is not occupied, performing a cache status query according to the target address to obtain a cache status query result in the first cache; Reading data from the first cache or the memory, or writing data to the first cache or the memory according to the cache status query result and the type of the request message; Generate a response message to the request message.

[0084] In some embodiments of the present invention, the type of the request message includes a read data request message or a write data request message, and the first cache stores a plurality of first data to be written into the memory and a first address corresponding to each of the first data and the memory; wherein, when the request message is the write data request message, the request message also includes second data; and performing a cache status query according to the target address to obtain a cache status query result in the first cache includes: If the target address exists in the plurality of first addresses, the cache status query result indicates a cache hit; If the target address does not exist in the plurality of first addresses, the cache status query result indicates a cache miss.

[0085] In some embodiments of the present invention, reading data from the first cache or the memory, or writing data to the first cache or the memory according to the cache status query result and the type of the request message, includes: If the cache status query result indicates a cache hit, and the type of the request message is a write data request message, first target data corresponding to the target address is determined in the first cache, and the first target data is updated to the second data.

[0086] In some embodiments of the present invention, reading data from the first cache or the memory, or writing data to the first cache or the memory according to the cache status query result and the type of the request message, further includes: If the cache status query result indicates a cache hit, and the type of the request message is a read data request message, determining first target data corresponding to the target address in the first cache, and reading the first target data; The generating of a response message to the request message comprises: A response message to the request message is generated according to the first target data.

[0087] In some embodiments of the present invention, reading data from the first cache or the memory, or writing data to the first cache or the memory according to the cache status query result and the type of the request message, further includes: If the cache status query result indicates a cache miss, and the type of the request message is a write data request message, determining whether the first data reaches a storage threshold in the first cache; If the first data reaches the storage threshold in the first cache, second target data is determined from the plurality of first data; wherein the second target data is the data which has not been used for the longest time from the plurality of first data; Writing the second target data into the memory, and deleting the second target data in the first cache; The second data is written into the first cache.

[0088] In some embodiments of the present invention, after determining whether the first data reaches a storage threshold in the first cache, the method further includes: If the first data does not reach the storage threshold in the first cache, an empty cache line is written to the first cache according to the target address.

[0089] In some embodiments of the present invention, reading data from the first cache or the memory, or writing data to the first cache or the memory according to the cache status query result and the type of the request message, further includes: If the cache status query result indicates a cache miss, and the type of the request message is a read data request message, reading third target data from the memory according to the target address; The generating of a response message to the request message comprises: A response message to the request message is generated according to the third target data.

[0090] In some embodiments of the present invention, after receiving the request message for the processor core or the master node to access the memory, the method further includes: When the address status query result indicates that the target address is occupied, the request message is stored in a buffer flow.

[0091] In some embodiments of the present invention, the input channel corresponding to the slave node includes a request channel and a data channel, both of the request channel and the data channel are used to receive the request message, and the priority of receiving the request message through the data channel is higher than the priority of receiving the request message through the request channel.

[0092] In some embodiments of the present invention, the on-chip network further includes a memory control unit, the slave node is communicatively connected to the memory via the memory control unit, and the master node interacts with the memory via the slave node.

[0093] In some embodiments of the present invention, the on-chip network further includes a cross switch, and the cross switch is communicatively connected with the master node, the slave node, and the plurality of processor cores.

[0094] In some embodiments of the present invention, each of the processor cores is provided with a second cache.

[0095] The communication bus mentioned in the above terminal can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. The communication bus can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, only one thick line is used in the figure, but it does not mean that there is only one bus or one type of bus.

[0096] The communication interface is used for communication between the above terminal and other devices.

[0097] The memory may include a random access memory (RAM) or a non-volatile memory, such as at least one disk memory. Optionally, the memory may also be at least one storage device located away from the aforementioned processor.

[0098] The above-mentioned processor can be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc.; it can also be a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components.

[0099] Some embodiments of the present invention further provide a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the above-mentioned message processing method based on on-chip network is implemented.

[0100] Some embodiments of the present invention further provide a computer program product, including a computer program, which implements the above-mentioned message processing method based on on-chip network when executed by a processor.

[0101] As for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0102] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data must comply with the relevant laws, regulations and standards of relevant countries and regions, and provide corresponding operation entrances for users to choose to authorize or refuse.

[0103] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0104] Those skilled in the art will appreciate that the embodiments of the present invention may be provided as methods, devices, or computer program products. Therefore, the embodiments of the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the embodiments of the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes.

[0105] The embodiments of the present invention are described with reference to the flowcharts and / or block diagrams of the methods, terminal devices (systems), and computer program products according to the embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of the processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing terminal device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing terminal device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0106] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing terminal device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce a manufactured product including an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0107] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal device so that a series of operating steps are executed on the computer or other programmable terminal device to produce a computer-implemented process, thereby providing instructions for executing on the computer or other programmable terminal device to implement the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0108] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the embodiments of the present invention.

[0109] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or terminal device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or terminal device. In the absence of further restrictions, the elements defined by the sentence "including one..." do not exclude the existence of other identical elements in the process, method, article or terminal device including the above elements.

[0110] The above is a detailed introduction to the provided on-chip network-based message processing method and equipment, medium, and product. Specific examples are used in this article to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea; at the same time, for general technical personnel in this field, according to the idea of ​​the present invention, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present invention.

Claims

1. A message processing method based on a network on chip, characterized in that: The network on chip includes a memory, a plurality of processor cores, at least one master node and at least one slave node, wherein the slave node is provided with a first cache, and the method includes: receiving a request message from the processor core or the master node to access the memory; wherein the request message includes a target address of the memory to be accessed; Performing an address status query according to the target address to obtain an address status query result; When the address status query result indicates that the target address is not occupied, performing a cache status query according to the target address to obtain a cache status query result in the first cache; Reading data from the first cache or the memory, or writing data to the first cache or the memory according to the cache status query result and the type of the request message; Generate a response message to the request message.

2. The message processing method based on network on chip according to claim 1, characterized in that: The type of the request message includes a read data request message or a write data request message, and the first cache stores a plurality of first data to be written into the memory and a first address corresponding to each of the first data and the memory; wherein, when the request message is the write data request message, the request message also includes second data; and performing a cache status query according to the target address to obtain a cache status query result in the first cache includes: If the target address exists in the plurality of first addresses, the cache status query result indicates a cache hit; If the target address does not exist in the plurality of first addresses, the cache status query result indicates a cache miss.

3. The method for processing messages based on network on chip according to claim 2, characterized in that: The reading data from the first cache or the memory, or writing data to the first cache or the memory according to the cache status query result and the type of the request message, includes: If the cache status query result indicates a cache hit, and the type of the request message is a write data request message, first target data corresponding to the target address is determined in the first cache, and the first target data is updated to the second data.

4. The method for processing messages based on network on chip according to claim 2, characterized in that: The step of reading data from the first cache or the memory, or writing data to the first cache or the memory according to the cache status query result and the type of the request message, further includes: If the cache status query result indicates a cache hit, and the type of the request message is a read data request message, determining first target data corresponding to the target address in the first cache, and reading the first target data; The generating of a response message to the request message comprises: A response message to the request message is generated according to the first target data.

5. The method for processing messages based on network on chip according to claim 2, characterized in that: The step of reading data from the first cache or the memory, or writing data to the first cache or the memory according to the cache status query result and the type of the request message, further includes: If the cache status query result indicates a cache miss, and the type of the request message is a write data request message, determining whether the first data reaches a storage threshold in the first cache; If the first data reaches the storage threshold in the first cache, second target data is determined from the plurality of first data; wherein the second target data is the data which has not been used for the longest time from the plurality of first data; Writing the second target data into the memory, and deleting the second target data in the first cache; The second data is written into the first cache.

6. The method for processing messages based on network on chip according to claim 5, characterized in that: After determining whether the first data reaches the storage threshold in the first cache, the method further includes: If the first data does not reach the storage threshold in the first cache, an empty cache line is written to the first cache according to the target address.

7. The method for processing messages based on network on chip according to claim 2, characterized in that: The step of reading data from the first cache or the memory, or writing data to the first cache or the memory according to the cache status query result and the type of the request message, further includes: If the cache status query result indicates a cache miss, and the type of the request message is a read data request message, reading third target data from the memory according to the target address; The generating of a response message to the request message comprises: A response message to the request message is generated according to the third target data.

8. The method for processing messages based on a network on chip according to any one of claims 1 to 7, characterized in that: After receiving the request message for the processor core or the master node to access the memory, the method further includes: When the address status query result indicates that the target address is occupied, the request message is stored in a buffer flow.

9. The method for processing messages based on a network on chip according to any one of claims 1 to 7, characterized in that: The input channel corresponding to the slave node includes a request channel and a data channel, both of which are used to receive the request message, and the priority of receiving the request message through the data channel is higher than the priority of receiving the request message through the request channel.

10. The method for processing messages based on a network on chip according to any one of claims 1 to 7, characterized in that: The on-chip network also includes a memory control unit, the slave node is communicatively connected to the memory via the memory control unit, and the master node interacts with the memory via the slave node.

11. The method for processing messages based on a network on chip according to any one of claims 1 to 7, characterized in that: The on-chip network further includes a cross switch, which is communicatively connected with the master node, the slave node, and the plurality of processor cores.

12. The method for processing messages based on a network on chip according to any one of claims 1 to 7, characterized in that: Each of the processor cores is provided with a second cache.

13. An electronic device, characterized in that: The invention comprises a processor, a memory and a computer program stored in the memory and capable of running on the processor, wherein when the computer program is executed by the processor, the method for processing messages based on a network on a chip as claimed in any one of claims 1 to 12 is implemented.

14. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the method for processing messages based on a network on a chip according to any one of claims 1 to 12 is implemented.

15. A computer program product comprising a computer program / instructions, characterized in that When the computer program / instruction is executed by the processor, the method for processing messages based on a network on a chip as described in any one of claims 1 to 12 is implemented.

Images