Matrix multiplication rapid calculation method and device, equipment and storage medium

Abstract

The invention provides a matrix multiplication rapid calculation method, device and equipment and a storage medium, and relates to the field of electrical digital data processing.The method comprises the steps that a first matrix and a third matrix are determined based on different storage positions; determining the actual bit width of the processor, and compressing the first matrix and the third matrix based on the actual bit width to obtain a fourth matrix and a fifth matrix; and performing finite field multiplication and addition operation on the fourth matrix and the fifth matrix based on matrix multiplication to obtain a seventh matrix. According to the scheme, addition, subtraction, multiplication and division operation of a rational number field is converted into XOR and AND operation of a finite field, and the operation performance is greatly improved.

Description

Technical Field

[0001] The present disclosure relates to the field of electronic digital data processing, and in particular to a matrix multiplication fast calculation method, device, equipment and storage medium. Background Art

[0002] Matrix multiplication is a core technology for data processing and is widely used in communications, image processing, and scientific computing. With the development of technologies such as big data and artificial intelligence, the performance and power consumption of matrix operations have become very important. Large matrix multiplication consumes a lot of resources and has a large delay. In order to calculate matrix multiplication, people have proposed a variety of optimization schemes. For matrices with different characteristics, the proposed optimization schemes are also different. Finite field matrices have special elements. Each element in this matrix is ​​an element in a finite field, and the operation of the elements also follows the operation rules of the finite field. In communication, coding, and encryption systems, matrix operations in finite fields are more common.

[0003] In the prior art, no matter whether the matrix is ​​stored in the memory in a row-first storage format or a column-first storage format, when the cache memory takes a row of matrix A or a column of matrix B from the main memory, a large number of cache memory misses will occur on one side due to discontinuous addresses. One method is to divide the matrix into blocks for operation, but there is still a problem of high complexity. In the prior art, no optimization algorithm for matrix multiplication in finite fields has been found. Summary of the invention

[0004] The present disclosure provides a matrix multiplication fast calculation method, device, equipment and storage medium to at least solve the above technical problems existing in the prior art.

[0005] According to a first aspect of the present disclosure, a fast matrix multiplication calculation method is provided, the method comprising: Based on different storage locations, respectively determine a first matrix and a third matrix; Acquire an actual bit width of a processor, and compress the first matrix and the third matrix based on the actual bit width to obtain a fourth matrix and a fifth matrix; A finite field multiplication and addition operation is performed on the fourth matrix and the fifth matrix by using matrix multiplication to obtain a seventh matrix.

[0006] In one possible implementation, the determining the first matrix and the third matrix respectively based on different storage locations includes: Based on different storage locations, respectively determining the first matrix and the second matrix; Reading storage formats of the first matrix and the second matrix respectively; Determine dimension information of the first matrix and the second matrix based on the storage format, and determine whether the first matrix and the second matrix comply with a matrix multiplication operation rule based on the dimension information; If the matrix multiplication operation rule is not met, an error message is generated; If the matrix multiplication operation rule is met, the storage format of the second matrix is ​​transposed based on the matrix multiplication rule to obtain a third matrix.

[0007] In one possible implementation manner, obtaining the actual bit width of the processor includes: The actual number of bytes of the single data is measured based on the first keyword, and the actual bit width of the processor is calculated based on the actual number of bytes of the single data.

[0008] In one embodiment, the method further comprises: Determine a first data amount based on memory sizes occupied by the first matrix and the second matrix; The memory required for the fourth matrix and the fifth matrix is ​​calculated based on the actual bit width and the first data amount, the second data amount is determined based on the required memory, and memory space is allocated to the fourth matrix and the fifth matrix based on the second data amount.

[0009] In one possible implementation, compressing the first matrix and the third matrix based on the actual bit width includes: dividing the column index of the first matrix into a first bit index and a first other column index; Reading a first bit index of the first matrix based on a column index thereof, and calculating a bit index of a compressed fourth matrix based on the first bit index and the actual bit width; Reading a first other column index therein based on the column index of the first matrix, and calculating other column indexes of a compressed fourth matrix based on the first other column index and the actual bit width; Constructing the fourth matrix based on the bit index of the fourth matrix and other column indexes of the fourth matrix; Dividing the index of the third matrix into a third bit index and a third other index; Reading a third bit index of the third matrix based on the column index thereof, and calculating a bit index of a compressed fifth matrix based on the third bit index and the actual bit width; Reading a third other column index therein based on the column index of the third matrix, and calculating other column indexes of the compressed fifth matrix based on the third other column index and the actual bit width; The fifth matrix is ​​constructed based on the bit index of the fifth matrix and other column indexes of the fifth matrix.

[0010] In one possible implementation, the fourth matrix and the fifth matrix perform a finite field multiplication and addition operation based on matrix multiplication to obtain a seventh matrix, including: Performing a finite field multiplication and addition operation on the fourth matrix and the fifth matrix by using matrix multiplication to obtain a sixth matrix; Based on finite field addition, each bit of data in the sixth matrix is ​​added to obtain a seventh matrix.

[0011] In one possible implementation manner, the fourth matrix and the fifth matrix perform a finite field multiplication and addition operation based on matrix multiplication to obtain a sixth matrix, including: Selecting corresponding rows in the fourth matrix and the fifth matrix, and performing a bitwise AND operation on the selected corresponding elements in the corresponding rows; An XOR operation is performed on the elements after the bitwise AND operation to obtain the sixth matrix.

[0012] According to a second aspect of the present disclosure, a matrix multiplication fast calculation device is provided, the device comprising: A data input and output module, used to determine the first matrix and the third matrix respectively based on different storage locations; A matrix compression module, used for obtaining an actual bit width of a processor, and compressing the first matrix and the third matrix based on the actual bit width to obtain a fourth matrix and a fifth matrix; The matrix operation module is used to perform finite field multiplication and addition operations on the fourth matrix and the fifth matrix by using matrix multiplication to obtain a seventh matrix.

[0013] In one embodiment, the device further comprises: A parameter configuration module, used to determine the first matrix and the second matrix respectively based on different storage locations; read the storage formats of the first matrix and the second matrix respectively; determine the dimension information of the first matrix and the second matrix based on the storage formats, and judge whether the first matrix and the second matrix conform to the matrix multiplication operation rules based on the dimension information; if they do not conform to the matrix multiplication operation rules, generate an error message; A matrix transposition module, used for transposing the storage format of the second matrix based on a matrix multiplication rule to obtain a third matrix; The data input and output module is further configured to determine a first data volume based on the memory size occupied by the first matrix and the second matrix; calculate the memory required for the fourth matrix and the fifth matrix based on the actual bit width and the first data volume, determine a second data volume based on the required memory, and allocate memory space for the fourth matrix and the fifth matrix based on the second data volume. In one embodiment, the matrix compression unit further includes: The processor bit width calculation module is used to measure the actual number of bytes of a single data based on the first keyword, and calculate the actual bit width of the processor based on the actual number of bytes of the single data.

[0014] In one possible implementation, the matrix compression module is also used to divide the column index of the first matrix into a first bit index and a first other column index; read the first bit index based on the column index of the first matrix, and calculate the bit index of the compressed fourth matrix based on the first bit index and the actual bit width; read the first other column index based on the column index of the first matrix, and calculate the other column index of the compressed fourth matrix based on the first other column index and the actual bit width; construct the fourth matrix based on the bit index of the fourth matrix and the other column index of the fourth matrix; divide the index of the third matrix into a third bit index and a third other index; read the third bit index based on the column index of the third matrix, and calculate the bit index of the compressed fifth matrix based on the third bit index and the actual bit width; read the third other column index based on the column index of the third matrix, and calculate the other column index of the compressed fifth matrix based on the third other column index and the actual bit width; construct the fifth matrix based on the bit index of the fifth matrix and the other column index of the fifth matrix.

[0015] In one possible implementation manner, the matrix operation module is further used to perform a finite field multiplication and addition operation on the fourth matrix and the fifth matrix using matrix multiplication to obtain a sixth matrix; The matrix operation module includes: a matrix accumulation module, which is used to add each bit of data in the sixth matrix based on finite field addition to obtain a seventh matrix.

[0016] In one possible implementation, the matrix operation module further includes: a matrix multiplication module, configured to select corresponding rows in the fourth matrix and the fifth matrix, and perform a bitwise AND operation on the selected corresponding elements in the corresponding rows; The matrix accumulation module is further used to perform an XOR operation on the elements after the bitwise AND operation to obtain the sixth matrix.

[0017] According to a third aspect of the present disclosure, there is provided an electronic device, including: at least one processor; and a memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the method described in the present disclosure.

[0018] According to a fourth aspect of the present disclosure, a non-transitory computer-readable storage medium storing computer instructions is provided, wherein the computer instructions are used to cause the computer to execute the method described in the present disclosure.

[0019] The present invention discloses a fast matrix multiplication calculation method, device, equipment and storage medium. Before performing matrix multiplication, the storage order of matrix multiplication is adjusted by transposing the matrix stored in row priority, the cache hit rate is improved, and matrix compression is performed. The compressed matrix is ​​subjected to XOR and AND operations to obtain the calculation results of the two matrices before transposition. A scheme of compression before operation is proposed and optimized, which greatly improves the utilization rate of hardware resources, converts addition, subtraction, multiplication and division operations in the rational number domain into XOR and AND operations in the finite domain, greatly improves the operation performance, and at the same time, adjusts the calculation order, and no longer needs to restore the compressed matrix.

[0020] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present disclosure, nor is it intended to limit the scope of the present disclosure. Other features of the present disclosure will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The above and other objects, features and advantages of the exemplary embodiments of the present disclosure will become readily understood by reading the detailed description below with reference to the accompanying drawings. In the accompanying drawings, several embodiments of the present disclosure are shown in an exemplary and non-limiting manner, in which: In the drawings, the same or corresponding reference numerals represent the same or corresponding parts.

[0022] Figure 1 The schematic diagram shows the implementation process of a fast matrix multiplication calculation method according to the embodiment of the present disclosure. Figure 1 ; Figure 2 The schematic diagram shows the implementation process of a fast matrix multiplication calculation method according to the embodiment of the present disclosure. Figure 2 ; Figure 3 The schematic diagram shows the implementation process of a fast matrix multiplication calculation method according to the embodiment of the present disclosure. Figure 3 ; Figure 4 The present disclosure is a schematic diagram of an overall implementation scheme of matrix multiplication in an embodiment; Figure 5 A schematic diagram showing a specific implementation scheme of matrix compression in an embodiment of the present disclosure is shown; Figure 6 A schematic diagram showing a specific implementation scheme of matrix element grouping calculation in an embodiment of the present disclosure is shown; Figure 7 A schematic diagram of a fast matrix multiplication calculation device according to an embodiment of the present disclosure is shown. Figure 1 ; Figure 8 A schematic diagram of a fast matrix multiplication calculation device according to an embodiment of the present disclosure is shown. Figure 2 ; Fig. 9 A schematic diagram of the structure of an electronic device according to an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0023] In order to make the purpose, features, and advantages of the present disclosure more obvious and easy to understand, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present disclosure.

[0024] In the prior art, the finite field gf(2) has only two elements, 0 and 1, and follows the following operation rules: a+b=ab=a^b, addition and subtraction operations can be converted into XOR operations; a×b=a&b, multiplication operations can be converted into AND operations; Assume that A is an m n matrix, B is an n p matrix, multiply the two matrices to get the matrix C as an m The matrix of p follows the following rules:

[0025] That is, the element indexed (i, j) in the C matrix is ​​equal to the corresponding multiplication of all elements in the i-th row of the A matrix and all elements in the j-th column of the B matrix, and finally the results are added. Generally, to calculate matrix multiplication, it is necessary to traverse the rows of the A matrix, the columns of the B matrix, and the elements corresponding to the two rows and columns. Therefore, due to the closed nature of finite field operations, matrix multiplication can be processed in parallel.

[0026] Figure 1 The schematic diagram shows the implementation process of a fast matrix multiplication calculation method according to the embodiment of the present disclosure. Figure 1 ;like Figure 1 As shown, a fast matrix multiplication calculation method according to an embodiment of the present disclosure includes the following steps: Step 101: Determine a first matrix and a third matrix based on different storage locations.

[0027] In an embodiment of the present disclosure, a first matrix and a second matrix are respectively determined based on different storage locations; wherein the matrix generally adopts a row-first storage format, and the storage formats of the first matrix and the second matrix are respectively read; dimension information of the first matrix and the second matrix is ​​determined based on the storage format, and whether the first matrix and the second matrix comply with the matrix multiplication operation rules is judged based on the dimension information; if the matrix multiplication operation rules are not complied with, an error message is generated, wherein the error message is used to prompt the system to report an error; if the matrix multiplication operation rules are complied with, the matrix calculation needs to read an entire row of the first matrix and an entire column of the second matrix respectively, so in order to improve the cache hit rate, based on the matrix multiplication rule, the storage format of the second matrix is ​​transposed to obtain a third matrix.

[0028] In an embodiment of the present disclosure, the actual number of bytes of a single data is measured based on a first keyword, wherein the first keyword may be a data type length function (sizeof) keyword, and the actual bit width of the processor is calculated based on the actual number of bytes of the single data, specifically, the actual bit width is obtained by multiplying the measured actual number of bytes of the single data by 8.

[0029] In the disclosed embodiment, the memory size occupied by the storage of the first matrix and the second matrix is ​​obtained, which is recorded as the first data amount; the memory required for the fourth matrix and the fifth matrix is ​​calculated based on the actual bit width and the first data amount, which is recorded as the second data amount, and memory space is allocated to the fourth matrix and the fifth matrix based on the second data amount. Among them, since the fourth matrix and the fifth matrix are matrices after the first matrix and the third matrix are compressed, and the matrix compression is based on the actual bit width of the processor, the data size of the compressed fourth matrix and the fifth matrix can be calculated using the actual bit width according to the data size of the first matrix and the third matrix before compression, that is, the first data size. The corresponding memory space is allocated according to the size of the second data amount.

[0030] Step 102: Obtain an actual bit width of a processor, and compress the first matrix and the third matrix based on the actual bit width to obtain a fourth matrix and a fifth matrix.

[0031] In an embodiment of the present disclosure, the correspondence between the matrix before and after compression is determined, and matrix compression is achieved according to the correspondence between the matrix elements before and after compression, specifically: the column index of the first matrix element is divided into two parts: a first bit index and a first other column index; based on the column index of the first matrix, the first bit index is read as the bit index of the matrix element after compression, and the bit index of the compressed fourth matrix is ​​calculated based on the first bit index and the actual bit width, indicating the bit of the first matrix element before compression in the corresponding element of the compressed fourth matrix; based on the column index of the first matrix, the first other column index is read, that is, the column index remaining after removing the bit index, and the other column indexes of the compressed fourth matrix are calculated based on the first other column index and the actual bit width, indicating which elements of the first matrix before compression are included in the fourth matrix element after compression; and the fourth matrix is ​​constructed based on the bit index of the fourth matrix and the other column indexes of the fourth matrix.

[0032] In the embodiment of the present disclosure, the compression method of the third matrix is ​​the same as the compression method of the first matrix mentioned above: dividing the index of the third matrix into a third bit index and a third other index; reading the third bit index based on the column index of the third matrix, and calculating the bit index of the compressed fifth matrix based on the third bit index and the actual bit width; reading the third other column index based on the column index of the third matrix, and calculating the other column index of the compressed fifth matrix based on the third other column index and the actual bit width; constructing the fifth matrix based on the bit index of the fifth matrix and the other column index of the fifth matrix.

[0033] Step 103: Perform finite field multiplication and addition operations on the fourth matrix and the fifth matrix using matrix multiplication to obtain a seventh matrix.

[0034] In the disclosed embodiment, matrix multiplication is used to perform finite field multiplication and addition operations on the fourth matrix and the fifth matrix to obtain a sixth matrix; specifically: corresponding rows in the fourth matrix and the fifth matrix are selected, and the corresponding elements in the corresponding rows are subjected to bitwise AND operations (AND operations are equivalent to multiplication operations in the gf(2) finite field); the elements after the bitwise AND operations are subjected to XOR operations (in the finite field, addition operations are equivalent to XOR operations) to obtain the sixth matrix. Based on finite field addition, each bit of data in the sixth matrix is ​​added to obtain the seventh matrix. In the actual implementation process, the initial value of the XOR operation is assigned to 0, and each time a result of the AND operation is obtained, it is added to the result of the previous XOR operation using the XOR operation.

[0035] In an embodiment of the present disclosure, a first matrix, a second matrix, a third matrix, a fourth matrix, a fifth matrix, a sixth matrix and a seventh matrix may be stored in a random access memory (RAM), wherein matrices having a conversion relationship may be stored in the same RAM, specifically: the first matrix and the fourth matrix are stored in the same RAM, the second matrix, the third matrix and the fifth matrix are stored in the same RAM, and the sixth matrix and the seventh matrix are stored in the same RAM.

[0036] Figure 2 The schematic diagram shows the implementation process of a fast matrix multiplication calculation method according to the embodiment of the present disclosure. Figure 2 ,like Figure 2 As shown, a fast matrix multiplication calculation method according to an embodiment of the present disclosure includes the following steps: Step 201, adjusting the matrix.

[0037] In the disclosed embodiment, in order to improve the cache hit rate, the matrix storage format must be changed first. First, the input matrix A and matrix B are received through the configured interface, and the dimensions of matrix A and matrix B are read, where the number of rows of A is row_A, the number of columns of A is col_A; the number of rows of B is row_B, the number of columns of B is col_B. In order to comply with the operation rules of matrix multiplication, it is necessary to ensure that: col_A=row_B.

[0038] In the disclosed embodiment, assuming that the matrix adopts a row-first storage format, then calculating an element in the C matrix requires reading an entire row row_A of the A matrix and an entire column col_B of the B matrix. Due to the row-first storage method, a continuous section of data in an entire row row_A of the matrix A can be loaded into the cache and can be used for matrix multiplication, that is, the cache hit rate of the matrix A is very high. For the matrix B, each time a row row_B is read, only one number is used, and the cache hit rate of the B matrix is ​​very low. A method to improve the cache hit rate of the B matrix is ​​to transpose the B matrix before using it. That is, when calculating the matrix multiplication, the transposed matrix of B is used instead of directly using the B matrix. Here, the transposed matrix of the B matrix is ​​recorded as B_rev. Therefore, the method of calculating C(i,j) becomes, the method of operating the i-th row col_A of the matrix A and the j-th column col_B of the matrix B is changed to the operation between the i-th row col_A of the matrix A and the j-th row_B of the matrix B_rev.

[0039] Step 202, compress the matrix.

[0040] In the disclosed embodiment, since both A and B_rev are operated in rows, a method of first compressing and then calculating can be used. The principle is as follows: the elements in gf(2) can be represented by 1 bit, and the operations in gf(2) are also completed within this 1 bit, and there will be no carry phenomenon. However, the processor inside the computer stores and operates according to 32 bits or 64 bits, so the 1-bit operation a^b in gf(2) will be converted into a 32-bit operation in the processor, which will lead to a large waste of computing resources in the processor. We assume that the CPU bit width is 32 bits. In the process of matrix multiplication, the main operation is performed in units of rows, which requires operations to be performed on the entire row and the entire row. Therefore, the data in a row can be divided into a group of 32, and each group of data can be compressed into one data in the computer. The processor's one-bit operation can complete the operation of 32 data in the matrix, so the processor resources are fully utilized and the computing performance is greatly improved.

[0041] In the disclosed embodiment, preferably, the storage space with address 1 is regarded as a 32-bit cache space for storing compressed data. Only the lowest bit in the input data is valid, and the lowest bit is intercepted and placed in the corresponding position in the 32-bit cache space. That is, the valid bit of the first data is stored in the first bit of the cache space, the valid bit of the second data is placed in the second bit of the cache space, and so on. When the storage space with address 1 is full, go to the next address (address 2), which is regarded as a new 32-bit cache space to store the next 32 data. So when the matrix input is completed, the data after matrix compression will be stored.

[0042] Step 203: group calculation.

[0043] In the disclosed embodiment, when calculating each C(i, j), there are a total of 2n numbers, and n multiplication operations and n-1 addition operations are performed. Since the CPU calculates 32 data at a time, these 2n numbers can be grouped. For example, the n numbers of matrix A are divided into groups of 32 numbers each, and matrix B is grouped in the same way. When calculating matrix multiplication, first calculate the multiplication between the corresponding group elements of matrix A and matrix B, and then add these 32 elements and the 32 elements after the corresponding elements are multiplied according to the corresponding elements in the group. After all groups have completed the operation, 32 elements are obtained, and finally these 32 elements are added together to obtain the final C(i, j). Assume that matrix A is compressed to cA with a dimension of m (n / 32); after compression, the matrix B_rev is cB_rev, with a dimension of p (n / 32), then C(i,j) is expressed as:

[0044] Among them, cA(i,kb,b) represents the b-th bit of the ikb-th element of the cA matrix, and the corresponding relationship between cA and A is: ,in, .

[0045] Figure 3 The schematic diagram shows the implementation process of a fast matrix multiplication calculation method according to the embodiment of the present disclosure. Figure 3 , Figure 4 FIG. 2 shows a schematic diagram of an overall implementation scheme of matrix multiplication in an embodiment of the present disclosure. Figure 4 and Figure 3 The implementation process in corresponds to Figure 3 As shown, the implementation process of a fast matrix multiplication calculation method in the embodiment of the present disclosure includes the following steps: Step 301, transpose the matrix B to obtain B_rev.

[0046] In the embodiment of the present disclosure, before transposing the matrix B, the data input and output interfaces need to be configured first, specifically: configuration interface: input the dimensions of the matrix A: the number of rows of A row_A, the number of columns of A col_A; input the dimensions of the matrix B: the number of rows of B row_B, the number of columns of B col_B. According to the operation rules of matrix multiplication, col_A=row_B is required; data input interface: 32 bits, that is, a 32-bit data is input in each clock cycle, and the data of the matrix A is input, and a total of row_A is input. col_A data. Input the data of matrix B, a total of row_B col_B data. Data output interface: 32 bits, that is, one 32-bit data is output in each clock cycle; output matrix C data, a total of row_A col_B data.

[0047] In the embodiment of the present disclosure, the dimensions of matrix A and matrix B are received, and if col_A and row_B are not equal, an error is reported. If the amount of data in the input matrix is ​​not equal to the corresponding dimension, an error is reported.

[0048] In the disclosed embodiment, the matrix data can be stored in a random access memory (RAM), specifically: three RAMs store matrix A, matrix B and matrix C, namely: RAM_A, RAM_B, RAM_C, with a width of 32 bits. That is, one address can store a 32-bit data.

[0049] In the disclosed embodiment, since the default storage format is row-major, it is necessary to first transpose the matrix B so that when the matrix A and the matrix B perform a matrix multiplication operation, the cache hit rate is improved.

[0050] Step 302: compress the matrix A and the matrix B_rev according to the processor bit width to obtain matrices cA and cB_rev.

[0051] In the disclosed embodiment, first determine the processor bit width, denoted as size_bint; the sizeof keyword can be used to measure the actual number of bytes of the variable, multiplied by 8 to obtain the actual bit width, and it is assumed here that size_bint is 32; secondly, allocate memory space to construct the compressed matrix. Among them, it is necessary to first read the memory space occupied by matrices A and B, and calculate the memory space required for the compressed matrices cA and cB_rev according to the actual bit width of the processor and the memory space occupied by matrices A and B. The number of rows of the matrix after compression is the same as that of the matrix before compression, and the number of columns of the matrix after compression is 1 / 32 of the matrix before compression. After the matrix is ​​compressed, one number in the matrix represents 32 numbers in the original matrix.

[0052] In the disclosed embodiment, Figure 5 The schematic diagram of the specific implementation scheme of matrix compression in the embodiment of the present disclosure is shown. The specific operations include: the correspondence between the matrix elements before and after compression is that the column index of the matrix element before compression is divided into two parts, where the last 5 bits (log2size_bint=log232=5) are used as the bit index of the matrix element after compression, representing the bit of the matrix element before compression in the corresponding element of the matrix after compression. The remaining part of the column index of the matrix before compression can be used as the column index of the matrix element after compression, representing which elements of the matrix before compression are included in the matrix element after compression; the correspondence between the matrix elements can be expressed by the following C code: cop_mat_a[i cop_c+j / size_bint]+=Bmat_A[i ca_rb+j]<<(j%size_bint) Among them, cop_mat_a represents the compressed matrix A, and Bmat_A represents the uncompressed matrix A. i is the row index, j is the column index, ca_rb represents the number of columns of matrix A and the number of rows of matrix B, and cop_c is equal to ca_rb / size_bint. This line of code means that the corresponding elements of matrix Bmat_A are first shifted left and then added to cop_mat_a.

[0053] In the disclosed embodiment, the compressed matrix A data is sent to RAM_A, and the compressed / transposed matrix B data is sent to RAM_B.

[0054] In the disclosed embodiment, the valid bits in the input data are intercepted and stored in the corresponding bit positions. The specific method is: take the storage space with address 1 in RAM_A as a 32-bit cache space to store the compressed data. Only the lowest bit in the input data is valid, intercept the lowest bit, and put it in the corresponding position in the 32-bit cache space. That is, the valid bit of the first data is stored in the first bit of the cache space, the valid bit of the second data is placed in the second bit of the cache space, and so on. When the storage space with address 1 in RAM_A is full, go to the next address of RAM (address 2), regard it as a new 32-bit cache space, and store the next 32 data. So when the input of matrix A is completed, RAM_A will store the compressed data of matrix A, intercept the valid bits of the 32-bit data, and store this 1-bit data in RAM_B. When the input of matrix B is completed, RAM_B stores the data after matrix B is compressed and transposed.

[0055] Step 303, calculating the multiplication of the compressed matrix.

[0056] In the disclosed embodiment, data at corresponding addresses in RAM_A and RAM_B are read out, and an AND operation is performed on corresponding bits.

[0057] In the disclosed embodiment, the corresponding rows of the cA matrix and the cB_rev matrix should be selected at this time, and finite field multiplication and addition operations should be performed according to matrix multiplication. After the calculation is completed, the matrix element cC(i,j) is obtained, specifically: take the i-th row of the matrix cA and the j-th row of the matrix cB_rev, and select the corresponding elements in each row to perform a bitwise AND operation (the AND operation is equivalent to the multiplication operation in the gf(2) finite field). Note that here cA and cB_rev are compressed matrices, and each element in these two matrices represents the 32 elements of the original matrix. Since the original two matrices follow the same compression scheme, the bitwise AND operation of the compressed matrix elements will not change the corresponding relationship between the original matrix elements.

[0058] Step 304: Use finite field addition to add up each bit of the matrix element cC(i,j).

[0059] In the disclosed embodiment, two types of XOR operations are involved, one is to perform XOR operations on corresponding bits, and the other is to perform XOR operations on 32 bits together. Based on the result of the above XOR operation, the new data is added to the old data until the cumulative number of additions reaches row_A / 32, and then the accumulated result is XORed on 32 bits together. The operation result is 1 bit, and the operation result is stored in the corresponding bit in RAM_C.

[0060] In the disclosed embodiment, the elements after the bitwise AND operation are accumulated. In the finite field, the addition operation is equivalent to the XOR operation. That is, the data after the AND operation is subjected to the bitwise XOR operation. In the actual implementation process, the initial value of the XOR operation is assigned to 0, and each time a result of the AND operation is obtained, it is added to the result of the previous XOR operation using the XOR operation.

[0061] In the disclosed embodiment, the above calculated result has 32 bits, which can be understood as dividing the result of the bitwise AND operation of the original matrix into 32 groups, performing an XOR operation inside each group, and finally obtaining 32 numbers. Finally, it is necessary to perform an XOR operation on these 32 numbers again to finally obtain a 1-bit calculation result. This 1 bit is C(i, j) in practice. In the actual implementation process, the initial value of the XOR operation is assigned to 0, and each time a result of the AND operation is obtained, it is added to the result of the previous XOR operation using an XOR operation.

[0062] In the embodiment of the present disclosure, after both matrix A and matrix B are input, matrix calculation is started, data in RAM_A and RAM_B are read out, and functions of multiplication according to corresponding elements and accumulation according to rows are performed, and then the operation results are stored in RAM_C.

[0063] Figure 6 A schematic diagram of a specific implementation scheme for grouping matrix elements in an embodiment of the present disclosure is shown, including the relevant contents of steps 303 and 304 described above.

[0064] In the disclosed embodiment, preferably, if the matrix dimension does not exceed the RAM storage upper limit, hardware is used to perform matrix multiplication; if it exceeds, an error is reported, indicating that the hardware cannot execute and software is used for calculation.

[0065] In the disclosed embodiment, a calculation method for matrix multiplication on a finite field gf(2) is proposed, which converts addition, subtraction, multiplication and division operations in the rational number field into XOR and AND operations in the finite field, greatly improving the calculation performance; the data in a row of the matrix is ​​divided into a group of 32 data, and each group of data is compressed into one data in the computer. A single bit operation of the processor can complete the operation of 32 data in the matrix, thereby making full use of the processor resources and greatly improving the calculation performance; at the same time, it includes an implementation method of group calculation, and it is no longer necessary to restore the compressed matrix.

[0066] Figure 7 A schematic diagram of a fast matrix multiplication calculation device according to an embodiment of the present disclosure is shown. Figure 1 ,like Figure 7 As shown, a matrix multiplication fast calculation device according to an embodiment of the present disclosure includes: A data input and output module 701 is used to determine the first matrix and the third matrix respectively based on different storage locations; The data input and output module 701 is also used to determine a first data amount based on the memory size occupied by the first matrix and the second matrix; calculate the memory required for the fourth matrix and the fifth matrix based on the actual bit width and the first data amount, determine the second data amount based on the required memory, and allocate memory space for the fourth matrix and the fifth matrix based on the second data amount.

[0067] A matrix compression module 702 is used to obtain an actual bit width of a processor, and compress the first matrix and the third matrix based on the actual bit width to obtain a fourth matrix and a fifth matrix; The matrix compression module 702 is also used to divide the column index of the first matrix into a first bit index and a first other column index; read the first bit index based on the column index of the first matrix, and calculate the bit index of the compressed fourth matrix based on the first bit index and the actual bit width; read the first other column index based on the column index of the first matrix, and calculate the other column index of the compressed fourth matrix based on the first other column index and the actual bit width; construct the fourth matrix based on the bit index of the fourth matrix and the other column index of the fourth matrix; divide the index of the third matrix into a third bit index and a third other index; read the third bit index based on the column index of the third matrix, and calculate the bit index of the compressed fifth matrix based on the third bit index and the actual bit width; read the third other column index based on the column index of the third matrix, and calculate the other column index of the compressed fifth matrix based on the third other column index and the actual bit width; construct the fifth matrix based on the bit index of the fifth matrix and the other column index of the fifth matrix.

[0068] The matrix compression module 702 and the matrix transposition module 705 constitute a matrix reorganization module 709 .

[0069] The matrix operation module 703 performs a finite field multiplication and addition operation on the fourth matrix and the fifth matrix by using matrix multiplication to obtain a seventh matrix.

[0070] The matrix operation module 703 is further used to perform a finite field multiplication and addition operation on the fourth matrix and the fifth matrix using matrix multiplication to obtain a sixth matrix; The parameter configuration module 704 is used to receive the first matrix and the second matrix respectively based on different storage locations; read the storage formats of the first matrix and the second matrix respectively; determine the dimension information of the first matrix and the second matrix based on the storage formats, and determine whether the first matrix and the second matrix comply with the matrix multiplication operation rules based on the dimension information; if they do not comply with the matrix multiplication operation rules, generate error information; A matrix transposition module 705, configured to transpose the storage format of the second matrix based on a matrix multiplication rule to obtain a third matrix; The processor bit width calculation module 706 is used to measure the actual number of bytes of a single data based on the first keyword, and calculate the actual bit width of the processor based on the actual number of bytes of the single data.

[0071] The matrix operation module 703 includes: a matrix accumulation module 707, which is used to add each bit of data in the sixth matrix based on finite field addition to obtain a seventh matrix.

[0072] The matrix accumulation module 707 is further used to perform an XOR operation on the elements after the bitwise AND operation to obtain the sixth matrix.

[0073] The matrix operation module 703 also includes: a matrix multiplication module 708, which is used to select corresponding rows in the fourth matrix and the fifth matrix, and perform a bitwise AND operation on the selected corresponding elements in the corresponding rows.

[0074] Figure 8 A schematic diagram of a fast matrix multiplication calculation device according to an embodiment of the present disclosure is shown. Figure 2 ,like Figure 8 As shown, a schematic diagram of a matrix fast calculation device according to an embodiment of the present disclosure includes: The data input and output module 701 is used to receive matrix data, count the data quantity, and pass the input data to the matrix reorganization module 709. After receiving the operation completion signal sent by the matrix operation module 703, the data in the RAM_C module 712 is sent out.

[0075] The parameter configuration module 704 is used to receive the dimensions of the matrix A and the matrix B, and report an error if col_A and row_B are not equal. If the amount of data in the input matrix is ​​not equal to the corresponding dimension, report an error.

[0076] The parameter configuration module 704 may also pass the matrix dimensions to the matrix reorganization module 709 and the matrix operation module 703 .

[0077] Matrix reorganization module 709: The matrix reorganization module 709 is composed of a matrix compression module 702 and a matrix transposition module 705. If the input matrix is ​​matrix A, the matrix compression function is performed, and the compressed data is sent to the RAM_A module 710. If the input matrix is ​​matrix B, the matrix compression and matrix transposition functions are performed, and the compressed / transposed data is sent to the RAM_B module 711.

[0078] The matrix operation module 703 is used to start the matrix calculation after the matrix A and the matrix B are input. The matrix calculation is composed of the matrix multiplication module 708 and the matrix accumulation module 707. The data in the RAM_A module 710 and the RAM_B module 711 are read out, and the corresponding element multiplication and row accumulation functions are performed, and then the operation results are stored in the RAM_C module 712.

[0079] The RAM_A module 710 is used to store the matrix A, and has a width of 32 bits, that is, one address can store a 32-bit data.

[0080] RAM_B module 711 is used to store matrix B, and has a width of 32 bits, that is, one address can store a 32-bit data.

[0081] The RAM_C module 712 is used to store the matrix C, and has a width of 32 bits, that is, one address can store a 32-bit data.

[0082] In the embodiment of the present disclosure, when the hardware performs matrix multiplication, parameter configuration is required first, namely: configuration interface: input the dimensions of matrix A: the number of rows of A row_A, the number of columns of A col_A; input the dimensions of matrix B: the number of rows of B row_B, the number of columns of B col_B. According to the operation rules of matrix multiplication, col_A=row_B is required; data input interface: 32 bits, that is, a 32-bit data is input in each clock cycle, and the data of matrix A is input, and row_A is input in total. col_A data. Input the data of matrix B, a total of row_B col_B data. Data output interface: 32 bits, that is, one 32-bit data is output in each clock cycle; output matrix C data, a total of row_A col_B data.

[0083] In the disclosed embodiment, after the hardware completes parameter configuration, the relevant data is input, that is, the matrix A is compressed and stored, and the matrix B is compressed and transposed and then stored. Specifically, the matrix reorganization module 709 with only compression function: intercepts the valid bits in the input data and stores them in the corresponding bit position. The specific method is: take the storage space with address 1 in the RAM_A module 710 as a 32-bit cache space for storing compressed data. Only the lowest bit in the input data is valid, intercept the lowest bit, and put it in the corresponding position in the 32-bit cache space. That is, the valid bit of the first data is stored in the first bit of the cache space, and the valid bit of the second data is placed in the second bit of the cache space, and so on. When the storage space with address 1 in the RAM_A module 710 is full, go to the next address of the RAM (address 2), regard it as a new 32-bit cache space, and store the next 32 data. So when the input of matrix A is completed, the RAM_A module 710 will store the compressed data of matrix A.

[0084] In the embodiment of the present disclosure, the compression and transposition function of the matrix reorganization module 709 is used to process the matrix B, specifically: intercepting the effective bit of the 32-bit data, storing the 1-bit data in the RAM_B module 711, and the position stored in the RAM_B module 711 is calculated by the matrix transposition module 705. When the input of the matrix B is completed, the data of the matrix B after compression and transposition is stored in the RAM_B module 711.

[0085] The matrix multiplication module 708 is also used to read out the data of the corresponding addresses in the RAM_A module 710 and the RAM_B module 711, and perform an AND operation according to the corresponding bits, and send the obtained results to the matrix accumulation module 707. Specifically, take the i-th row of the matrix cA and the j-th row of the matrix cB_rev, select the corresponding elements in each row to perform a bitwise AND operation (the AND operation is equivalent to the multiplication operation in the gf(2) finite field). At this time, cA and cB_rev are compressed matrices, and each element in these two matrices represents the 32 elements of the original matrix. Since the original two matrices follow the same compression scheme, the bitwise AND operation of the compressed matrix elements will not change the corresponding relationship between the original matrix elements.

[0086] The matrix accumulation module 707 is also used to perform two addition functions, one is to perform an XOR operation according to the corresponding bit position, and the other is to perform an XOR operation on 32 bits together. Receive the data of the matrix multiplication module 708, and add the new data to the old data until the number of accumulations reaches row_A / 32, and then perform an XOR operation on the accumulated result together with 32 bits. The operation result is 1 bit, and the operation result is stored in the corresponding bit position in the RAM_C module 712. Specifically: add up the elements after the bitwise AND operation. In the finite field, the addition operation is equivalent to the XOR operation. That is, perform a bitwise XOR operation on the data after the AND operation. Assign 0 to the initial value of the XOR operation. Each time a result of the AND operation is obtained, it is added to the result of the previous XOR operation using an XOR operation. The above-mentioned accumulated result has 32 bits, which can be understood as dividing the result of the bitwise AND operation of the original matrix into 32 groups, performing an XOR operation inside each group, and finally obtaining 32 numbers. Finally, these 32 numbers need to be XORed again to get a 1-bit calculation result. This 1-bit is C(i,j) in practice. In the actual implementation process, the initial value of the XOR operation is assigned to 0, and each time a result of the AND operation is obtained, it is added to the result of the previous XOR operation using the XOR operation.

[0087] In the disclosed embodiment, after completing the data input, the matrix C is calculated internally and stored, and then the data is output.

[0088] In an exemplary embodiment, the data input and output module 701, the matrix compression module 702, the matrix operation module 703, the parameter configuration module 704, the matrix transposition module 705, the processor bit width calculation module 706, the matrix accumulation module 707, the matrix multiplication module 708, the matrix reorganization module 709, the RAM_A module 710, the RAM_B module 711 and the RAM_C module 712 can be implemented by one or more central processing units (CPU), graphics processing units (GPU), application specific integrated circuits (ASIC), DSP, programmable logic devices (PLD), complex programmable logic devices (CPLD), field programmable gate arrays (FPGA), general-purpose processors, controllers, microcontrollers (MCU), microprocessors, or other electronic components.

[0089] Regarding the device in the above embodiment, the specific manner in which each module and unit performs operations has been described in detail in the embodiment of the method, and will not be elaborated here.

[0090] According to an embodiment of the present disclosure, the present disclosure also provides an electronic device and a readable storage medium.

[0091] Fig. 9 A schematic block diagram of an example electronic device 800 that can be used to implement an embodiment of the present disclosure is shown. The electronic device 800 is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device 800 can also represent various forms of mobile devices, such as personal digital processing, cellular phones, smart phones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the present disclosure described and / or required herein.

[0092] like Fig. 9 As shown, the electronic device 800 includes a computing unit 801, which can perform various appropriate actions and processes according to a computer program stored in a read-only memory (ROM) 802 or a computer program loaded from a storage unit 808 to a random access memory (RAM) 803. In the random access memory (RAM) 803, various programs and data required for the operation of the electronic device 800 can also be stored. The computing unit 801, the read-only memory (ROM) 802, and the random access memory (RAM) 803 are connected to each other via a bus 804. An input / output (I / O) interface 805 is also connected to the bus 804.

[0093] Multiple components in the electronic device 800 are connected to an input / output (I / O) interface 805, including: an input unit 806, such as a keyboard, a mouse, etc.; an output unit 807, such as various types of displays, speakers, etc.; a storage unit 808, such as a disk, an optical disk, etc.; and a communication unit 809, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 809 allows the electronic device 800 to exchange information / data with other devices through a computer network such as the Internet and / or various telecommunication networks.

[0094] The computing unit 801 may be a variety of general and / or special processing components with processing and computing capabilities. Some examples of the computing unit 801 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various dedicated artificial intelligence (AI) computing chips, various computing units 801 running machine learning model algorithms, digital signal processors (DSPs), and any appropriate processors, controllers, microcontrollers, etc. The computing unit 801 performs the various methods and processes described above, such as a fast matrix multiplication calculation method. For example, in some embodiments, a fast matrix multiplication calculation method may be implemented as a computer software program, which is tangibly contained in a machine-readable medium, such as a storage unit 808. In some embodiments, part or all of the computer program may be loaded and / or installed on the electronic device 800 via a read-only memory (ROM) 802 and / or a communication unit 809. When the computer program is loaded into a random access memory (RAM) 803 and executed by the computing unit 801, one or more steps of a fast matrix multiplication calculation method described above may be performed. Alternatively, in other embodiments, the computing unit 801 may be configured to execute a fast matrix multiplication computing method in any other appropriate manner (eg, by means of firmware).

[0095] Various implementations of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on chips (SOCs), load programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various implementations can include: being implemented in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which can be a special purpose or general purpose programmable processor that can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, the at least one input device, and the at least one output device.

[0096] The program code for implementing the method of the present disclosure may be written in any combination of one or more programming languages. These program codes may be provided to a processor or controller of a general-purpose computer, a special-purpose computer, or other programmable data processing device, so that the program code, when executed by the processor or controller, enables the functions / operations specified in the flow chart and / or block diagram to be implemented. The program code may be executed entirely on the machine, partially on the machine, partially on the machine and partially on a remote machine as a stand-alone software package, or entirely on a remote machine or server.

[0097] In the context of the present disclosure, a machine-readable medium may be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, device, or equipment. A machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, device, or device, or any suitable combination of the foregoing. A more specific example of a machine-readable storage medium may include an electrical connection based on one or more lines, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0098] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user can provide input to the computer. Other types of devices can also be used to provide interaction with the user; for example, the feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including acoustic input, voice input, or tactile input).

[0099] The systems and techniques described herein may be implemented in a computing system that includes back-end components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes front-end components (e.g., a user computer with a graphical user interface or a web browser through which a user can interact with implementations of the systems and techniques described herein), or a computing system that includes any combination of such back-end components, middleware components, or front-end components. The components of the system may be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: a local area network (LAN), a wide area network (WAN), and the Internet.

[0100] A computer system may include a client and a server. The client and the server are generally remote from each other and usually interact through a communication network. The relationship of client and server is generated by computer programs running on respective computers and having a client-server relationship with each other. The server may be a cloud server, a server of a distributed system, or a server combined with a blockchain.

[0101] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps recorded in this disclosure can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solutions disclosed in this disclosure can be achieved, and this document does not limit this.

[0102] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of the features. In the description of the present disclosure, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0103] The above is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art who is familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A fast matrix multiplication calculation method, characterized in that: The method comprises: Based on different storage locations, respectively determine a first matrix and a third matrix; Acquire an actual bit width of a processor, and compress the first matrix and the third matrix based on the actual bit width to obtain a fourth matrix and a fifth matrix; A finite field multiplication and addition operation is performed on the fourth matrix and the fifth matrix by using matrix multiplication to obtain a seventh matrix.

2. The method according to claim 1, characterized in that The determining the first matrix and the third matrix respectively based on different storage locations includes: Based on different storage locations, respectively determining the first matrix and the second matrix; Reading storage formats of the first matrix and the second matrix respectively; Determine dimension information of the first matrix and the second matrix based on the storage format, and determine whether the first matrix and the second matrix comply with a matrix multiplication operation rule based on the dimension information; If the matrix multiplication operation rule is not met, an error message is generated; If the matrix multiplication operation rule is met, the storage format of the second matrix is ​​transposed based on the matrix multiplication rule to obtain a third matrix.

3. The method according to claim 1, characterized in that The obtaining the actual bit width of the processor includes: The actual number of bytes of the single data is measured based on the first keyword, and the actual bit width of the processor is calculated based on the actual number of bytes of the single data.

4. The method according to claim 2, characterized in that: The method further comprises: Determine a first data amount based on memory sizes occupied by the first matrix and the second matrix; The memory required for the fourth matrix and the fifth matrix is ​​calculated based on the actual bit width and the first data amount, the second data amount is determined based on the required memory, and memory space is allocated to the fourth matrix and the fifth matrix based on the second data amount.

5. The method according to claim 1, characterized in that The compressing the first matrix and the third matrix based on the actual bit width includes: dividing the column index of the first matrix into a first bit index and a first other column index; Reading a first bit index of the first matrix based on a column index thereof, and calculating a bit index of a compressed fourth matrix based on the first bit index and the actual bit width; Reading a first other column index therein based on the column index of the first matrix, and calculating other column indexes of a compressed fourth matrix based on the first other column index and the actual bit width; Constructing the fourth matrix based on the bit index of the fourth matrix and other column indexes of the fourth matrix; Dividing the index of the third matrix into a third bit index and a third other index; Reading a third bit index of the third matrix based on the column index thereof, and calculating a bit index of a compressed fifth matrix based on the third bit index and the actual bit width; Reading a third other column index therein based on the column index of the third matrix, and calculating other column indexes of the compressed fifth matrix based on the third other column index and the actual bit width; The fifth matrix is ​​constructed based on the bit index of the fifth matrix and other column indexes of the fifth matrix.

6. The method according to claim 1, characterized in that The method of performing a finite field multiplication and addition operation on the fourth matrix and the fifth matrix by matrix multiplication to obtain a seventh matrix includes: Performing a finite field multiplication and addition operation on the fourth matrix and the fifth matrix by using matrix multiplication to obtain a sixth matrix; Based on finite field addition, each bit of data in the sixth matrix is ​​added to obtain a seventh matrix.

7. The method according to claim 6, characterized in that The method of performing a finite field multiplication and addition operation on the fourth matrix and the fifth matrix by matrix multiplication to obtain a sixth matrix includes: Selecting corresponding rows in the fourth matrix and the fifth matrix, and performing a bitwise AND operation on the selected corresponding elements in the corresponding rows; An XOR operation is performed on the elements after the bitwise AND operation to obtain the sixth matrix.

8. A matrix multiplication fast calculation device, characterized in that: The device comprises: A data input and output module, used for respectively determining the first matrix and the third matrix based on different storage locations; A matrix compression module, used for obtaining an actual bit width of a processor, and compressing the first matrix and the third matrix based on the actual bit width to obtain a fourth matrix and a fifth matrix; The matrix operation module is used to perform finite field multiplication and addition operations on the fourth matrix and the fifth matrix by using matrix multiplication to obtain a seventh matrix.

9. The device according to claim 8, characterized in that The device also includes: a parameter configuration module, configured to respectively determine the first matrix and the second matrix based on different storage locations; respectively read the storage formats of the first matrix and the second matrix; determine the dimension information of the first matrix and the second matrix based on the storage formats, and determine whether the first matrix and the second matrix comply with the matrix multiplication operation rules based on the dimension information; and generate an error message if they do not comply with the matrix multiplication operation rules; A matrix transposition module, used for transposing the storage format of the second matrix based on a matrix multiplication rule to obtain a third matrix; The data input and output module is also used to determine a first data amount based on the memory size occupied by the first matrix and the second matrix; calculate the memory required for the fourth matrix and the fifth matrix based on the actual bit width and the first data amount, determine the second data amount based on the required memory, and allocate memory space for the fourth matrix and the fifth matrix based on the second data amount.

10. The device according to claim 8, characterized in that The matrix compression module also includes: The processor bit width calculation module is used to measure the actual number of bytes of a single data based on the first keyword, and calculate the actual bit width of the processor based on the actual number of bytes of the single data.

11. The device according to claim 8, characterized in that The matrix compression module is further used to divide the column index of the first matrix into a first bit index and a first other column index; read the first bit index therein based on the column index of the first matrix, and calculate the bit index of the compressed fourth matrix based on the first bit index and the actual bit width; read the first other column index therein based on the column index of the first matrix, and calculate the other column indexes of the compressed fourth matrix based on the first other column index and the actual bit width; Constructing the fourth matrix based on the bit index of the fourth matrix and other column indexes of the fourth matrix; dividing the index of the third matrix into a third bit index and a third other index; Based on the column index of the third matrix, a third bit index is read therein, and based on the third bit index and the actual bit width, a bit index of the compressed fifth matrix is ​​calculated; based on the column index of the third matrix, a third other column index is read therein, and based on the third other column index and the actual bit width, other column indexes of the compressed fifth matrix are calculated; The fifth matrix is ​​constructed based on the bit index of the fifth matrix and other column indexes of the fifth matrix.

12. The device according to claim 8, characterized in that The matrix operation module is further used to perform a finite field multiplication and addition operation on the fourth matrix and the fifth matrix using matrix multiplication to obtain a sixth matrix; The matrix operation module includes: a matrix accumulation module, which is used to add each bit of data in the sixth matrix based on finite field addition to obtain a seventh matrix.

13. The device according to claim 12, characterized in that The matrix operation module also includes: a matrix multiplication module, which is used to select corresponding rows in the fourth matrix and the fifth matrix, and perform a bitwise AND operation on the selected corresponding elements in the corresponding rows; The matrix accumulation module is further used to perform an XOR operation on the elements after the bitwise AND operation to obtain the sixth matrix.

14. An electronic device, characterized in that: include: at least one processor; as well as a memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the method according to any one of claims 1 to 7.

15. A non-transitory computer-readable storage medium storing computer instructions, characterized in that: The computer instructions are used to enable a computer to execute the method according to any one of claims 1-7.

Images