Reference model passive update verification system and method
By using the passively updated reference model verification system in chip verification, the difficulty of timing alignment caused by increasing chip complexity is solved, and a more efficient verification process and lower working pressure is achieved.
Patent Information
- Application Number
- CN202411604438.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-12
- Publication Date
- 2025-03-04
AI Technical Summary
In chip design, as the chip complexity increases, the timing logic becomes complex, making it difficult to align the reference model with the DUT timing, increasing verification difficulty and workload.
Provide a passive update verification system and method for reference model, sampling the input and output results of DUT through the monitor, and updating the data of the design simulator to be tested based on the sampling results, reducing the time when the reference model is aligned with the DUT timing.
This method can reduce the time of writing reference model, reduce the workload of timing alignment, improve work efficiency, reduce the work pressure of engineers, quickly locate problems and find solutions.
Smart Images
Figure CN119558240A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of storage, and in particular to a reference model passive update verification system and method. Background Art
[0002] In chip design, timing is indispensable. As the complexity of chips increases exponentially, the timing logic also becomes more complex, which undoubtedly increases the difficulty of verification for chip verification engineers. More and more modules need to align timing during the verification process to make the calculation results in the reference model consistent with the results in the scoreboard (comparison), otherwise the comparison may be wrong. It is more difficult to align the timing between the reference model and the DUT, and if the DUT is modified with a bug, the timing will change, resulting in a larger change in the reference model. Verification personnel need to spend more time to align the DUT timing, which is costly and seriously affects work efficiency.
[0003] Due to the increase in module complexity, almost most modules require more or less functional checks when using the UVM verification environment for verification. Timing alignment is required to make the results calculated by the reference model consistent with the logical results of the DUT. Otherwise, the check cannot be successful. There are many problems with timing alignment, which makes verification more difficult. For example, if a bug is found during the verification process, the DUT has to modify the code to cause a change in timing, and the reference model needs to be re-adapted. The difficulty may be greater than the DUT change, which will inevitably increase the workload of verification and affect the project progress. Summary of the invention
[0004] In view of the defects of the prior art, the present invention provides a reference model passive update verification system and method, which changes the reference model according to the results of DUT sampling, helps to reduce the reference model writing time, improve work efficiency, and reduce the workload.
[0005] In order to solve the technical problem, the technical solution adopted by the present invention is: a reference model passive update verification system, including a design to be tested, a driver, a monitor, a design to be tested simulator and a comparator, the driver is connected to the input end of the design to be tested, and is used to input a test stimulus to the design to be tested, the input end of the monitor is respectively connected to the input end and the output end of the design to be tested, and is used to sample the test stimulus at the input end of the design to be tested and the execution result at the output end, the output end of the monitor is respectively connected to the design to be tested simulator and the comparator, and is used to transmit the sampled test stimulus and execution result to the design to be tested simulator and the comparator, the output end of the design to be tested simulator is connected to the input end of the comparator, and the data transmitted to the comparator by the design to be tested simulator is determined according to the sampling result of the design to be tested; After receiving the test stimulus, the simulator of the design under test maintains the initial state value, recorded as data0, and then processes it according to the sampled test stimulus. The processed result is recorded as data1, and the execution result sampled by the monitor from the output end of the design under test is recorded as data2. Data2 is transmitted to the simulator of the design under test and compared with data0. If data2 is the same as data0, the simulator of the design under test sends data2 to the comparator. If data2 is different from data0, data1 replaces the value of data2 and sends it to the comparator. The comparator compares the data sent from the simulator of the design under test with the data used from the output end of the design under test to confirm whether there is a bug in the actual test.
[0006] Furthermore, an assertion check is added in the simulator of the design under test, and the assertion check determines that if data2 does not change within a set clock cycle, an error is reported.
[0007] Furthermore, the device under test is a DUT.
[0008] The present invention also discloses a reference model passive update verification method, which is implemented based on the above system and includes the following steps: S01, the driver transmits the test stimulus to the inside of the design under test through the input end of the design under test for processing; S02, the monitor samples the test stimulus of the driver from the input end of the design under test, and transmits the sampled data to the simulator and comparator of the design under test, and at the same time the monitor samples at the output end of the design under test, and sends the sampled data to the simulator and comparator of the design under test; S03, after receiving the input test stimulus, the simulator of the design under test first keeps the initial value, recorded as data0, and then processes it according to the received test stimulus, and the processed result is recorded as data1; S04. The execution result sampled by the monitor from the output end of the design under test is recorded as data2. Data2 is transmitted to the simulator of the design under test for comparison with data0. If data2 is the same as data0, the simulator of the design under test sends data2 to the comparator. If data2 is different from data0, data1 replaces the value of data2 and sends it to the comparator. The comparator compares the data sent from the simulator of the design under test with the data used from the output end of the design under test to confirm whether there is a bug in the actual design under test.
[0009] Furthermore, an assertion check is added in the simulator of the design under test, and if data2 does not change within a set clock cycle, the assertion check reports an error.
[0010] Furthermore, the device under test is a DUT.
[0011] The beneficial effects of the present invention are as follows: it saves the time for writing reference models, reduces the time spent on aligning reference models with DUT timing, and reduces the work pressure of engineers. It can help engineers locate problems more quickly and more effectively, find solutions more quickly, and improve work efficiency. BRIEF DESCRIPTION OF THE DRAWINGS
[0012] Figure 1 This is a functional block diagram of the system described in Example 1; Figure 2 This is a flow chart of the method described in Example 2. DETAILED DESCRIPTION
[0013] The present invention will be further described below in conjunction with the accompanying drawings and specific embodiments.
[0014] Example 1 This embodiment discloses a reference model passive update verification system, such as Figure 1As shown, it includes a design under test DUT, a driver driver, a monitor moniter, a simulator reference model of the design under test and a comparator scoreboard. The driver driver is connected to the input end of the design under test DUT, and is used to input a test stimulus to the design under test. The input end of the monitor moniter is respectively connected to the input end and the output end of the design under test DUT, and is used to sample the test stimulus at the input end of the design under test DUT and the execution result at the output end. The output end of the monitor moniter is respectively connected to the simulator reference model of the design under test and the comparator scoreboard, and is used to transmit the sampled test stimulus and execution result to the simulator reference model of the design under test and the comparator scoreboard, and the output end of the simulator reference model of the design under test is connected to the input end of the comparator scoreboard.
[0015] In this embodiment, the monitor moniter can simultaneously sample the test stimulus at the input end and the execution result at the output end of the design under test DUT, and send the test stimulus and the execution result to the reference model of the simulator of the design under test and the comparator scoreboard at the same time. Since the reference model of the simulator of the design under test has a fast data processing speed, it will cause the output result to be faster when processing some instructions, but the DUT fails to complete the processing. At this time, reading the internal data of the DUT cannot accurately give the processed data, which will cause the reference model data of the simulator of the design under test and the output data of the DUT to fail to match successfully, resulting in a check error, but this does not mean that there is a bug in the DUT, because the processing speed of the reference model of the simulator of the design under test is faster, and the DUT has not yet completed the processing and gives an unprocessed result (that is, the state has not changed). To address this problem, after receiving the test stimulus, the reference model of the simulator of the design under test maintains the initial state value, recorded as data0, and then processes it according to the sampled test stimulus. The processed result is recorded as data1, and the execution result sampled by the monitor moniter from the output end of the design under test is recorded as data2. Data2 is passed to the reference model of the simulator of the design under test and compared with data0. If data2 is the same as data0, the reference model of the simulator of the design under test sends data2 to the comparator scoreboard. If data2 is different from data0, data1 replaces the value of data2 and then sends it to the comparator scoreboard. The comparator scoreboard compares the data sent from the reference model of the simulator of the design under test with the data used from the output end of the design under test, so as to confirm whether there is a bug in the actual test. This embodiment can change the reference model of the simulator of the design under test according to the results of DUT sampling, and it can be checked.
[0016] Changing the reference model of the DUT simulator based entirely on the results of DUT sampling can effectively reduce the work of timing alignment, but it will also cause some other problems during the verification process. For example, if there is a bug in the DUT and the state cannot be changed, the results given by the reference model of the DUT simulator will also be consistent, which will cause the bug to be unable to be discovered or the environment to be stuck. In order to avoid this problem, assertions are used to assert how many clock cycles are required for the state change. If the DUT does not change within this clock cycle, an error is directly reported, and the existence of the bug can be discovered in time. The implementation method is to add an assertion check in the DUT simulator. The assertion check determines that if data2 does not change within the set clock cycle, an error is reported.
[0017] In this embodiment, the reference model refers to a function used to simulate the design under test and send the result to the scoreboard. The scoreboard is mainly used to compare whether the output results of the reference model and the design under test (DUT or DUT) are consistent and give the comparison result.
[0018] Example 2 This embodiment discloses a reference model passive update verification method, such as Figure 2 Said, comprising the following steps: S01, the driver transmits the test stimulus to the inside of the design under test through the input end of the design under test for processing; S02, the monitor samples the test stimulus of the driver from the input end of the design under test, and transmits the sampled data to the simulator and comparator of the design under test, and at the same time the monitor samples at the output end of the design under test, and sends the sampled data to the simulator and comparator of the design under test; S03, after receiving the input test stimulus, the simulator of the design under test first keeps the initial value, recorded as data0, and then processes it according to the received test stimulus, and the processed result is recorded as data1; S04. The execution result sampled by the monitor from the output end of the design under test is recorded as data2. Data2 is transmitted to the simulator of the design under test for comparison with data0. If data2 is the same as data0, the simulator of the design under test sends data2 to the comparator. If data2 is different from data0, data1 replaces the value of data2 and sends it to the comparator. The comparator compares the data sent from the simulator of the design under test with the data used from the output end of the design under test to confirm whether there is a bug in the actual design under test.
[0019] In this embodiment, an assertion check is added in the simulator of the design under test. If data2 does not change within a set clock cycle, the assertion check reports an error.
[0020] In this embodiment, the device under test is a DUT.
[0021] In a general verification environment, the result of DUT calculation is sent to the scoreboard, but not to the referencemodel. In the verification environment of the present invention, the result of DUT is sent to the reference model, and then the result of its own calculation is replaced with the result in the referencemodel, and then sent to the scoreboard. Whether to replace the result of DUT with the result of referencemodel calculation is determined by the verification personnel, because in many cases, the register state value of the design will not change when reading one or several beats, but the reference model calculates quickly, and the state of DUT will not change before the processing is completed. If the value is modified at this time, there will definitely be a comparison error, because at this time the value output by DUT is the original state value and has not changed. This kind of comparison error is not expected to occur, so it is generally necessary to align with the design code when the beat changes, which is more troublesome. If there is a bug, the environment must be modified after the design is modified, so the reference model decides when to modify the state and then transmits it. Since the reference model can get the result of DUT output, it can determine when the output state of DUT changes, and then my referencemodel also changes and then transmits the result, so the above problems can be avoided and the time spent on timing alignment of referencemodel and DUT can be reduced.
[0022] The above assertion is a check. It is mentioned above that the reference model determines the timing of transmitting the calculated result based on the result obtained by the DUT. If the result output by the DUT remains unchanged, then my reference model will have to wait all the time, which will cause the environment to freeze or other problems. The assertion means that it can be judged that if the result output by the DUT does not change within a few beats, an error will be reported, which means that there is a problem with the DUT calculation and it has not met expectations.
[0023] The above description is only the basic principle and preferred embodiments of the present invention. Improvements and substitutions made by those skilled in the art based on the present invention belong to the protection scope of the present invention.
Claims
1. A reference model passive update verification system, characterized by: It includes a design to be tested, a driver, a monitor, a simulator for the design to be tested and a comparator. The driver is connected to the input end of the design to be tested and is used to input a test stimulus to the design to be tested. The input end of the monitor is respectively connected to the input end and the output end of the design to be tested and is used to sample the test stimulus at the input end of the design to be tested and the execution result at the output end. The output end of the monitor is respectively connected to the simulator for the design to be tested and the comparator and is used to transmit the sampled test stimulus and execution result to the simulator for the design to be tested and the comparator. The output end of the simulator for the design to be tested is connected to the input end of the comparator and the data transmitted to the comparator by the simulator for the design to be tested is determined according to the sampling of the design to be tested. After receiving the test stimulus, the simulator of the design under test maintains the initial state value, recorded as data0, and then processes it according to the sampled test stimulus. The processed result is recorded as data1, and the execution result sampled by the monitor from the output end of the design under test is recorded as data2. Data2 is transmitted to the simulator of the design under test and compared with data0. If data2 is the same as data0, the simulator of the design under test sends data2 to the comparator. If data2 is different from data0, data1 replaces the value of data2 and sends it to the comparator. The comparator compares the data sent from the simulator of the design under test with the data used from the output end of the design under test to confirm whether there is a bug in the actual test.
2. The reference model passive update verification system according to claim 1, characterized in that: An assertion check is added to the simulator of the design under test. The assertion check determines that if data2 does not change within the set clock cycle, an error is reported.
3. The reference model passive update verification system according to claim 1, characterized in that: The design under test is DUT.
4. A reference model passive update verification method, which is implemented based on the system described in claim 1, and is characterized by: The following steps are involved: S01, the driver transmits the test stimulus to the inside of the design under test through the input end of the design under test for processing; S02, the monitor samples the test stimulus of the driver from the input end of the design under test, and transmits the sampled data to the simulator and comparator of the design under test, and at the same time the monitor samples at the output end of the design under test, and sends the sampled data to the simulator and comparator of the design under test; S03, after receiving the input test stimulus, the simulator of the design under test first keeps the initial value, recorded as data0, and then processes it according to the received test stimulus, and the processed result is recorded as data1; S04. The execution result sampled by the monitor from the output end of the design under test is recorded as data2. Data2 is transmitted to the simulator of the design under test for comparison with data0. If data2 is the same as data0, the simulator of the design under test sends data2 to the comparator. If data2 is different from data0, data1 replaces the value of data2 and sends it to the comparator. The comparator compares the data sent from the simulator of the design under test with the data used from the output end of the design under test to confirm whether there is a bug in the actual design under test.
5. The reference model passive update verification method according to claim 4, characterized in that: Add an assertion check in the simulator of the design under test. If data2 does not change within the set clock cycle, the assertion check will report an error.
6. The reference model passive update verification method according to claim 4, characterized in that: The design under test is DUT.