Skew calibration method and device for parallel bus and medium

Abstract

The invention discloses a deflection calibration method and device for a parallel bus and a medium, and relates to the technical field of communication, and the method comprises the steps: receiving an instruction and test data from an upper computer through a processor, sending the instruction to a controller, and analyzing the instruction through the controller to output a control signal; inputting the control signal and the test data to a PAD port, carrying out a loopback test through the PAD port to obtain a test result, and comparing the test result with the test data; if the test result is the same as the test data, the deflection is normal. According to the invention, self-transmitting and self-receiving are carried out through the ports in the chip, deflection between the ports is automatically calibrated, the phase margin of the clock and the data is improved, the design circuit is simple, the cost is relatively low, transplantation is convenient, and requirements in different scenes can be met.

Description

Technical Field

[0001] The present application relates to the field of communication technology, and in particular to a method, device and medium for skew calibration of a parallel bus. Background Art

[0002] In the design of electronic systems, the design of buses and clocks is crucial. As two basic technologies, parallel buses and serial buses each play an important role. Parallel buses can transmit multiple bits of data at the same time, so they have higher transmission efficiency. However, since parallel buses contain multiple signal lines, in order to reduce the skew between signals, equal length processing is usually required during PCB wiring.

[0003] In a source synchronous bus with a high signal rate, not only the delay time of the clock and data lines is required to be consistent, but also the delay time between the data lines is required to be consistent. Therefore, when routing the PCB, equal length processing can often meet most communication needs. However, in high-speed transmission scenarios, in addition to equal length of PCB traces, the impact of skew between ports must also be considered. For interfaces with higher transmission rates, such as BT656 and BT1120, their electrical standards do not clearly specify the amplitude, impedance, delay time and other parameters of the parallel interface transmitter and receiver. This leads to a lack of clear requirements for equal length errors when engineers design PCBs, which may cause insufficient clock and data phase margin when transmitting data in these parallel buses. Summary of the invention

[0004] In order to solve the above problems, the present application proposes a skew calibration method for a parallel bus, including: receiving instructions and test data from a host computer through a processor, sending the instructions to a controller, and parsing the instructions through the controller to output a control signal; inputting the control signal and the test data into a PAD port to perform a loopback test through the PAD port to obtain a test result, and comparing the test result with the test data; if the test result is the same as the test data, it indicates that the skew is normal.

[0005] In one example, the controller parses the instruction to output a control signal, specifically including: generating multiple control signals according to the instruction, the control signals including an enable signal, a clock control signal, and a data control signal; sending the enable signal to a multiplexer to enable the multiplexer; sending the clock control signal to a clock delay to turn on the clock delay; sending the data control signal to a data delay to turn on the data delay.

[0006] In one example, the control signal and the test data are input into the PAD port, specifically including: sending the test data to a buffer, sending the test data to the data delayer through the buffer, so as to obtain output data through the data delayer; obtaining an output clock through the clock delayer, and inputting the output clock and the output data into the PAD port.

[0007] In one example, a loopback test is performed through the PAD port, specifically including: the PAD port includes a clock PAD port and a data PAD port; the output clock is received through the DO end of the clock PAD port, and the PAD clock is output through the DI segment of the clock PAD port; the output data is received through the DO end of the data PAD port, and the PAD data is output through the DI segment of the data PAD port; the PAD data is sent to a trigger so that the trigger outputs the test result according to the rising edge of the PAD clock.

[0008] In one example, the method also includes: determining a preset data delay and clock delay, and setting the PAD port according to the data delay and the clock delay; aligning the clock edge with the data center, and determining the test data and the multiplexed output value of the PAD port, and comparing the test data and the multiplexed output value; if the test data is equal to the multiplexed output value, reducing the value of the clock delay according to a preset value, or increasing the value of the data delay according to a preset value, and resetting the PAD port according to the reduced clock delay or the increased data delay; if the test data is not equal to the multiplexed output value, taking the corresponding data delay as the skew difference of the PAD port.

[0009] In one example, the method further includes: determining a right boundary and a left boundary according to a preset clock delay, determining a selection range according to the right boundary and the left boundary, and determining a delay value in the selection range; and skew compensating a data port of the PAD port according to the delay value.

[0010] In one example, the right boundary is determined according to a preset clock delay, specifically including: determining test data and multiplexed output values ​​of multiple ports, and comparing the test data with the multiplexed output values; if the test data and the multiplexed output values ​​corresponding to all ports are not equal, reporting an error message to the processor; if the test data and the multiplexed output values ​​corresponding to one or more ports are equal, increasing the delay time of the PAD port according to a preset value; if the test data and the multiplexed output values ​​corresponding to one or more ports are not equal, using the corresponding clock delay as the right boundary.

[0011] In one example, the left boundary is determined according to a preset clock delay, specifically including: determining test data and multiplexed output values ​​of multiple ports, and comparing the test data with the multiplexed output values; if the test data and the multiplexed output values ​​corresponding to all ports are not equal, reporting an error message to the processor; if the test data and the multiplexed output values ​​corresponding to one or more ports are equal, reducing the delay time of the PAD port according to a preset value; if the test data and the multiplexed output values ​​corresponding to one or more ports are not equal, using the corresponding clock delay as the left boundary.

[0012] On the other hand, the present application also proposes a skew calibration device for a parallel bus, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor so that the skew calibration device for the parallel bus can execute: receiving instructions and test data from a host computer through the processor, sending the instructions to a controller, and parsing the instructions through the controller to output a control signal; inputting the control signal and the test data into a PAD port to perform a loopback test through the PAD port to obtain a test result, and comparing the test result with the test data; if the test result is the same as the test data, it indicates that the skew is normal.

[0013] On the other hand, the present application also proposes a non-volatile computer storage medium storing computer executable instructions, wherein the computer executable instructions are configured to: receive instructions and test data from a host computer through a processor, send the instructions to a controller, and parse the instructions through the controller to output a control signal; input the control signal and the test data into a PAD port to perform a loopback test through the PAD port to obtain a test result, and compare the test result with the test data; if the test result is the same as the test data, it indicates that the skew is normal.

[0014] The present application uses the ports inside the chip to transmit and receive automatically, automatically calibrates the skew between ports, improves the phase margin of the clock and data, and has a simple circuit design, low cost, and easy transplantation, which can meet the needs of different scenarios. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings: Figure 1 A schematic diagram of a flow chart of a skew calibration method for a parallel bus in an embodiment of the present application; Figure 2 This is a structural schematic diagram of a skew calibration system for a parallel bus in an embodiment of the present application; Figure 3 A schematic diagram of a loopback test for skew calibration in an embodiment of the present application; Figure 4 It is a schematic diagram of a skew calibration device for a parallel bus in an embodiment of the present application. DETAILED DESCRIPTION

[0016] In order to make the purpose, technical solution and advantages of the present application clearer, the technical solution of the present application will be clearly and completely described below in combination with the specific embodiments of the present application and the corresponding drawings. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present application.

[0017] The technical solutions provided by various embodiments of the present application are described in detail below in conjunction with the accompanying drawings.

[0018] like Figure 1 As shown, in order to solve the above problems, a parallel bus skew calibration method provided in an embodiment of the present application is applied in a parallel bus skew calibration system, such as Figure 2As shown, the system includes a PAD port, a delay module (Delay), a control module (Control), a CPU core (Core) and a host computer module (PC), and the method includes: S101, receiving instructions and test data from a host computer through a processor, sending the instructions to a controller, and parsing the instructions through the controller to output a control signal.

[0019] The PAD port is configured in bidirectional mode. In normal operation mode, if data needs to be output, the output enable OE is activated; if data needs to be input, the input enable IE is activated. When any enable is disabled, the subsequent signal will remain in a high-impedance state. In normal mode, OE and IE are in an interlocked state, that is, when one enable is valid, the other is invalid. When entering the loop test mode, the output of the interconnected device is set to a high-impedance state, and this application involves the PAD port of data and clock, and its OE and IE will be activated at the same time.

[0020] The delay module is responsible for receiving data from the transmit register or loop test data, delaying the data before transmitting it to the external PAD port. The delay time is regulated by the control module, which divides the width of 1 bit of data into 254 equal parts. By selecting the register to set the value between 0 and 255, different delay times can be achieved. The maximum delay is equivalent to the width of 1 bit of data.

[0021] The control module is responsible for receiving the instructions and loop test data sent by the processor core, setting the delay time of the clock delay module and the data delay module accordingly, and controlling the selection switch of the multiplexer. In addition, it is also responsible for receiving the data returned by the trigger D1 during the loop test.

[0022] The CPU core works in coordination with the host computer module. The host computer first sends the loop test command through the USB interface, and then sends the manual verification or automatic verification selection command of the loop test. After receiving and parsing the instructions from the host computer, the CPU core sends the data to the send buffer register or the control module, and receives the feedback data from the control module at the same time. Based on these feedback data, the CPU core calculates the skew value of each port and sets the appropriate delay time for each data port accordingly.

[0023] In one embodiment, Figure 3 As shown in the figure, the host computer sends instructions and test data to the processor through the USB interface. After receiving these data, the processor core first parses them and then transmits the test data PB_DATA[7:0] to the buffer TX buffer through the AHB bus. At the same time, the processor core also sends corresponding instructions to the control module.

[0024] After receiving the instruction, the control module will output an enable signal Looptest_EN to the multiplexer MUX and set the signal to 1. In addition, it will also output a control signal Lcontrol[8:0] to the clock delay module CLKdelay, and the value of this signal is set to 128. For each data delay module Data delay, the control signal output by the data control module is Dcontrol[8:0], and its value is set to 0, which means that the clock delay module will delay half of the 1-bit data width to ensure that the data is output first, and the clock is delayed afterwards, so that the clock edge is aligned with the center of the data.

[0025] S102: Input the control signal and the test data to a PAD port to perform a loopback test through the PAD port to obtain a test result, and compare the test result with the test data.

[0026] After being processed by the MUX and the delay module Data delay, the data to be sent PB_DATA[7:0] is output as out_data and sent to the PAD port. At the same time, the reference clock PB_CLK is output as out_clk after being implemented by the clock delay CLK delay and is also sent to the PAD port.

[0027] When the output enable OE and input enable IE of the clock PAD port are activated at the same time, the clock signal out_clk will form a loop inside the CLK PAD port: it is input from the DO end and then output from the DI end as PAD_CLK. Similarly, in the data PAD port, when the output enable OE and input enable IE are activated at the same time, the data signal out_data will also be input from the DO end and output from the DI end as PAD_data, thus forming a loop inside the DATA PAD port.

[0028] PAD_data then enters the input of trigger D1, and when triggered by the rising edge of PAD_CLK, the trigger outputs looptest_data.

[0029] S103. If the test result is the same as the test data, it indicates that the skew is normal.

[0030] The looptest_data is then fed into the control module and compared with the original PB_DATA[7:0]. If the two are identical, then the port skew is normal in the initialization state.

[0031] In one embodiment, the skew between data ports is calibrated. The PAD ports to be tested are selected and their input and output enable are turned on at the same time to ensure that the PAD is in loopback mode. Then, the data delay setting Dcontrol[7:0] of all ports is set to 0, and the clock port delay setting Lcontrol[7:0] is set to 128 to achieve alignment of the clock edge with the data center.

[0032] Then, compare the loop test data looptest_data[7:0] and Mux_out[7:0] of each port to see if they are equal. If the two sets of data of all ports are equal, gradually reduce the clock port delay value Lcontrol[7:0], such as decreasing by one each time, and continue to compare until the two sets of data of a port are not equal.

[0033] When an inequality is found, the port number and Dcontrol[7:0] value of the current failed comparison are recorded as Dcontrol_x_fail, and the current clock port delay value Lcontrol[7:0] is recorded as Lcontrol_fail.

[0034] For other successful comparison ports, keep their Lcontrol values ​​unchanged, but gradually increase their Dcontrol[7:0] values, such as adding one each time, and continue to compare. If looptest_data[7:0] is equal to Mux_out[7:0], continue to increase the Dcontrol[7:0] value; if a new port fails to compare, record the port number and its Dcontrol[7:0] value. This process continues until all ports fail to compare, at which time the skew calibration between data ports is completed.

[0035] Finally, the data delay value Dcontrol_x_fail of each port reflects the skew difference between the data ports.

[0036] In one embodiment, before calibrating the skew of the clock port and the data port, the right and left boundaries of the clock delay are confirmed.

[0037] First, configure the data delay value Dcontrol[7:0] of each data port to the data skew calibration value Dcontrol_x_fail, and initialize the clock port delay value Lcontrol[7:0] to 128. Then, compare whether the looptest_data[7:0] and Mux_out[7:0] of each port are equal. If they are not equal, report an error to the processor core; if they are equal, gradually increase the value of Lcontrol[7:0] by one each time. After each increase, compare again. When the looptest_data[7:0] and Mux_out[7:0] of a port are not equal, record the current Lcontrol[7:0] value as Lcontrol_right, which is determined to be the right boundary of the clock delay.

[0038] The process of determining the right boundary is similar, but in the opposite direction. Similarly, configure the data delay value Dcontrol[7:0] of each data port to Dcontrol_x_fail, and initialize the clock port delay value Lcontrol[7:0] to 128. Compare the looptest_data[7:0] and Mux_out[7:0] of each port to see if they are equal. If they are not equal, report an error; if they are equal, gradually reduce the value of Lcontrol[7:0] by one each time. After each reduction, compare again. When the looptest_data[7:0] and Mux_out[7:0] of a port are not equal, it should be noted that Lcontrol_left should be recorded here as the left boundary of the clock delay.

[0039] Through the above process, the left and right boundaries of the clock delay can be determined.

[0040] In one embodiment, according to the left and right boundary values ​​of the clock port delay obtained by the test, a moderate delay value is selected within this range for setting. At the same time, the data delay value Dcontrol_x_fail of each data port actually performs skew compensation on the data port. Such compensation enables a larger phase margin between the data port and the clock port, thereby improving the integrity of the transmission signal.

[0041] like Figure 4 As shown, the embodiment of the present application also provides a skew calibration device for a parallel bus, including: at least one processor; and, a memory communicatively connected to at least one processor; wherein, The memory stores instructions executable by at least one processor, the instructions being executed by the at least one processor to enable a skew calibration device for a parallel bus to perform: The processor receives instructions and test data from the host computer, sends the instructions to the controller, and parses the instructions through the controller to output a control signal; Inputting the control signal and the test data into a PAD port to perform a loopback test through the PAD port to obtain a test result, and comparing the test result with the test data; If the test result is the same as the test data, it means that the skew is normal.

[0042] The embodiment of the present application further provides a non-volatile computer storage medium storing computer executable instructions, wherein the computer executable instructions are configured as follows: The processor receives instructions and test data from the host computer, sends the instructions to the controller, and parses the instructions through the controller to output a control signal; Inputting the control signal and the test data into a PAD port to perform a loopback test through the PAD port to obtain a test result, and comparing the test result with the test data; If the test result is the same as the test data, it means that the skew is normal.

[0043] In the 1990s, it was very clear whether the improvement of a technology was hardware improvement (for example, improvement of the circuit structure of diodes, transistors, switches, etc.) or software improvement (improvement of the method flow). However, with the development of technology, many improvements of the method flow today can be regarded as direct improvements of the hardware circuit structure. Designers almost always obtain the corresponding hardware circuit structure by programming the improved method flow into the hardware circuit. Therefore, it cannot be said that the improvement of a method flow cannot be implemented with hardware entity modules. For example, a programmable logic device (PLD) (such as a field programmable gate array (FPGA)) is such an integrated circuit whose logical function is determined by the user's programming of the device. Designers can "integrate" a digital system on a PLD by programming it themselves, without having to ask chip manufacturers to design and make dedicated integrated circuit chips. Moreover, nowadays, instead of manually making integrated circuit chips, this kind of programming is mostly implemented by "logic compiler" software, which is similar to the software compiler used when developing and writing programs, and the original code before compilation must also be written in a specific programming language, which is called hardware description language (HDL). There is not only one kind of HDL, but many kinds, such as ABEL (Advanced Boolean Expression Language), AHDL (Altera Hardware Description Language), Confluence, CUPL (Cornell University Programming Language), HDCal, JHDL (Java Hardware Description Language), Lava, Lola, MyHDL, PALASM, RHDL (Ruby Hardware Description Language), etc. The most commonly used ones are VHDL (Very-High-Speed ​​Integrated Circuit Hardware Description Language) and Verilog. Those skilled in the art should also know that it is only necessary to program the method flow slightly in the above-mentioned hardware description languages ​​and program it into the integrated circuit, and then it is easy to obtain the hardware circuit that implements the logic method flow.

[0044] The controller may be implemented in any suitable manner, for example, the controller may take the form of a microprocessor or processor and a computer-readable medium storing a computer-readable program code (e.g., software or firmware) executable by the (micro)processor, a logic gate, a switch, an application-specific integrated circuit (ASIC), a programmable logic controller, and an embedded microcontroller, examples of which include but are not limited to the following microcontrollers: ARC 625D, Atmel AT91SAM, Microchip PIC18F26K20, and Silicone Labs C8051F320, and the memory controller may also be implemented as part of the control logic of the memory. It is also known to those skilled in the art that, in addition to implementing the controller in a purely computer-readable program code manner, the controller may be implemented in the form of a logic gate, a switch, an application-specific integrated circuit, a programmable logic controller, and an embedded microcontroller by logically programming the method steps. Therefore, such a controller may be considered as a hardware component, and the devices for implementing various functions included therein may also be considered as structures within the hardware component. Or even, the devices for implementing various functions may be considered as both software modules for implementing the method and structures within the hardware component.

[0045] The systems, devices, modules or units described in the above embodiments may be implemented by computer chips or entities, or by products with certain functions. A typical implementation device is a computer. Specifically, the computer may be, for example, a personal computer, a laptop computer, a cellular phone, a camera phone, a smart phone, a personal digital assistant, a media player, a navigation device, an email device, a game console, a tablet computer, a wearable device, or a combination of any of these devices.

[0046] For the convenience of description, the above device is described in various units according to their functions. Of course, when implementing this specification, the functions of each unit can be implemented in the same or multiple software and / or hardware.

[0047] Each embodiment in this application is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the device and medium embodiments, since they are basically similar to the method embodiments, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiments.

[0048] The devices and media provided in the embodiments of the present application correspond one-to-one to the methods. Therefore, the devices and media also have similar beneficial technical effects as the corresponding methods. Since the beneficial technical effects of the methods have been described in detail above, the beneficial technical effects of the devices and media will not be repeated here.

[0049] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present application may adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes. The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0050] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0051] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0052] In a typical configuration, a computing device includes one or more processors (CPU), input / output interfaces, network interfaces, and memory.

[0053] Memory may include non-permanent storage in a computer-readable medium, in the form of random access memory (RAM) and / or non-volatile memory, such as read-only memory (ROM) or flash RAM. Memory is an example of a computer-readable medium.

[0054] Computer readable media include permanent and non-permanent, removable and non-removable media that can be implemented by any method or technology to store information. Information can be computer readable instructions, data structures, program modules or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, compact disk read-only memory (CD-ROM), digital versatile disk (DVD) or other optical storage, magnetic cassettes, magnetic tape magnetic disk storage or other magnetic storage devices or any other non-transmission media that can be used to store information that can be accessed by a computing device. As defined herein, computer readable media does not include temporary computer readable media (transitory media), such as modulated data signals and carrier waves.

[0055] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.

[0056] The above are only embodiments of the present application and are not intended to limit the present application. For those skilled in the art, the present application may have various changes and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included within the scope of the claims of the present application.

Claims

1. A method for skew calibration of a parallel bus, characterized in that: include: The processor receives instructions and test data from the host computer, sends the instructions to the controller, and parses the instructions through the controller to output a control signal; Inputting the control signal and the test data into a PAD port to perform a loopback test through the PAD port to obtain a test result, and comparing the test result with the test data; If the test result is the same as the test data, it means that the skew is normal.

2. The method according to claim 1, characterized in that The controller analyzes the instruction to output a control signal, which specifically includes: Produce a plurality of control signals according to the instructions, wherein the control signals include an enable signal, a clock control signal, and a data control signal; Sending the enable signal to the multiplexer to enable the multiplexer; Sending the clock control signal to the clock delay device to enable the clock delay device to start; The data control signal is sent to the data delayer to enable the data delayer to be turned on.

3. The method according to claim 2, characterized in that Inputting the control signal and the test data into the PAD port specifically includes: Sending the test data to a buffer, and sending the test data to the data delayer through the buffer to obtain output data through the data delayer; An output clock is obtained through the clock delay device, and the output clock and the output data are input to the PAD port.

4. The method according to claim 3, characterized in that: Perform a loopback test through the PAD port, specifically including: The PAD port includes a clock PAD port and a data PAD port; Receive the output clock through the DO end of the clock PAD port, and output the PAD clock through the DI segment of the clock PAD port; Receive the output data through the DO terminal of the data PAD port, and output the PAD data through the DI segment of the data PAD port; The PAD data is sent to a trigger, so that the trigger outputs the test result according to a rising edge of the PAD clock.

5. The method according to claim 1, characterized in that The method further comprises: Determine a preset data delay and a clock delay, and set the PAD port according to the data delay and the clock delay; Aligning a clock edge with a data center, determining test data and a multiplexed output value of the PAD port, and comparing the test data with the multiplexed output value; If the test data is equal to the multiplexed output value, the value of the clock delay is reduced according to a preset value, or the value of the data delay is increased according to a preset value, and the PAD port is reset according to the reduced clock delay or the increased data delay; If the test data is not equal to the multiplexed output value, the corresponding data delay is used as the skew difference of the PAD port.

6. The method according to claim 1, characterized in that The method further comprises: Determine a right boundary and a left boundary according to a preset clock delay, determine a selection range according to the right boundary and the left boundary, and determine a delay value in the selection range; The data port of the PAD port is skew compensated according to the delay value.

7. The method according to claim 6, characterized in that The right boundary is determined according to the preset clock delay, including: determining test data and multiplexed output values ​​for a plurality of ports, and comparing the test data with the multiplexed output values; If the test data corresponding to all ports are not equal to the multiplexed output values, reporting error information to the processor; If the test data corresponding to one or more ports are equal to the multiplexed output value, the delay time of the PAD port is increased according to a preset value; If the test data and the multiplexed output value corresponding to one or more ports are not equal, the corresponding clock delay is used as the right boundary.

8. The method according to claim 6, characterized in that The left boundary is determined according to the preset clock delay, including: determining test data and multiplexed output values ​​for a plurality of ports, and comparing the test data with the multiplexed output values; If the test data corresponding to all ports are not equal to the multiplexed output values, reporting error information to the processor; If the test data corresponding to one or more ports are equal to the multiplexed output value, the delay time of the PAD port is reduced according to a preset value; If the test data and the multiplexed output value corresponding to one or more ports are not equal, the corresponding clock delay is used as the left boundary.

9. A skew calibration device for a parallel bus, characterized in that: include: at least one processor; as well as, a memory communicatively connected to the at least one processor; wherein, The memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the skew calibration device for a parallel bus to perform: The processor receives instructions and test data from the host computer, sends the instructions to the controller, and parses the instructions through the controller to output a control signal; Inputting the control signal and the test data into a PAD port to perform a loopback test through the PAD port to obtain a test result, and comparing the test result with the test data; If the test result is the same as the test data, it means that the skew is normal.

10. A non-volatile computer storage medium storing computer executable instructions, characterized in that: The computer executable instructions are configured to: The processor receives instructions and test data from the host computer, sends the instructions to the controller, and parses the instructions through the controller to output a control signal; Inputting the control signal and the test data into a PAD port to perform a loopback test through the PAD port to obtain a test result, and comparing the test result with the test data; If the test result is the same as the test data, it means that the skew is normal.

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