Control circuit, asymmetric half-bridge flyback converter, control method and chip
By designing a control circuit in an asymmetric half-bridge flyback converter, sampling the secondary current value and turning off the second transistor when the threshold is reached, the problem of excessive resonant cavity current is solved, and the effect of extending the working life is achieved.
Patent Information
- Application Number
- CN202411937118.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-26
- Publication Date
- 2025-03-04
AI Technical Summary
The asymmetric half-bridge flyback converter damages the device due to excessive resonant cavity current in DCM and CRM modes, affecting the working life.
A control circuit is designed, including a primary controller, a secondary controller and a secondary sampling circuit, and reduces the resonant current of the resonant cavity by sampling the secondary current value in the secondary circuit within each working cycle and turning off the second transistor when the secondary current value reaches the maximum threshold.
It effectively avoids device damage caused by excessive resonant cavity current and extends the working life of the asymmetric half-bridge flyback converter.
Smart Images
Figure CN119561391A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the technical field of converters, and in particular to a control circuit, an asymmetric half-bridge flyback converter, a control method and a chip. Background Art
[0002] Asymmetric Half-Bridge (AHB) flyback converter has the advantages of wide input and output voltage range, stability, reliability and fast response. Therefore, it is widely used in various application scenarios. Discontinuous Conduction Mode (DCM) and Critical Conduction Mode (CRM) are two common operating modes of asymmetric half-bridge flyback converter. DCM and CRM are often used in light load conditions to reduce losses and improve efficiency.
[0003] In the related art, when the asymmetric half-bridge flyback converter operates in DCM mode and CRM mode, the load size at the output end of the asymmetric half-bridge flyback converter often changes, causing the resonant cavity current of the asymmetric half-bridge flyback converter to be too large and damaging the device, thereby affecting the working life of the asymmetric half-bridge flyback converter. Summary of the invention
[0004] The present application provides a control circuit, an asymmetric half-bridge flyback converter, a control method and a chip to solve the technical problem in the related art that the asymmetric half-bridge flyback converter may damage the device due to excessive current in the resonant cavity, thereby affecting the working life of the asymmetric half-bridge flyback converter.
[0005] In a first aspect, the present application provides a control circuit for an asymmetric half-bridge flyback converter, wherein the asymmetric half-bridge flyback converter comprises: a first transistor, a second transistor, a third transistor, a transformer, a first capacitor, a second capacitor, a third capacitor, and a first inductor; the first transistor, the second transistor, the first capacitor, the second capacitor, and the first inductor are arranged in a primary loop where a primary winding of the transformer is located, and the third transistor and the third capacitor are arranged in a secondary loop where a secondary winding of the transformer is located;
[0006] The control circuit includes a primary controller, a secondary controller and a secondary sampling circuit; the primary controller is connected to the control electrodes of the first transistor and the second transistor respectively, and the secondary controller is connected to the control electrode of the third transistor;
[0007] The sampling end of the secondary sampling circuit is arranged in the secondary loop, and the output end of the secondary sampling circuit is connected to the secondary controller; the secondary sampling circuit is used to sample the secondary current value in the secondary loop in each working cycle, and output the secondary current value to the secondary controller; the secondary controller is used to send a first control signal to the primary controller when it is determined that the secondary current value is greater than or equal to a first current threshold value;
[0008] The primary controller is used for controlling the second transistor to be turned off according to the first control signal.
[0009] In a possible design, the secondary sampling circuit is a voltage sampling circuit; the secondary sampling circuit is used to sample the source-drain voltage of the third transistor in the secondary loop;
[0010] The secondary controller is further used to determine the secondary current value in the secondary loop according to the source-drain voltage of the third transistor and the on-resistance of the third transistor.
[0011] In a possible design, the control circuit further includes a secondary sampling resistor, and the secondary sampling resistor is connected in series in the secondary loop;
[0012] The secondary sampling circuit is a voltage sampling circuit; the secondary sampling circuit is used to sample the voltage value on the secondary sampling resistor in the secondary loop;
[0013] The secondary controller is further used to determine the secondary current value according to the voltage value on the secondary sampling resistor and the resistance value of the secondary sampling resistor.
[0014] In a possible design, the control circuit further includes a primary first sampling circuit, a sampling end of the primary first sampling circuit is arranged in the primary loop, and an output end of the primary first sampling circuit is connected to the primary controller;
[0015] The primary first sampling circuit is used to sample the resonant current value in the primary loop and output the sampled resonant current value to the primary controller;
[0016] The primary controller is used to control the second transistor to be turned off when it is determined that the resonant current value is greater than or equal to a second current threshold; or the primary controller is used to determine the resonant current value in the primary loop according to the secondary current value, and control the second transistor to be turned off when it is determined that the resonant current value is greater than or equal to the second current threshold.
[0017] In a possible design, the control circuit further includes a primary second sampling circuit, a sampling end of the primary second sampling circuit is arranged in the primary loop or the secondary loop, and an output end of the primary second sampling circuit is connected to the primary controller;
[0018] The primary second sampling circuit is used to sample the voltage information and current information of the primary winding or the secondary winding, and the primary controller is used to control the opening and closing of the asymmetric half-bridge flyback converter according to the voltage information and current information of the primary winding or the secondary winding;
[0019] Alternatively, the primary controller is used to perform circuit protection on the asymmetric half-bridge flyback converter according to the voltage information and current information of the primary winding or the secondary winding;
[0020] Alternatively, the primary controller is used to perform valley control on the asymmetric half-bridge flyback converter according to voltage information and current information of the primary winding or the secondary winding.
[0021] In a possible design, the primary second sampling circuit includes an auxiliary winding, a first resistor and a second resistor;
[0022] The auxiliary winding is coupled to the secondary winding of the transformer, the first end of the auxiliary winding is grounded, the second end of the auxiliary winding is connected to the first end of the first resistor, the second end of the first resistor is connected to the first end of the second resistor, and the second end of the second resistor is grounded; the first end of the second resistor is the output end of the primary second sampling circuit, and the first end of the second resistor is connected to the primary controller.
[0023] In a second aspect, the present application further provides an asymmetric half-bridge flyback converter, wherein the asymmetric half-bridge flyback converter comprises a control circuit as described in any one of the above items.
[0024] In a third aspect, the present application further provides a control method for an asymmetric half-bridge flyback converter, wherein the asymmetric half-bridge flyback converter comprises: a first transistor, a second transistor, a third transistor, a transformer, a first capacitor, a second capacitor, a third capacitor and a first inductor; the first transistor, the second transistor, the first capacitor, the second capacitor and the first inductor are arranged in a primary loop where the primary winding of the transformer is located, and the third transistor and the third capacitor are arranged in a secondary loop where the secondary winding of the transformer is located;
[0025] The control method comprises:
[0026] In each working cycle, after the second transistor is turned on, obtaining a secondary current value in the secondary loop;
[0027] Determine whether the secondary current value is greater than or equal to a first current threshold, and if so, control turning off the second transistor.
[0028] In a fourth aspect, the present application also provides a chip, comprising a control circuit as described in any one of the above items.
[0029] In a fifth aspect, the present application further provides an electronic device, the electronic device comprising the control circuit as described in any one of the above items; or the electronic device comprising the asymmetric half-bridge flyback converter as described in any one of the above items.
[0030] The control circuit provided by the first aspect is used in an asymmetric half-bridge flyback converter, and the control circuit includes a primary controller, a secondary controller and a secondary sampling circuit; the primary controller is connected to the control electrodes of the first transistor and the second transistor respectively, and the secondary controller is connected to the control electrode of the third transistor; the sampling end of the secondary sampling circuit is arranged in the secondary loop, and the output end of the secondary sampling circuit is connected to the secondary controller; the secondary sampling circuit is used to sample the secondary current value in the secondary loop in each working cycle and output the secondary current value to the secondary controller; the secondary controller is used to send a first control signal to the primary controller when it is determined that the secondary current value is greater than or equal to the first current threshold value, and the primary controller is used to control the shutdown of the second transistor according to the first control signal. When the secondary current in the secondary loop reaches the maximum threshold, the resonant current of the resonant cavity also reaches the maximum threshold synchronously. Therefore, when the load size at the output end of the asymmetric half-bridge flyback converter changes, causing the secondary current value of the asymmetric half-bridge flyback converter to be too large, the second transistor can be immediately turned off to quickly reduce the resonant current value of the resonant cavity of the asymmetric half-bridge flyback converter, thereby avoiding the resonant current value of the resonant cavity being too large to damage components in the circuit, thereby ensuring the working life of the asymmetric half-bridge flyback converter.
[0031] The beneficial effects provided in the above-mentioned second aspect and various possible designs of the above-mentioned second aspect can refer to the beneficial effects brought about by the above-mentioned first aspect and various possible implementation methods of the first aspect, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS
[0032] Figure 1 One of the control circuit structure schematic diagrams provided in the embodiment of the present application;
[0033] Figure 2 One of the waveform diagrams of the asymmetric half-bridge flyback converter provided in the embodiment of the present application working in the critical conduction mode;
[0034] Figure 3 One of the waveform diagrams of the asymmetric half-bridge flyback converter provided in the embodiment of the present application working in the discontinuous conduction mode;
[0035] Figure 4 The second waveform diagram of the asymmetric half-bridge flyback converter provided in the embodiment of the present application working in the critical conduction mode;
[0036] Figure 5 The second waveform diagram of the asymmetric half-bridge flyback converter provided in the embodiment of the present application working in the discontinuous conduction mode;
[0037] Figure 6 The second schematic diagram of the control circuit structure provided in the embodiment of the present application;
[0038] Figure 7 The third schematic diagram of the control circuit structure provided in the embodiment of the present application;
[0039] Figure 8 The fourth schematic diagram of the control circuit structure provided in the embodiment of the present application;
[0040] Fig. 9 The fifth schematic diagram of the control circuit structure provided in the embodiment of the present application;
[0041] Fig.10 The sixth schematic diagram of the control circuit structure provided in the embodiment of the present application;
[0042] Fig.11 A flow chart of a control method for an asymmetric half-bridge flyback converter provided in an embodiment of the present application. DETAILED DESCRIPTION
[0043] In this application, "at least one" means one or more, and "plurality" means two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone, where A and B can be singular or plural. The character " / " generally indicates that the associated objects before and after are in an "or" relationship. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single items or plural items. For example, at least one of a, b, or c alone can represent: a, b, c, a and b, a and c, or a, b, and c, where a, b, and c can be single or multiple. In addition, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance.
[0044] The directions or positional relationships indicated by terms such as "center", "longitudinal", "lateral", "up", "down", "left", "right", "front", and "back" are based on the directions or positional relationships shown in the accompanying drawings and are only for the convenience of describing the present application and simplifying the description. They do not indicate or imply that the device or element referred to must have a specific direction, be constructed and operated in a specific direction, and therefore should not be understood as a limitation on the present application.
[0045] The terms "connected" and "connected" should be understood in a broad sense. For example, the "connected" or "connected" of a circuit structure can refer to not only physical connection, but also electrical connection or signal connection. For example, it can be directly connected, that is, physically connected, or indirectly connected through at least one intermediate element, as long as the circuit is connected, or it can be the internal connection of two elements; signal connection can refer to signal connection through a circuit or through a media medium, such as radio waves. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.
[0046] The transistor in the present application is a three-terminal transistor, and its three terminals are a control electrode, a first electrode, and a second electrode. The transistor can be a bipolar transistor or a field effect transistor, etc. For example, when the transistor is a bipolar transistor, its control electrode refers to the base of the bipolar transistor, the first electrode can be the collector or emitter of the bipolar transistor, and the corresponding second electrode can be the emitter or collector of the bipolar transistor; when the transistor is a field effect transistor, its control electrode refers to the gate of the field effect transistor, the first electrode can be the drain or source of the field effect transistor, and the corresponding second electrode can be the source or drain of the field effect transistor.
[0047] The control circuit provided in the present application is mainly used in an asymmetric half-bridge flyback converter. The working modes of the asymmetric half-bridge flyback converter include multiple modes, which can generally be divided into a continuous conduction mode CCM (Continuous Conduction Mode), a critical conduction mode CRM and a discontinuous conduction mode DCM. The present application focuses on the control method of the asymmetric half-bridge flyback converter in the CRM mode and the DCM mode. When the asymmetric half-bridge flyback converter works in the DCM mode and the CRM mode, the load size at the output end of the asymmetric half-bridge flyback converter often changes, causing the resonant cavity current of the asymmetric half-bridge flyback converter to be too large and damage the device, thereby affecting the working life of the asymmetric half-bridge flyback converter. For example, when the load at the output end of the asymmetric half-bridge flyback converter becomes smaller within a certain working cycle, the resonant cavity current of the asymmetric half-bridge flyback converter will increase significantly, which will damage the device in the circuit, thereby affecting the working life of the asymmetric half-bridge flyback converter.
[0048] In order to overcome the deficiencies in the above-mentioned related technologies, the present application provides a control circuit for an asymmetric half-bridge flyback converter, the control circuit comprising a primary controller, a secondary controller and a secondary sampling circuit; the primary controller is connected to the control electrodes of a first transistor and a second transistor respectively, and the secondary controller is connected to the control electrode of a third transistor; the sampling end of the secondary sampling circuit is arranged in a secondary loop, and the output end of the secondary sampling circuit is connected to the secondary controller; the secondary sampling circuit is used to sample the secondary current value in the secondary loop in each working cycle, and output the secondary current value to the secondary controller, the secondary controller is used to send a first control signal to the primary controller when determining that the secondary current value is greater than or equal to a first current threshold value, and the primary controller is used to control the shutdown of the second transistor according to the first control signal. When the secondary current in the secondary loop reaches the maximum threshold, the resonant current of the resonant cavity also reaches the maximum threshold synchronously. Therefore, when the load size at the output end of the asymmetric half-bridge flyback converter changes, causing the secondary current value of the asymmetric half-bridge flyback converter to be too large, the second transistor can be immediately turned off to quickly reduce the resonant current value of the resonant cavity of the asymmetric half-bridge flyback converter, thereby avoiding the resonant current value of the resonant cavity being too large to damage components in the circuit, thereby ensuring the working life of the asymmetric half-bridge flyback converter.
[0049] Figure 1 This is one of the schematic diagrams of the control circuit structure provided in the embodiment of the present application. In order to more clearly describe the control circuit provided in the present application, Figure 1 A common flyback converter circuit is taken as an example to illustrate the control circuit provided by the present application in detail.
[0050] See also Figure 1 As shown, the flyback converter circuit provided in this embodiment includes a first transistor Q1, a second transistor Q2, a third transistor Q3, a transformer T, a first capacitor C1, a second capacitor C2, a third capacitor C3 and a first inductor L1. The first transistor Q1, the second transistor Q2, the first capacitor C1, the second capacitor C2 and the first inductor L1 are arranged in a primary loop where the primary winding of the transformer T is located, and the third transistor Q3 and the third capacitor C3 are arranged in a secondary loop where the secondary winding of the transformer is located.
[0051] Among them, the first capacitor C1 is connected in parallel to the output end of the power supply, the first electrode of the first transistor Q1 is connected to the first end of the first capacitor C1, the second electrode of the first transistor Q1 is connected to the first electrode of the second transistor Q2, the second electrode of the second transistor Q2 is connected to the second end of the first capacitor C1, and at the same time, the second end of the second transistor Q2 is grounded GND; the second electrode of the first transistor Q1 is also connected to the first end of the first inductor L1, the second end of the first inductor L1 is connected to the first end of the primary winding of the transformer T, the second end of the primary winding of the transformer T is connected to the first end of the second capacitor C2, and the second end of the second capacitor C2 is connected to the second electrode of the second transistor Q2.
[0052] The first end of the secondary winding of the transformer T is connected to the first end of the third capacitor C3, and the second end of the third capacitor C3 is connected to the ground GND; at the same time, the second end of the third capacitor C3 is also connected to the second electrode of the third transistor Q3, and the first electrode of the third transistor Q3 is connected to the second end of the secondary winding of the transformer T. The two ends of the third capacitor C3 are output ends, which are used to output the transformed output voltage signal.
[0053] Among them, the first end of the primary winding of the transformer T in this embodiment is a terminal of different names, the second end of the primary winding is a terminal of the same name, the first end of the secondary winding of the transformer T is a terminal of the same name, and the second end of the secondary winding is a terminal of different names. In other embodiments, the first end of the primary winding of the transformer T can also be a terminal of the same name, and the second end of the primary winding is a terminal of different names, and correspondingly, the first end of the secondary winding of the transformer T is a terminal of different names, and the second end of the secondary winding is a terminal of the same name.
[0054] Specifically, in this embodiment, the second end of the first inductor L1 is connected to the opposite end of the primary winding of the transformer T, and the same end of the primary winding of the transformer T is connected to the first end of the second capacitor C2. The same end of the secondary winding of the transformer T is connected to the first end of the third capacitor C3, and the opposite end of the secondary winding of the transformer T is connected to the first electrode of the third transistor Q3.
[0055] Among them, the first transistor Q1, the second transistor Q2 and the third transistor Q3 in the flyback converter circuit of this embodiment adopt PMOS (P-Metal-Oxide-Semiconductor) tubes. In other embodiments, the first transistor Q1, the second transistor Q2 and the third transistor Q3 can also adopt NMOS (N-Metal-Oxide-Semiconductor) tubes. For example, when the first transistor Q1, the second transistor Q2 and the third transistor Q3 adopt PMOS, their first pole is the drain, their second pole is the source, and their control pole is the gate.
[0056] Please continue to see Figure 1As shown, the control circuit provided in this embodiment includes a primary controller 10, a secondary controller 20, a secondary sampling circuit 15, a first drive circuit 11, a second drive circuit 12 and a third drive circuit 16. The primary controller 10 is connected to the gate of the first transistor Q1 through the first drive circuit 11, the primary controller 10 is connected to the gate of the second transistor Q2 through the second drive circuit 12, and the secondary controller 20 is connected to the gate of the third transistor Q3 through the third drive circuit 16.
[0057] Among them, the sampling end of the secondary sampling circuit 15 is set in the secondary loop of the transformer T, and the output end of the secondary sampling circuit 15 is connected to the secondary controller 20; the secondary sampling circuit 15 is used to sample the secondary current value in the secondary loop in each working cycle, and output the secondary current value to the secondary controller 20; the secondary controller 20 is used to determine whether the secondary current value is greater than or equal to the first current threshold value, and if so, send a first control signal to the primary controller 10; the primary controller 10 is used to control the shutdown of the second transistor Q2 according to the first control signal.
[0058] By analyzing the relationship between the resonant current in the primary circuit and the secondary current in the secondary circuit, it can be known that when the secondary current in the secondary circuit reaches the maximum threshold, the resonant current of the resonant cavity also reaches the maximum threshold synchronously. Therefore, when the load size at the output end of the asymmetric half-bridge flyback converter changes, causing the secondary current value of the asymmetric half-bridge flyback converter to be too large, the second transistor can be immediately turned off to quickly reduce the resonant current value of the resonant cavity of the asymmetric half-bridge flyback converter, thereby avoiding the resonant current value of the resonant cavity being too large to damage components in the circuit, thereby ensuring the working life of the asymmetric half-bridge flyback converter.
[0059] The technical solution of this embodiment is further described below in conjunction with the specific critical conduction mode CRM and discontinuous conduction mode DCM. Q1 represents the driving signal input to the control electrode of the first transistor Q1. Q1 When it is high, it means that the first transistor Q1 is in the on state. Q1 When V is low, it indicates that the first transistor Q1 is in the off state. Q2 represents the driving signal input to the control electrode of the second transistor Q2. Q2 When it is high, it means that the second transistor Q2 is in the on state. Q2 When it is low level, it indicates that the second transistor Q2 is in the off state. Q3 represents the driving signal input to the control electrode of the third transistor Q3. Q3 When it is high, it means that the third transistor Q3 is in the on state. Q3When it is low level, it indicates that the third transistor Q3 is in the off state. resonant Represents the resonant current in the primary circuit, I mag Represents the excitation current in the primary circuit of the transformer, I SEC Indicates the secondary current in the secondary circuit. I SEC_limit Represents the secondary current I in the secondary circuit SEC The corresponding first current threshold, I resonant_limit Represents the resonant current I in the primary circuit resonant The corresponding second current threshold. T dead1 represents the dead time between the turn-off moment of the first transistor Q1 and the turn-on moment of the second transistor Q2, T dead2 It represents the dead time between the moment when the second transistor Q2 is turned off and the moment when the first transistor Q1 is turned on in the next working cycle.
[0060] Figure 2 One of the waveform diagrams of the asymmetric half-bridge flyback converter provided in the embodiment of the present application working in the critical conduction mode, see Figure 2 As shown, in a working scenario, when the asymmetric half-bridge flyback converter works in the CRM mode, in a working cycle, the first transistor Q1 is first turned on at time t0 to charge the second capacitor C2 for energy storage, and the first transistor Q1 is turned off at time t1. After the first dead time T dead1 At time t2, the second transistor Q2 is turned on, and the third transistor Q3 is turned on at the same time, so that the first inductor L1 and the second capacitor C2 in the primary circuit resonate, and the excitation current I mag The excitation inductance transfers energy to the secondary circuit, and the third transistor Q3 is turned off at time t3, and the second transistor Q2 is turned off at time t4, thus completing a working cycle. dead2 After that, the first transistor Q1 is turned on again to start the next working cycle.
[0061] Please continue to see Figure 2 As shown, when the load at the output end of the asymmetric half-bridge flyback converter is small and the load at the output end of the asymmetric half-bridge flyback converter does not change during the current working cycle, the secondary sampling circuit 15 samples the secondary current value I in the secondary loop during the current working cycle. SEC , and the secondary current value I SEC Output to the secondary controller 20; the secondary controller 20 determines the secondary current value I SEC Less than the first current threshold I SEC_limit, there is no need to send the first control signal to the primary controller 10; that is, there is no need to immediately control the second transistor Q2 to be turned off so that the resonant current value of the resonant cavity of the asymmetric half-bridge flyback converter is quickly reduced.
[0062] Among them, due to the secondary current I SEC and the resonant current I resonant The corresponding relationship between them is that between t2 and t3, when the secondary current I SEC When the resonant current I reaches its maximum value, resonant The reverse maximum value was also reached.
[0063] Figure 3 This is one of the waveform diagrams of the asymmetric half-bridge flyback converter provided in the embodiment of the present application working in the discontinuous conduction mode, see Figure 3 As shown, in one working scenario, when the asymmetric half-bridge flyback converter operates in the DCM mode, when the secondary controller 20 determines the secondary current value I SEC Less than the first current threshold I SEC_limit , there is no need to send the first control signal to the primary controller 10; that is, there is no need to immediately control the second transistor Q2 to be turned off.
[0064] In one embodiment, when the asymmetric half-bridge flyback converter operates in the DCM mode, the secondary controller 20 is further configured to control the second transistor Q2 to be pre-conducted for a first time period T at the beginning of each working cycle. zvspulse In other words, at the beginning of each working cycle, the second transistor Q2 is first controlled to turn on, and the second transistor Q2 is turned on for the first time length T zvspulse After that, the second transistor Q2 is controlled to be turned off. After the second transistor Q2 is turned off, the second dead time T dead2 Then, the first transistor Q1 is turned on.
[0065] See also Figure 3 As shown in the waveform diagram, in the current working cycle, the second transistor Q2 is pre-conducted for the first time length T zvspulse After that, the secondary current I in the secondary circuit SEC The zero crossing turns negative. Due to the resonance effect of transformer T, the excitation inductance current I in transformer T at this time mag It will also cross zero and become negative, and then when the first transistor Q1 is turned on, the first transistor Q1 is a zero voltage switch, which improves the working efficiency of the asymmetric half-bridge flyback converter. And according to the control method provided in this embodiment, the risk of the first transistor Q1 and the third transistor Q3 being turned on at the same time is avoided, thereby avoiding damage to the components in the circuit and ensuring the working life of the circuit.
[0066] In one embodiment, the secondary controller 20 is further used to determine whether the asymmetric half-bridge flyback converter operates in the DCM mode. If so, at the beginning of each working cycle, the second transistor Q2 is first controlled to be pre-conducted for a first time length T zvspulse When the asymmetric half-bridge flyback converter operates in other modes, it is not necessary to control the second transistor Q2 to be pre-conducted for a period of time.
[0067] Figure 4 The second waveform diagram of the asymmetric half-bridge flyback converter provided in the embodiment of the present application working in the critical conduction mode is shown in FIG. Figure 4 As shown, when the asymmetric half-bridge flyback converter operates in the CRM mode, in the first working cycle, the load size at the output end of the asymmetric half-bridge flyback converter does not change, so the resonant current I resonant and the secondary current I SEC When the load size at the output of the asymmetric half-bridge flyback converter changes during the second working cycle, the secondary current I SEC Equal to the first current threshold I SEC_limit , and at the same time, the resonant current I resonant Reaching the second current threshold I resonant_limit At this time, the secondary sampling circuit 15 samples the secondary current value in the secondary loop and outputs the secondary current value to the secondary controller 20; the secondary controller 20 determines the secondary current value I SEC Equal to the first current threshold I SEC_limit , then sends a first control signal to the primary controller 10; the primary controller 10 is used to control the second transistor Q2 to be turned off according to the first control signal, so that the resonant current value I of the resonant cavity of the asymmetric half-bridge flyback converter resonant The rapid reduction avoids the resonant current value of the resonant cavity being too large and damaging the components in the circuit, thereby ensuring the working life of the asymmetric half-bridge flyback converter.
[0068] Figure 5 The second waveform diagram of the asymmetric half-bridge flyback converter provided in the embodiment of the present application working in the discontinuous conduction mode is shown in FIG. Figure 5 As shown in FIG. 1 , when the asymmetric half-bridge flyback converter operates in DCM mode, in the first working cycle, the load size at the output end of the asymmetric half-bridge flyback converter does not change, so the resonant current I resonant and the secondary current I SEC When the load size at the output of the asymmetric half-bridge flyback converter changes during the second working cycle, the secondary current I SEC Equal to the first current threshold I SEC_limit , and at the same time, the resonant current I resonantReaching the second current threshold I resonant_limit At this time, the secondary sampling circuit 15 samples the secondary current value in the secondary loop and outputs the secondary current value to the secondary controller 20; the secondary controller 20 determines the secondary current value I SEC Equal to the first current threshold I SEC_limit , then sends a first control signal to the primary controller 10; the primary controller 10 is used to control the second transistor Q2 to be turned off according to the first control signal, so that the resonant current value I of the resonant cavity of the asymmetric half-bridge flyback converter resonant The rapid reduction avoids the resonant current value of the resonant cavity being too large and damaging the components in the circuit, thereby ensuring the working life of the asymmetric half-bridge flyback converter.
[0069] Please continue to see Figure 1 As shown, in one embodiment, the secondary sampling circuit 15 is a voltage sampling circuit; the sampling end of the secondary sampling circuit 15 is connected to the drain of the third transistor Q3, and the secondary sampling circuit 15 is used to sample the source-drain voltage of the third transistor Q3 in the secondary loop; the secondary controller 20 is also used to sample the source-drain voltage of the third transistor Q3 and the on-resistance R of the third transistor Q3 according to the source-drain voltage of the third transistor Q3 and the on-resistance R of the third transistor Q3. DSON , determine the secondary current value I in the secondary circuit SEC .
[0070] It can be understood that the third transistor Q3 mainly plays the role of synchronous rectification in the secondary circuit. In the secondary circuit, assuming that the on-resistance of the third transistor Q3 is R DSON , then the source-drain voltage V SRD It can be expressed as: V SRD =I sec *R DSON =(I mag -I resonant )*N*R DSON , it can be seen from this formula that the source-drain voltage of the third transistor Q3 can reflect the resonant current I of the primary resonant cavity of the transformer to a certain extent. resonant Therefore, the source-drain voltage V of the third transistor Q3 can be detected. SRD , according to the source-drain voltage V SRD Calculate the secondary current value I SEC , and then the secondary current value I SEC The first current threshold I SEC_limit Comparison is used to realize the resonant cavity peak current protection.
[0071] Figure 6 For the second schematic diagram of the control circuit structure provided in the embodiment of the present application, please refer to Figure 6 As shown, in one embodiment, the control circuit further includes a secondary sampling resistor Rsense , secondary sampling resistor R sense In series in the secondary circuit, specifically, the secondary sampling resistor R sense The secondary sampling circuit 15 of this embodiment is specifically a voltage sampling circuit; the secondary sampling circuit 15 is used to sample the secondary sampling resistor R in the secondary loop. sense The voltage value V sense The secondary controller 20 is also used according to the secondary sampling resistor R sense The voltage value V sense And the secondary sampling resistor V sense The resistance value determines the secondary current value I SEC .
[0072] It can be understood that in this embodiment, by introducing the secondary sampling resistor R sense The resonant current I in the primary resonant cavity of the transformer T is sampled by resonant Among them, the sampling resistor R sense The voltage V sense It can be expressed as: V sense =I sec *R sense =(I mag -I resonant )*N*R sense , N is the winding ratio of transformer T, therefore, the sampling resistor R sense The voltage V sense It can reflect the transformer primary resonant cavity resonant current I to a certain extent. resonant changes.
[0073] Figure 7 For the third schematic diagram of the control circuit structure provided in the embodiment of the present application, please refer to Figure 7 As shown, in one embodiment, the control circuit further includes a primary first sampling circuit 13, the sampling end of the primary first sampling circuit 13 is arranged in the primary loop, and the output end of the primary first sampling circuit 13 is connected to the primary controller 10; the primary first sampling circuit 13 is used to sample the resonant current value I in the primary loop resonant and outputs the sampled resonant current value to the primary controller 10; the primary controller 10 is used to determine the resonant current value I resonant When the current is greater than or equal to the second current threshold, the second transistor Q2 is controlled to be turned off.
[0074] Specifically, in one embodiment, the first sampling circuit 13 may be a current sampling circuit, which may sample the resonant current value I in the primary loop. resonantIn another embodiment, the first sampling circuit 13 may be a sampling resistor and a voltage sampling circuit, and the resonant current value I in the primary loop may be calculated according to the sampled voltage and resistance. resonant .
[0075] In one embodiment, see Figure 7 As shown, a primary sampling resistor CS is set in the primary loop, and the first sampling circuit 13 is a voltage sampling circuit. The voltage sampling circuit collects the voltage value on the primary sampling resistor CS and outputs it to the primary controller 10. The primary controller 10 calculates the resonant current value I according to the sampled voltage value and the resistance value of the primary sampling resistor CS. resonant .
[0076] See also Figure 7 As shown, in one embodiment, the first end of the primary sampling resistor CS is connected to the second end of the second capacitor C2, and the second end of the primary sampling resistor CS is connected to the second end of the first capacitor C1. Figure 7 The primary first sampling circuit 13 shown can make the primary sampling resistor CS in the loop in a complete switching cycle to sample the resonant current I of the resonant cavity in a complete working cycle. resonant .
[0077] Figure 8 For the fourth schematic diagram of the control circuit structure provided in the embodiment of the present application, please refer to Figure 8 As shown, in one embodiment, the first end of the secondary sampling resistor CS is connected to the second end of the second capacitor C2, and the second end of the secondary sampling resistor CS is connected to the source of the second transistor Q2. Figure 8 The primary first sampling circuit 13 is shown, so that in a complete switching cycle, the primary sampling resistor CS only samples the resonant cavity current value during the turn-on period of the first transistor Q1.
[0078] In one embodiment, the primary controller 10 is used to sec Determine the resonant current value I in the primary circuit resonant , in determining the resonant current value I resonant Greater than or equal to the second current threshold I resonant_limit When the second transistor Q2 is turned off, the resonant current value I of the resonant cavity of the asymmetric half-bridge flyback converter can also be made resonant The rapid reduction avoids the resonant current value of the resonant cavity being too large and damaging the components in the circuit, thereby ensuring the working life of the asymmetric half-bridge flyback converter.
[0079] In one embodiment, the control circuit also includes a primary second sampling circuit 14, the sampling end of the primary second sampling circuit 14 is arranged in the primary loop or the secondary loop, and the output end of the third sampling circuit is connected to the primary controller; the primary second sampling circuit 14 is used to sample the voltage information and current information of the primary winding or the secondary winding, and the primary controller 10 is used to control the opening and closing of the asymmetric half-bridge flyback converter according to the voltage information and current information of the primary winding or the secondary winding.
[0080] In one embodiment, the primary controller 10 is used to perform circuit protection on the asymmetric half-bridge flyback converter according to voltage information and current information of the primary winding or the secondary winding.
[0081] In one embodiment, the primary controller 10 is used to perform valley control on the asymmetric half-bridge flyback converter according to voltage information and current information of the primary winding or the secondary winding.
[0082] Please continue to see Figure 7 or Figure 8 As shown, in some embodiments, the primary second sampling circuit 14 includes an auxiliary winding, a first resistor R1 and a second resistor R2; the auxiliary winding is coupled to the secondary winding of the transformer T, the first end of the auxiliary winding is grounded GND, the second end of the auxiliary winding is connected to the first end of the first resistor R1, the second end of the first resistor R1 is connected to the first end of the second resistor R2, and the second end of the second resistor R2 is grounded; the first end of the second resistor R2 is the output end of the third sampling circuit 14, and the first end of the second resistor R2 is connected to the first controller 10. It can be understood that the voltage or current information of the secondary winding can be sampled through the auxiliary winding and the first resistor R1 and the second resistor R2.
[0083] In some embodiments, the control circuit also includes an isolation communication unit 30, which is arranged on the communication loop of the primary controller 10 and the secondary controller 20, so that the primary controller 10 and the secondary controller 20 can avoid signal interference while ensuring communication, thereby ensuring the stability of circuit operation.
[0084] Fig. 9 For the fifth schematic diagram of the control circuit structure provided in the embodiment of the present application, please refer to Fig. 9As shown, the control circuit of this embodiment is the same as the control circuit provided in the above embodiment, and also includes a primary controller 10 and a secondary controller 20. In addition, the control circuit also includes a primary first sampling circuit 13, a primary second sampling circuit 14, a secondary sampling circuit 15, a first drive circuit 11, a second drive circuit 12 and a third drive circuit 16. These circuits are the same as those in the above embodiment and are not described here. Different from the above embodiment, the asymmetric half-bridge flyback converter of this embodiment is a high-side synchronous rectification type, that is, the third transistor Q3 is arranged on the loop upstream of the third capacitor C3.
[0085] Fig.10 For the sixth schematic diagram of the control circuit structure provided in the embodiment of the present application, please refer to Fig.10 As shown, Fig.10 The asymmetric half-bridge flyback converter in the embodiment is another common structure of the asymmetric flyback converter. Fig. 9 Unlike the asymmetric half-bridge flyback converter shown, when the second transistor Q2 is turned on, the current of the resonant inductor and the excitation inductor increases, and the resonant capacitor stores energy. When the first transistor Q1 is turned on, the resonant capacitor resonates with the resonant inductor and transmits energy to the secondary through the transformer. Among them, the control circuit of this embodiment also includes a secondary controller 10 and a secondary controller 20. In addition, the control circuit also includes a primary first sampling circuit 13, a primary second sampling circuit 14, a secondary sampling circuit 15, a first drive circuit 11, a second drive circuit 12 and a third drive circuit 16. These circuits are similar to those in the above embodiments and are not repeated here.
[0086] The present application also provides an asymmetric half-bridge flyback converter, which includes a control circuit as described in any one of the above items. The circuit structure of the asymmetric half-bridge flyback converter can be found in Figure 6 to Figure 10 As can be understood from the circuit structure shown, the asymmetric half-bridge flyback converter has the same technical effects as the above-mentioned control circuits due to the introduction of the control circuits provided by the above-mentioned embodiments, and thus will not be described in detail here.
[0087] Fig.11 Flowchart of the control method of the asymmetric half-bridge flyback converter provided in the embodiment of the present application. The control method can be applied to the asymmetric half-bridge flyback converter provided in the above embodiments. Fig.11 As shown, the control method includes:
[0088] S110 . In each working cycle, after the second transistor is turned on, obtain a secondary current value in the secondary loop.
[0089] S111, determining whether the secondary current value is greater than or equal to a first current threshold, and if so, controlling to turn off the second transistor.
[0090] According to the control method provided in this embodiment, when the load size at the output end of the asymmetric half-bridge flyback converter changes, causing the secondary current value of the asymmetric half-bridge flyback converter to be too large, the second transistor Q2 can be immediately turned off to quickly reduce the resonant current value of the resonant cavity of the asymmetric half-bridge flyback converter, thereby avoiding the resonant current value of the resonant cavity being too large to damage components in the circuit, thereby ensuring the working life of the asymmetric half-bridge flyback converter.
[0091] In one embodiment, the control method further includes: when the asymmetric half-bridge flyback converter operates in the DCM mode, at the start of each working cycle, the secondary first controls the second transistor Q2 to be pre-conducted for a first time length T zvspulse In other words, at the beginning of each working cycle, the second transistor Q2 is first controlled to turn on, and the second transistor Q2 is turned on for the first time length T zvspulse After that, the second transistor Q2 is controlled to be turned off. After the second transistor Q2 is turned off, the second dead time T dead2 Then, the first transistor Q1 is turned on.
[0092] According to the above description, it can be known that the second transistor Q2 is pre-conducted for the first time length T zvspulse After that, the secondary current I in the secondary circuit SEC The zero crossing turns negative. Due to the resonance effect of transformer T, the excitation inductance current I in transformer T at this time mag It will also cross zero and become negative, and then when the first transistor Q1 is turned on, the first transistor Q1 is a zero voltage switch, which improves the working efficiency of the asymmetric half-bridge flyback converter. And according to the control method provided in this embodiment, the risk of the first transistor Q1 and the third transistor Q3 being turned on at the same time is avoided, thereby avoiding damage to the components in the circuit and ensuring the working life of the circuit.
[0093] Based on the control circuits provided in the above embodiments, this embodiment further provides a chip, which includes the control circuit as described above.
[0094] Based on the control circuits provided in the above embodiments, this embodiment further provides an electronic device, which includes the control circuit described above; or the electronic device includes the asymmetric half-bridge flyback converter described above.
[0095] It is understandable that the electronic device of this embodiment may be an electronic device such as a power adapter, a smart phone, a tablet computer, a laptop computer, etc.
[0096] Finally, it should be noted that the above embodiments are only specific implementation methods of the present application, but the protection scope of the present application is not limited thereto, and any changes or substitutions within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.
Claims
1. A control circuit for an asymmetric half-bridge flyback converter, the asymmetric half-bridge flyback converter comprising: A first transistor, a second transistor, a third transistor, a transformer, a first capacitor, a second capacitor, a third capacitor and a first inductor; the first transistor, the second transistor, the first capacitor, the second capacitor and the first inductor are arranged in a primary loop where the primary winding of the transformer is located, and the third transistor and the third capacitor are arranged in a secondary loop where the secondary winding of the transformer is located; The control circuit comprises a primary controller, a secondary controller and a secondary sampling circuit; the primary controller is connected to the control electrodes of the first transistor and the second transistor respectively, and the secondary controller is connected to the control electrode of the third transistor; The sampling end of the secondary sampling circuit is arranged in the secondary loop, and the output end of the secondary sampling circuit is connected to the secondary controller; the secondary sampling circuit is used to sample the secondary current value in the secondary loop in each working cycle, and output the secondary current value to the secondary controller; the secondary controller is used to send a first control signal to the primary controller when it is determined that the secondary current value is greater than or equal to a first current threshold value; The primary controller is used for controlling the second transistor to be turned off according to the first control signal.
2. The control circuit according to claim 1, characterized in that: The secondary sampling circuit is a voltage sampling circuit; the secondary sampling circuit is used to sample the source-drain voltage of the third transistor in the secondary loop; The secondary controller is further used to determine the secondary current value in the secondary loop according to the source-drain voltage of the third transistor and the on-resistance of the third transistor.
3. The control circuit according to claim 1, characterized in that: The control circuit further comprises a secondary sampling resistor, wherein the secondary sampling resistor is connected in series in the secondary loop; The secondary sampling circuit is a voltage sampling circuit; the secondary sampling circuit is used to sample the voltage value on the secondary sampling resistor in the secondary loop; The secondary controller is further used to determine the secondary current value according to the voltage value on the secondary sampling resistor and the resistance value of the secondary sampling resistor.
4. The control circuit according to claim 1, characterized in that: The control circuit further comprises a primary first sampling circuit, a sampling end of the primary first sampling circuit is arranged in the primary loop, and an output end of the primary first sampling circuit is connected to the primary controller; The primary first sampling circuit is used to sample the resonant current value in the primary loop and output the sampled resonant current value to the primary controller; The primary controller is configured to control turning off the second transistor when determining that the resonant current value is greater than or equal to a second current threshold; Or the primary controller is used to determine the resonant current value in the primary loop according to the secondary current value, and when it is determined that the resonant current value is greater than or equal to a second current threshold, control the second transistor to be turned off.
5. The control circuit according to claim 1, characterized in that: The control circuit further comprises a primary second sampling circuit, a sampling end of the primary second sampling circuit is arranged in the primary loop or the secondary loop, and an output end of the primary second sampling circuit is connected to the primary controller; The primary second sampling circuit is used to sample the voltage information and current information of the primary winding or the secondary winding, and the primary controller is used to control the opening and closing of the asymmetric half-bridge flyback converter according to the voltage information and current information of the primary winding or the secondary winding; Alternatively, the primary controller is used to perform circuit protection on the asymmetric half-bridge flyback converter according to the voltage information and current information of the primary winding or the secondary winding; Alternatively, the primary controller is used to perform valley control on the asymmetric half-bridge flyback converter according to voltage information and current information of the primary winding or the secondary winding.
6. The control circuit according to claim 5, characterized in that: The primary second sampling circuit includes an auxiliary winding, a first resistor and a second resistor; The auxiliary winding is coupled to the secondary winding of the transformer, the first end of the auxiliary winding is grounded, the second end of the auxiliary winding is connected to the first end of the first resistor, the second end of the first resistor is connected to the first end of the second resistor, and the second end of the second resistor is grounded; the first end of the second resistor is the output end of the primary second sampling circuit, and the first end of the second resistor is connected to the primary controller.
7. An asymmetric half-bridge flyback converter, characterized in that: The asymmetric half-bridge flyback converter comprises: a first transistor, a second transistor, a third transistor, a transformer, a first capacitor, a second capacitor, a third capacitor and a first inductor; the first transistor, the second transistor, the first capacitor, the second capacitor and the first inductor are arranged in a primary loop where the primary winding of the transformer is located, and the third transistor and the third capacitor are arranged in a secondary loop where the secondary winding of the transformer is located; The asymmetric half-bridge flyback converter also includes a control circuit as described in any one of claims 1-6.
8. A control method for an asymmetric half-bridge flyback converter, the asymmetric half-bridge flyback converter comprising: A first transistor, a second transistor, a third transistor, a transformer, a first capacitor, a second capacitor, a third capacitor and a first inductor; the first transistor, the second transistor, the first capacitor, the second capacitor and the first inductor are arranged in a primary loop where the primary winding of the transformer is located, and the third transistor and the third capacitor are arranged in a secondary loop where the secondary winding of the transformer is located; Characterized in that the control method comprises: In each working cycle, after the second transistor is turned on, obtaining a secondary current value in the secondary loop; Determine whether the secondary current value is greater than or equal to a first current threshold, and if so, control turning off the second transistor.
9. A chip, characterized in that: The chip comprises the control circuit as described in any one of claims 1-6.
10. An electronic device, characterized in that: The electronic device comprises the control circuit as claimed in any one of claims 1 to 6; or the electronic device comprises the asymmetric half-bridge flyback converter as described above.