Differential switched capacitor amplifier and wireless transceiver

Abstract

The invention relates to the technical field of integrated circuits, and discloses a differential switched capacitor amplifier, which comprises two switched capacitor amplification units, the input ends of which are respectively connected with two input signals with opposite phases; the balance-unbalance converter is connected with the output ends of the two switched capacitor amplification units and used for converting the differential signals output by the switched capacitor amplification units into single-ended signals; wherein each switched capacitor amplification unit is split into two subunits which are connected in parallel and have non-common-mode level signals, and each subunit comprises an amplifier and a coupling capacitor. According to the circuit, each differential switch amplification unit is divided into two subunits. After the two subunits are subjected to signal synthesis at an output node, the differential switch amplification unit outputs stable common-mode voltage, so that the purpose of suppressing low-frequency spurious components is achieved. Meanwhile, the circuit is simple in structure, and the robustness of the circuit is enhanced. The invention also discloses a wireless transceiver.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit technology, for example, to a differential switched capacitor amplifier and a wireless transceiver. Background Art

[0002] In ultra-wideband wireless transceivers, since the bandwidth of the frequency band they occupy is very wide, in order to prevent radio frequency signals from interfering with other communication equipment, the International Communications Organization has strictly restricted the RF (Radio Frequency) signal spectrum of broadband systems and provided specific spectrum templates. The SCPA (Switched-Capacitor Power Amplifier) ​​circuit in the wireless transmitter is the core circuit module of the wireless transceiver, which amplifies and controls the power of the RF signal. When the SCPA circuit is applied to a wireless transmitter, the common-mode voltage at the output changes with the transmission pulse, which may cause frequency components that exceed the allowable range in the low-frequency band close to DC, thereby violating the spectrum template.

[0003] The related technology discloses a switched capacitor amplifier, comprising: an input capacitor; an input switch, arranged between an input terminal of the switched capacitor amplifier and the input capacitor; a first reference voltage switch, arranged between a connection point between the input capacitor and the input switch and a reference voltage input terminal of the switched capacitor amplifier; an output capacitor, whose capacitance value is smaller than that of the input capacitor; an output switch, arranged between the output capacitor and an output terminal of the switched capacitor amplifier; an internal amplifier, amplifying an input voltage according to a capacitance ratio between the input capacitor and the output capacitor and outputting an output voltage; a holding capacitor, charged by a charge generated by the output voltage; and a control circuit, outputting a first clock signal for controlling the first reference voltage switch, a second clock signal for controlling the input switch, and a third clock signal for controlling the output switch, so as to control the output switch to be turned on after a predetermined time has passed since the first reference voltage switch was turned off and the input switch was turned on during sampling.

[0004] In the process of implementing the embodiments of the present disclosure, it is found that there are at least the following problems in the related art:

[0005] Although the related technology can suppress the fluctuation of common mode voltage, the circuit structure is complex.

[0006] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present application, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention

[0007] In order to provide a basic understanding of some aspects of the disclosed embodiments, a brief summary is given below. The summary is not an extensive review, nor is it intended to identify key / critical components or delineate the scope of protection of these embodiments, but rather serves as a prelude to the detailed description that follows.

[0008] The embodiments of the present disclosure provide a differential switched capacitor amplifier and a wireless transceiver, and provide a circuit structure with a simple structure to suppress the fluctuation of the common mode voltage.

[0009] In some embodiments, the differential switched capacitor amplifier includes: two switched capacitor amplifying units, whose input ends are respectively connected to two input signals with opposite phases; a balanced-unbalanced converter connected to the output ends of the two switched capacitor amplifying units, and used to convert the differential signal output by the switched capacitor amplifying unit into a single-ended signal; wherein each switched capacitor amplifying unit is split into two sub-units connected in parallel and having non-common mode level signals, and each sub-unit includes an amplifier and a coupling capacitor.

[0010] In some embodiments, the wireless transmitter includes: a differential switched capacitor amplifier as described above.

[0011] The differential switched capacitor amplifier and wireless transceiver provided by the embodiments of the present disclosure can achieve the following technical effects:

[0012] In the disclosed embodiment, each differential switch amplifier unit is split into two subunits. Each subunit includes an amplifier and a coupling capacitor, and the common-mode voltage signals of the branches where the two subunits are located are different. In this way, after the two subunits perform signal synthesis at the common node, the differential switch amplifier unit outputs a stable common-mode voltage to achieve the purpose of suppressing low-frequency stray components. At the same time, the circuit structure is simple and the circuit robustness is enhanced.

[0013] The above general description and the following description are exemplary and explanatory only and are not intended to limit the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] One or more embodiments are exemplarily described by corresponding drawings, which do not limit the embodiments. Elements with the same reference numerals in the drawings are shown as similar elements, and the drawings do not constitute a scale limitation, and wherein:

[0015] Figure 1 is a structural schematic diagram of a traditional differential switched capacitor amplifier provided by an embodiment of the present disclosure;

[0016] Figure 2 is a schematic diagram of a differential switch amplification unit of a traditional differential switch capacitor amplifier provided in an embodiment of the present disclosure;

[0017] Figure 3 is a structural schematic diagram of a differential switched capacitor amplifier provided by an embodiment of the present disclosure;

[0018] Figure 4 is a circuit structure diagram of a differential switched capacitor amplification unit provided in an embodiment of the present disclosure;

[0019] Figure 5 is a schematic diagram of an output waveform of a differential switched capacitor amplification unit provided by an embodiment of the present disclosure;

[0020] Figure 6 is a state schematic diagram of a differential switched capacitor amplifier unit when the differential switched capacitor amplifier provided by an embodiment of the present disclosure is turned off;

[0021] Figure 7 is a simplified model schematic diagram of a differential switched capacitor amplifier provided by an embodiment of the present disclosure;

[0022] Figure 8 It is a frequency performance comparison diagram provided by an embodiment of the present disclosure.

[0023] Reference numerals:

[0024] 10: switched capacitor amplifier unit; 20: balanced-unbalanced converter; 11: amplifier; 12: coupling capacitor; 11a: first amplifier; 12a: first coupling capacitor; 13a: first logic unit; 11b: second amplifier; 12b: second coupling capacitor; 13b: second logic unit; nand: NAND gate; inv: invert gate; nor: NOR gate. DETAILED DESCRIPTION

[0025] In order to be able to understand the features and technical contents of the embodiments of the present disclosure in more detail, the implementation of the embodiments of the present disclosure is described in detail below in conjunction with the accompanying drawings. The attached drawings are for reference only and are not used to limit the embodiments of the present disclosure. In the following technical description, for the convenience of explanation, a full understanding of the disclosed embodiments is provided through multiple details. However, one or more embodiments can still be implemented without these details. In other cases, to simplify the drawings, well-known structures and devices can be simplified for display.

[0026] The terms "first", "second", etc. in the specification and claims of the embodiments of the present disclosure and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the terms used in this way can be interchanged where appropriate, so that the embodiments of the embodiments of the present disclosure described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions.

[0027] In the embodiments of the present disclosure, the terms "upper", "lower", "inside", "middle", "outside", "front", "back" and the like indicate directions or positional relationships based on the directions or positional relationships shown in the accompanying drawings. These terms are mainly intended to better describe the embodiments of the present disclosure and their embodiments, and are not intended to limit the indicated devices, elements or components to have a specific direction, or to be constructed and operated in a specific direction. Moreover, in addition to being used to indicate directions or positional relationships, some of the above terms may also be used to indicate other meanings. For example, the term "upper" may also be used to indicate a certain dependency or connection relationship in certain circumstances. For those of ordinary skill in the art, the specific meanings of these terms in the embodiments of the present disclosure can be understood according to specific circumstances.

[0028] In addition, the terms "disposed", "connected", and "fixed" should be understood in a broad sense. For example, "connected" can be a fixed connection, a detachable connection, or an integral structure; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate medium, or it can be an internal connection between two devices, elements, or components. For those of ordinary skill in the art, the specific meanings of the above terms in the embodiments of the present disclosure can be understood according to specific circumstances.

[0029] Unless otherwise stated, the term "plurality" means two or more.

[0030] In the embodiment of the present disclosure, the character " / " indicates that the preceding and following objects are in an "or" relationship. For example, A / B indicates: A or B.

[0031] The term "and / or" is a description of the association relationship between objects, indicating that three relationships can exist. For example, A and / or B means: A or B, or, A and B.

[0032] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present disclosure may be combined with each other.

[0033] Combination Figure 1 As shown in FIG. 1 , the conventional differential switched capacitor amplifier includes two switched capacitor amplifying units with inverted input signals and a balanced-unbalanced converter. The switched capacitor amplifying unit includes an amplifier and a capacitor. When processing pulse radio, the signal amplitude will continue to swing, which affects the impedance of the amplifier to the power supply or to the ground, thereby affecting the common-mode level of the amplifier output node (such as Figure 2 , the common-mode level is unstable and changes in an arc. Therefore, the switched capacitor amplifier will amplify the common-mode signal and affect the final spectrum. If no measures are taken to combat common-mode fluctuations, the common-mode level at the amplifier output node will be higher than V DD / 2, there will be a lot of low-frequency components in the output signal. Then, the common-mode level of the output voltage will be directly pulled to the power rail or ground, resulting in blocking of the transmission signal.

[0034] To solve the above problems, combined with Figure 3 As shown, an embodiment of the present disclosure provides a differential switched capacitor amplifier, including two switched capacitor amplifying units 10 and a balanced-unbalanced converter 20 (i.e., Balun). The input ends of the two switched capacitor amplifying units 10 are respectively connected to two input signals with opposite phases. The balanced-unbalanced converter 20 is connected to the output ends of the two switched capacitor amplifying units 10, and is used to convert the differential signal output by the switched capacitor amplifying unit 10 into a single-ended signal. Each switched capacitor amplifying unit 10 is split into two parallel sub-units with two different common-mode level signals, and each sub-unit includes an amplifier 11 and a coupling capacitor 12.

[0035] Here, the two input signals of the differential switched capacitor amplifier with opposite phases are differential RF signals LO_P and LO_N. The two differential RF signals are amplified by a switched capacitor amplifier unit respectively. The two amplified signals are converted into single-ended signals through a balanced-unbalanced converter and supplied to the load (i.e., R L ). In the disclosed embodiment, in order to stabilize the common-mode voltage and achieve the goal of suppressing low-frequency stray components, each switched capacitor amplification unit is split into two sub-units, and the two sub-units have different common-mode levels (i.e., the common-mode voltage of the branch where each sub-unit is located, and the voltage output by each unit is referred to as the branch common-mode voltage hereinafter). Each sub-unit includes an amplifier and a coupling capacitor.

[0036] Due to the different common-mode levels of the two sub-units, the common-mode voltage of the synthesized output signal (i.e., the average voltage output by the two sub-units of the switched capacitor amplifier unit at the output node, hereinafter referred to as the common-mode voltage) is stable, thereby achieving the suppression of low-frequency stray components. In addition, the circuit structure of the embodiment of the present disclosure is simple, and the circuit robustness is enhanced.

[0037] In addition, the two sub-units having different common-mode levels can generate two different branch common-mode voltages by controlling the input signals of the amplifiers of the sub-units. As an example, the control signals are provided to the two sub-units by a controller.

[0038] Using the differential switch capacitor amplifier provided in the embodiment of the present disclosure, each differential switch amplifier unit is split into two subunits. Each subunit includes an amplifier and a coupling capacitor, and the common-mode level signals of the branches where the two subunits are located are different. In this way, after the two subunits perform signal synthesis at the common node, the differential switch amplifier unit outputs a stable common-mode voltage to achieve the purpose of suppressing low-frequency stray components. At the same time, the circuit structure is simple and the circuit robustness is enhanced.

[0039] Optionally, the capacitance value of the coupling capacitor 12 of each sub-unit is 1 / 2 of the initial capacitance value; wherein the initial capacitance value is the capacitance value of each switch capacitor amplification unit before being split.

[0040] Here, the coupling capacitance of each sub-unit is half of the capacitance (i.e., initial capacitance) in the switched capacitor amplifier unit before splitting. In this way, the output power, efficiency, and frequency of the switched capacitor amplifier unit of the two sub-units split into remain consistent with those before splitting; and the power consumption and area of ​​the circuit are not increased. As an example, the initial capacitance of the switched capacitor amplifier unit in the traditional differential switched capacitor amplifier is Ccu, and the coupling capacitance of the sub-unit in the embodiment of the present disclosure is Ccu / 2.

[0041] Optionally, each switched capacitor amplification unit includes a first subunit and a second subunit. The first subunit includes a first logic unit 13a, a first amplifier 11a and a first coupling capacitor 12a. The second subunit includes a second logic unit 13b, a second amplifier 11b and a second coupling capacitor 12b.

[0042] The first logic unit 13a and the second logic unit 13b are both connected to the input signal and the control signal to provide bias control signals for the first amplifier 11a and the second amplifier 11b. One end of the first coupling capacitor 12a and the second coupling capacitor 12b are used as output nodes to output differential signals.

[0043] Here, the differential switched capacitor amplifier is provided with a control signal, and the output signals of the first logic unit and the second logic unit of the differential switched capacitor amplifier are controlled by the control signal and the input signal. In the disclosed embodiment, the subunit of the switched capacitor amplifier unit also includes a logic unit, which is used to perform logical operations on the input signal and the control signal to provide different bias control signals for the first amplifier and the second amplifier of the two subunits when the differential switched capacitor amplifier is not working. Under the action of the bias control signal, the first subunit and the second subunit generate two different branch common mode levels. Furthermore, when the differential switched capacitor amplifier is working, the common mode voltage of the first subunit and the second subunit at the output node is stable.

[0044] In addition, when the differential switched capacitor amplifier is working, the output signals of the first logic unit and the second logic unit are the same. Therefore, the first subunit and the second subunit of the switched capacitor amplifier unit have the same working state to achieve amplification of the input signal. Figure 5 As shown, the input signal of the switched capacitor amplifier unit is LO, and the output signal is OUT; the first amplifier is Ap, and the second amplifier is Bp. Then the output signal of the first subunit is a negative signal, and the output signal of the second subunit is a positive signal, and a complete RF pulse signal is generated after coupling by the coupling capacitor. In the figure, the branch common mode voltage (arc in the waveform) vibrates as the pulse signal amplitude swings, and the branch common mode levels of the two subunits are different, so the common mode voltage of the output signal OUT is stable after coupling.

[0045] Optionally, the control signal is an enable signal. When the enable signal is disabled, the first logic unit 13a and the second logic unit 136 generate control signals with opposite logics.

[0046] Here, when the enable signal (i.e., Enable) is not enabled, the differential switched capacitor amplifier does not work. In order to achieve common mode stability, the enable signal is used to enable the first logic unit and the second logic unit to generate control signals of opposite logic. As an example, when the enable signal is set to 0 and is not enabled, the bias control signal obtained by the first logic unit through logical operation is a high level, and the bias control signal obtained by the second logic unit through logical operation is a low level. In this way, the states of the first amplifier and the second amplifier are different, which makes the output voltage of the branch different. In this way, the common mode voltages of the two branches are different, the common mode voltage is stabilized, and the low-frequency spectrum quality in the transmitted signal is improved.

[0047] Optionally, when the enable signal is not enabled, the common mode signal of the output node of the first subunit and the second subunit is V DD / 2; where V DD is the voltage of the power supply.

[0048] Here, as shown above, when the enable signal is not enabled, under the action of the first logic unit and the second logic unit, the control signals of the first amplifier and the second amplifier are different, so that there is a voltage difference between the branch output voltages. Among them, one branch output voltage is connected to the ground, and one branch output voltage is connected to the power supply V DD ; so that the common mode voltage remains at the middle value of the power supply voltage V DD / 2 nearby.

[0049] Combination Figure 4 As shown, optionally, the first logic unit 13a includes a NAND gate nand, two input terminals of the NAND gate nand are respectively connected to an enable signal and an input signal, and an output terminal is connected to the first amplifier 11a.

[0050] Here, the differential switched capacitor amplifier is set not to work when the enable signal Enable = 0, and to work when Enable = 1; the input signal is a square wave. Then, when the square wave signal is high and the enable signal is enabled, the first logic unit outputs a low level. When the square wave signal is low and the enable signal is enabled, the first logic unit outputs a high level. However, when the enable signal is not enabled, regardless of whether the square wave signal is low or high, the first logic unit outputs a high level, and the branch output voltage, i.e., the branch common mode voltage, is pulled to ground, and the branch common mode voltage is 0.

[0051] Optionally, the second logic unit 13b includes an invertor inv and a NOR gate nor. The invertor inv has an input end connected to the enable signal and an output end connected to the input end of the NOR gate nor. One input end of the NOR gate nor is connected to the input signal, the other input end is connected to the output end of the invertor inv, and the output end is connected to the second amplifier 11b.

[0052] Here, like the first logic unit, when the square wave signal is high and the enable signal is enabled, the second logic unit outputs a low level. When the square wave signal is low and the enable signal is enabled, the second logic unit outputs a high level. That is, when the differential switched capacitor amplifier is working, the logic unit output signals of the first subunit and the second subunit are the same. However, when the enable signal is not enabled, regardless of whether the direction signal is low or high, the second logic unit outputs a low level, and the output voltage of the branch, that is, the common-mode voltage of the branch, is pulled to the voltage of the power supply, and the common-mode voltage of the branch is V DD .

[0053] In this way, when the enable signal is not enabled, the first logic unit and the second logic unit output different logic signals, thereby realizing the processing of the common mode voltage of the output node. Even if the common mode voltage is maintained at the middle value V DD / 2 to resist common mode voltage fluctuations.

[0054] Optionally, the amplifiers 11 a / 11 b of the two sub-units of each switched capacitor amplification unit are a group of inverting amplifiers.

[0055] Here, the amplifier 11a / 11b of each subunit is an inverting amplifier, which has a stronger anti-interference ability. The input signal is input to the inverting input terminal of the amplifier to obtain an output signal inverted to the input signal.

[0056] Optionally, the amplifier 11a / 11b of each subunit includes a PMOS tube and an NMOS tube. The source of the PMOS tube is connected to the power supply, the gate is connected to the input signal, and the drain is connected to the coupling capacitor. The source of the NMOS tube is grounded, the gate is connected to the gate of the PMOS tube, and the drain is connected to the drain of the PMOS tube.

[0057] Combination Figure 4 The first amplifier includes a PMOS tube M1 and an NMOS tube M2. When the enable signal is enabled, when the first logic unit 13a outputs a high level, the PMOS tube M1 is turned off, the NMOS tube M2 is turned on, and the first coupling capacitor 12a is discharged. When the first logic unit 13a outputs a low level, the PMOS tube M1 is turned on, the NMOS tube M2 is turned off, and the first coupling capacitor 12a is charged.

[0058] The working principle of the second amplifier 11b is the same as that of the first amplifier 11a. When the enable signal is enabled, when the second logic unit 13b outputs a high level, the PMOS tube M3 is turned off, the NMOS tube M4 is turned on, and the second coupling capacitor 12b is discharged. When the first logic unit 13b outputs a low level, the PMOS tube M1 is turned on, the NMOS tube M2 is turned off, and the first coupling capacitor 12a is charged.

[0059] Because the two RF signal paths have different branch common mode levels, RF synthesis is performed at the output node through coupling capacitors, thereby achieving the stability of the common mode point and improving the low-frequency spectrum quality of the transmitted signal.

[0060] Combination Figure 6 , when the enable signal is not enabled, the first logic unit 13a outputs a high level, and the second logic unit 13b outputs a low level. The NMOS tube M2 of the first amplifier is turned on, the first coupling capacitor 12a is discharged, and the branch common mode voltage is pulled down and biased to ground. The PMOS tube M3 of the second amplifier is turned on, the second coupling capacitor 12b is charged, and the branch common mode voltage is pulled up and biased to the power supply voltage. Therefore, the common mode voltage of the output node is V DD / 2. In addition, it should be noted that Figure 4 and Figure 6 The waveform of the RF pulse signal output in is a schematic waveform.

[0061] The differential switched capacitor amplifier of the embodiment of the present disclosure is analyzed in principle. Figure 7 As shown, Figure 7 is a simplified model of a differential switched capacitor amplifier. The input signal is two pulse signals v with the same RF component and opposite common mode. in1 (t), v in2 (t), input signal v in1 (t), v in2(t) is used to represent a single unshaped pulse:

[0062]

[0063] Where ω0 is the carrier frequency, τ c is the width of the pulse, u(t) is the unit impulse function, and in the above formula (2), π / ω0 is equal to half a period of the RF signal. Perform Laplace transform on the simplified circuit model and analyze it in the frequency domain:

[0064]

[0065] Take the Laplace transform of two input signals:

[0066]

[0067] In the above analysis, we need τ c It is an integer multiple of 2π / ω0, that is, the pulse is an integer period of the RF signal. It can be seen that the spectrum of the output signal represents the sum of the two input signals, the cascade of the first-order high-pass filter, and the expression is:

[0068]

[0069] Near the carrier frequency (s=jω≈jω0), there will be no interference in signal amplification. In the low-frequency part (ω<<ω0), the signal will decay exponentially and has nothing to do with the size of the coupling capacitor. Assume that the parameter size is: C=1pF, R L =50Ω,ω / 2π=4GHz.

[0070] Depend on Figure 8 It can be seen that the differential switched capacitor amplifier (Dual Capacitors) of the embodiment of the present disclosure has a power spectral density (PSD) of 4.4dB more attenuation than the first-order high-pass filter (No Capacitor) at the edge of the 960MHz-1610MHz frequency band, and the first-order high-pass filter has a 2.7dB less attenuation than the direct coupling (Single Capacitors). Therefore, the differential switched capacitor amplifier of the embodiment of the present disclosure can provide sufficient attenuation to meet the compliance of the spectrum specified by the radio spectrum management agency.

[0071] An embodiment of the present disclosure provides a wireless transceiver, comprising the aforementioned differential switched capacitor amplifier.

[0072] The above description and the accompanying drawings sufficiently illustrate the embodiments of the present disclosure to enable those skilled in the art to practice them. Other embodiments may include structural and other changes. The embodiments represent only possible variations. Unless explicitly required, individual components and functions are optional, and the order of operations may vary. Portions and features of some embodiments may be included in or replace portions and features of other embodiments. The embodiments of the present disclosure are not limited to the structures described above and shown in the accompanying drawings, and various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.

Claims

1. A differential switched capacitor amplifier, characterized in that: include: Two switched capacitor amplifier units, the input ends of which are respectively connected to two input signals with opposite phases; A balanced-unbalanced converter connected to the output ends of the two switched capacitor amplifying units, and used for converting the differential signals output by the switched capacitor amplifying units into single-ended signals; Each switched capacitor amplifying unit is split into two sub-units connected in parallel and having non-common mode level signals, and each sub-unit includes an amplifier and a coupling capacitor.

2. The differential switched capacitor amplifier according to claim 1, wherein: The capacitance value of the coupling capacitor of each subunit is 1 / 2 of the initial capacitance value; The initial capacitance value is the capacitance value of each switch capacitor amplification unit before it is split.

3. The differential switched capacitor amplifier according to claim 1, wherein: Each switched capacitor amplifier unit includes: A first subunit, comprising a first logic unit, a first amplifier and a first coupling capacitor; A second subunit, comprising a second logic unit, a second amplifier and a second coupling capacitor; The first logic unit and the second logic unit are connected to input signals and control signals to provide bias control signals for the first amplifier and the second amplifier; one end of the first coupling capacitor and the second coupling capacitor serves as an output node to output a differential signal.

4. The differential switched capacitor amplifier according to claim 3, characterized in that: The control signal is an enable signal. When the enable signal is disabled, the first logic unit and the second logic unit generate bias control signals of opposite logic.

5. The differential switched capacitor amplifier according to claim 4, characterized in that: When the enable signal is not enabled, the common mode level of the output nodes of the first subunit and the second subunit is V DD / 2; Among them, V DD is the voltage of the power supply.

6. The differential switched capacitor amplifier according to claim 4, characterized in that: The first logic unit comprises: The NAND gate has two input terminals connected to the enable signal and the input signal respectively, and an output terminal connected to the first amplifier.

7. The differential switched capacitor amplifier according to claim 4, wherein: The second logic unit includes: NOT gate, the input terminal is connected to the enable signal; The NOR gate has one input terminal connected to the input signal, another input terminal connected to the output terminal of the NOR gate, and an output terminal connected to the second amplifier.

8. The differential switched capacitor amplifier according to claim 1, wherein: The amplifiers of the two sub-units of each switched capacitor amplification unit are inverting amplifiers.

9. The differential switched capacitor amplifier according to claim 1, wherein: The amplifier comprises: PMOS tube, the source is connected to the power supply, the gate is connected to the input signal, and the drain is connected to the coupling capacitor; The NMOS tube has a source connected to the ground, a gate connected to the gate of the PMOS tube, and a drain connected to the drain of the PMOS tube.

10. A wireless transceiver, characterized in that: Comprising the differential switched capacitor amplifier according to any one of claims 1 to 9.

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