Semiconductor device and method for manufacturing semiconductor device

Abstract

The present disclosure provides a semiconductor device that is easy to manufacture and a method of manufacturing the semiconductor device. A method for manufacturing a semiconductor device includes: forming a first nitride semiconductor layer having nitrogen polarity on an upper surface; forming a first dielectric film over the first nitride semiconductor layer; forming a first opening for exposing a part of the first nitride semiconductor layer in the first dielectric film; forming a second nitride semiconductor layer inside the first opening and over the first nitride semiconductor layer; forming, after the step of forming the second nitride semiconductor layer, a second opening through which a part of the first nitride semiconductor layer is exposed in the first dielectric film; forming a second dielectric film inside the second opening and over the first nitride semiconductor layer; forming an ohmic electrode in ohmic contact with the second nitride semiconductor layer; and forming a gate electrode over the second opening and over the second dielectric film.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing the semiconductor device. Background Art

[0002] A high electron mobility transistor (HEMT) having a structure in which a channel layer is formed on a barrier layer has been proposed. Also proposed is a transistor in which a hafnium silicate film having a high relative dielectric constant is used for a gate insulating film.

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Document 1: Japanese Patent Application Publication No. 2007-329483

[0006] Patent Document 2: Japanese Patent Application No. 2010-510680

[0007] However, conventionally, even if one attempts to manufacture a HEMT having a structure in which a channel layer is formed on a barrier layer and a hafnium silicate film is used for a gate insulating film, it is difficult to control etching and the like. Summary of the invention

[0008] An object of the present disclosure is to provide a semiconductor device that is easy to manufacture and a method for manufacturing a semiconductor device.

[0009] The manufacturing method of the semiconductor device disclosed in the present invention comprises the following steps: forming a first nitride semiconductor layer having a nitrogen polarity on its upper surface; forming a first dielectric film on the first nitride semiconductor layer; forming a first opening in the first dielectric film to expose a portion of the first nitride semiconductor layer; forming a second nitride semiconductor layer on the inner side of the first opening and on the first nitride semiconductor layer; after the step of forming the second nitride semiconductor layer, forming a second opening in the first dielectric film to expose a portion of the first nitride semiconductor layer; forming a second dielectric film on the inner side of the second opening and on the first nitride semiconductor layer; forming an ohmic electrode in ohmic contact with the second nitride semiconductor layer; and forming a gate electrode above the second opening and on the second dielectric film.

[0010] Effects of the Invention

[0011] According to the present disclosure, a semiconductor device can be easily manufactured. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 is a cross-sectional view showing a semiconductor device according to an embodiment.

[0013] Figure 2 It is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment (Part 1).

[0014] Figure 3 This is a cross-sectional view showing the method for manufacturing a semiconductor device according to the embodiment (part 2).

[0015] Figure 4 It is a cross-sectional view showing the method for manufacturing a semiconductor device according to the embodiment (part 3).

[0016] Figure 5 It is a cross-sectional view showing the method for manufacturing a semiconductor device according to an embodiment (Part 4).

[0017] Figure 6 This is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment (Part 5).

[0018] Figure 7 It is a cross-sectional view showing the method for manufacturing a semiconductor device according to an embodiment (the sixth).

[0019] Figure 8 This is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment (part seven).

[0020] Fig. 9 It is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment (the eighth one).

[0021] Fig.10 It is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment (part 9).

[0022] Fig.11 This is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment (part 10).

[0023] Fig.12 11 is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment.

[0024] Fig.13 12 is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment.

[0025] Fig.14 13 is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment.

[0026] Fig.15 2 is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment (fourteen).

[0027] Fig.16 is a cross-sectional view showing a semiconductor device according to a modification of the embodiment.

[0028] Description of Reference Numerals

[0029] 1, 2: semiconductor devices;

[0030] 10: Growth substrate;

[0031] 20: nitride semiconductor layer;

[0032] 21: buffer layer;

[0033] 22: barrier layer;

[0034] 23: spacer layer;

[0035] 24: channel layer;

[0036] 24A: upper surface;

[0037] 25: cap layer;

[0038] 25G, 40D, 40S: concave part;

[0039] 26: channel area;

[0040] 31: a first dielectric film;

[0041] 31D, 31G, 31S, 32D, 32G, 32S, 51D, 51S, 52D, 52G, 52S: opening;

[0042] 32: Insulation film;

[0043] 41D, 41S: regrowth layer;

[0044] 41X: Layer;

[0045] 42D: drain electrode;

[0046] 42S: source electrode;

[0047] 43: gate electrode;

[0048] 51: second dielectric film;

[0049] 52: passivation film;

[0050] 59: Laminated film. DETAILED DESCRIPTION

[0051] [Description of Embodiments of the Present Disclosure]

[0052] First, embodiments of the present disclosure will be described by way of examples.

[0053] [1] A method for manufacturing a semiconductor device according to one embodiment of the present disclosure comprises the following steps: forming a first nitride semiconductor layer having a nitrogen polarity on its upper surface; forming a first dielectric film on the first nitride semiconductor layer; forming a first opening in the first dielectric film to expose a portion of the first nitride semiconductor layer; forming a second nitride semiconductor layer on the inner side of the first opening and on the first nitride semiconductor layer; after the step of forming the second nitride semiconductor layer, forming a second opening in the first dielectric film to expose a portion of the first nitride semiconductor layer; forming a second dielectric film on the inner side of the second opening and on the first nitride semiconductor layer; forming an ohmic electrode in ohmic contact with the second nitride semiconductor layer; and forming a gate electrode above the second opening and on the second dielectric film.

[0054] After forming the first opening and the second nitride semiconductor layer, the second dielectric film is formed, so the second dielectric film does not need to be etched when the first opening is formed. Depending on the materials of the first dielectric film and the second dielectric film, the etching selectivity between the first dielectric film and the second dielectric film may be small, but even when the etching selectivity is small, the first opening can be easily formed. Therefore, the semiconductor device can be easily manufactured.

[0055] [2] In [1], the step of forming the second dielectric film may include the steps of: forming a plurality of insulating films on the first nitride semiconductor layer; and performing a heat treatment on the plurality of insulating films to form a composite insulating film. In this case, it is easy to obtain a high relative dielectric constant in the second dielectric film.

[0056] [3] In [2], the plurality of insulating films may include: a first oxide film including at least one selected from the group consisting of hafnium, lanthanum, and zirconium; and a second oxide film including at least one selected from the group consisting of silicon and aluminum. In this case, it is easier to obtain a high relative dielectric constant in the second dielectric film.

[0057] [4] In [2] or [3], the step of forming the second dielectric film may include the step of nitriding the composite insulating film after the step of performing the heat treatment. In this case, it is easier to obtain a particularly high relative dielectric constant in the second dielectric film.

[0058] [5] In any one of [1] to [4], the step of reducing the portion of the first nitride semiconductor layer exposed from the second opening using pyrolyzed ammonia may be included between the step of forming the second opening and the step of forming the second dielectric film. In this case, even if the first nitride semiconductor layer is damaged when the second opening is formed, the damaged portion can be removed, thereby suppressing changes in characteristics associated with the damage.

[0059] [6] In [1], the second dielectric film may include at least one selected from the group consisting of a silicon nitride film, an aluminum oxide film, and a silicon oxynitride film. In this case, it is also easy to obtain a high relative dielectric constant in the second dielectric film.

[0060] [7] In any one of [1] to [6], the first dielectric film may be formed by a thermal film forming method using a nitrogen-containing raw material. In this case, nitrogen atoms can be supplied to the upper surface of the first nitride semiconductor layer when the first dielectric film is formed, thereby modifying the upper surface.

[0061] [8] A semiconductor device according to another embodiment of the present disclosure comprises: a first nitride semiconductor layer, the upper surface of which has nitrogen polarity; a first dielectric film on the first nitride semiconductor layer; a first opening and a second opening formed in the first dielectric film to expose a portion of the first nitride semiconductor layer; a second nitride semiconductor layer on the inner side of the first opening and on the first nitride semiconductor layer; a second dielectric film on the inner side of the second opening and on the first nitride semiconductor layer; an ohmic electrode in ohmic contact with the second nitride semiconductor layer; and a gate electrode above the second opening and on the second dielectric film.

[0062] In order to obtain this structure, the second dielectric film may be formed after forming the first opening and the second nitride semiconductor layer. Therefore, as described above, the semiconductor device can be easily manufactured.

[0063] [9] In [8], the resistivity of the second dielectric film may be higher than the resistivity of the first dielectric film. In this case, the first dielectric film can suppress current collapse, and the second dielectric film can suppress gate leakage.

[0064]

[10] In [8] or [9], the relative dielectric constant of the second dielectric film may be higher than the relative dielectric constant of the first dielectric film. In this case, the current collapse can be suppressed by the first dielectric film, and the gate leakage can be suppressed by the second dielectric film.

[0065]

[11] A method for manufacturing a semiconductor device according to another embodiment of the present invention comprises the following steps: forming a first nitride semiconductor layer having a nitrogen polarity on its upper surface; forming a first dielectric film on top of the first nitride semiconductor layer; forming a gate opening in the first dielectric film to expose a portion of the first nitride semiconductor layer; reducing the portion of the first nitride semiconductor layer exposed from the gate opening using pyrolyzed ammonia; and forming a second dielectric film on the inner side of the gate opening and on top of the first nitride semiconductor layer.

[0066] [Details of the embodiments of the present disclosure]

[0067] The following describes the embodiments of the present disclosure in detail, but the present disclosure is not limited to these contents. It should be noted that in this specification and the drawings, for components having substantially the same functional configuration, repeated descriptions are sometimes omitted by marking the same figure numbers. In the present disclosure, "looking down" refers to observing an object from above.

[0068] The embodiment relates to a semiconductor device including a GaN-based high electron mobility transistor (HEMT). Figure 1 is a cross-sectional view showing a semiconductor device according to an embodiment.

[0069] like Figure 1 As shown, the semiconductor device 1 of the embodiment mainly includes a growth substrate 10, a nitride semiconductor layer 20, a first dielectric film 31, an insulating film 32, a second dielectric film 51, a passivation film 52, a regrown layer 41S, a regrown layer 41D, a gate electrode 43, a source electrode 42S and a drain electrode 42D.

[0070] The growth substrate 10 is, for example, a semi-insulating silicon carbide (SiC) substrate. When the growth substrate 10 is a SiC substrate, the upper surface of the growth substrate 10 is a carbon (C) polar surface. When the surface of the growth substrate 10 is a C polar surface, the nitride semiconductor layer 20 can grow crystals with the nitrogen (N) polar surface as the growth surface.

[0071] The nitride semiconductor layer 20 includes a buffer layer 21, a barrier layer 22, a spacer layer 23, a channel layer 24, and a cap layer 25. The nitride semiconductor layer 20 may include a nucleation layer between the growth substrate 10 and the buffer layer 21. The nitride semiconductor layer 20 is an example of a first nitride semiconductor layer.

[0072] The buffer layer 21 is located on the growth substrate 10. The buffer layer 21 is, for example, an aluminum nitride (AlN) layer. The thickness of the AlN layer is, for example, not less than 1 nm and not more than 2000 nm. The buffer layer 21 may also include an AlN layer and a GaN layer or an aluminum gallium nitride (AlGaN) layer on the AlN layer.

[0073] The barrier layer 22 is located on the buffer layer 21. The barrier layer 22 is, for example, an AlGaN layer. The band gap of the barrier layer 22 is greater than the band gap of the channel layer 24. The thickness of the barrier layer 22 is, for example, greater than 1 nm and less than 50 nm. The composition of the barrier layer 22 is, for example, Al Y Ga 1－Y N (0.15≤Y≤0.55). The conductivity type of the barrier layer 22 is, for example, n-type or non-doped (i-type). A scandium aluminum nitride (ScAlN) layer, an indium aluminum nitride (InAlN) layer, or an indium aluminum gallium nitride (InAlGaN) layer may be used instead of the AlGaN layer.

[0074] The spacer layer 23 is located on the barrier layer 22. The spacer layer 23 is, for example, an AlN layer. The thickness of the spacer layer 23 is, for example, in the range of 0.2 nm to 5 nm.

[0075] The channel layer 24 is located on the spacer layer 23. The channel layer 24 is, for example, a GaN layer. The band gap of the channel layer 24 is smaller than the band gap of the barrier layer 22. The thickness of the channel layer 24 is, for example, greater than 1 nm and less than 50 nm. Between the channel layer 24 and the barrier layer 22 and the spacer layer 23, strain is generated due to the difference in their lattice constants, and the strain causes piezoelectric charge at the interface between the two. As a result, a two-dimensional electron gas (two dimensional electron gas: 2DEG) is generated near the surface of the channel layer 24 that is opposite to the barrier layer 22, and a channel region 26 is formed. The conductivity type of the channel layer 24 is, for example, n-type or non-doped (i-type).

[0076] The cap layer 25 is located on the channel layer 24. The cap layer 25 is, for example, an AlGaN layer. The thickness of the cap layer 25 is, for example, not less than 0.2 nm and not more than 10 nm.

[0077] On the C-polarity surface of the SiC substrate, the buffer layer 21, the barrier layer 22, the spacer layer 23, the channel layer 24, and the cap layer 25 grow crystals with the N-polarity surface as the growth surface. Therefore, the upper surfaces of the buffer layer 21, the barrier layer 22, the spacer layer 23, the channel layer 24, and the cap layer 25 have N-polarity, and the lower surfaces have gallium (Ga) polarity.

[0078] A recess 40S for the source and a recess 40D for the drain are formed in the nitride semiconductor layer 20. The bottom of the recess 40S and the bottom of the recess 40D are closer to the lower surface of the nitride semiconductor layer 20 than the upper surface 24A of the channel layer 24. That is, the recess 40S and the recess 40D are formed deeper than the upper surface 24A of the channel layer 24. The bottom of the recess 40S and the bottom of the recess 40D may be located in the channel layer 24, in the spacer layer 23, or in the barrier layer 22.

[0079] In addition, a recess 25G is formed in the cap layer 25. When viewed from above, the recess 25G is located between the recess 40S and the recess 40D. The thickness of the portion of the cap layer 25 remaining at the bottom of the recess 25G is, for example, greater than 1 nm and less than 5 nm. That is, the distance between the lower surface of the cap layer 25 and the bottom surface of the recess 25G is, for example, greater than 1 nm and less than 5 nm. It should be noted that, for example, when the thickness of the cap layer 25 is less than 5 nm, the recess 25G may not be formed.

[0080] The first dielectric film 31 is located on the nitride semiconductor layer 20. The first dielectric film 31 is in contact with the upper surface of the cap layer 25. For example, the relative dielectric constant of the first dielectric film 31 is higher than the relative dielectric constant of silicon dioxide (SiO2). The first dielectric film 31 may also be a high dielectric constant film. The first dielectric film 31 is, for example, a silicon nitride (SiN) film. The thickness of the first dielectric film 31 is, for example, greater than 2 nm and less than 100 nm. An opening 31S for the source, an opening 31D for the drain, and an opening 31G for the gate are formed in the first dielectric film 31. The opening 31S is connected to the recess 40S, the opening 31D is connected to the recess 40D, and the opening 31G is connected to the recess 25G. The opening 31S and the opening 31D are examples of the first opening. The first opening may also be referred to as a drain-source opening. The opening 31G is an example of the second opening. The second opening may also be referred to as a gate opening.

[0081] The regrown layer 41S is located on the channel layer 24, the spacer layer 23 or the barrier layer 22 in the recess 40S. The regrown layer 41D is located on the channel layer 24, the spacer layer 23 or the barrier layer 22 in the recess 40D. The regrown layer 41S and the regrown layer 41D are, for example, n-type GaN layers. The regrown layer 41S and the regrown layer 41D contain germanium (Ge) or Si as n-type impurities. The resistance of the regrown layer 41S and the regrown layer 41D is lower than the resistance of the channel layer 24. For example, the regrown layer 41S and the regrown layer 41D are formed by regrowing the n-type GaN layer after the recess 40S and the recess 40D are formed in the nitride semiconductor layer 20. The regrown layer 41S and the regrown layer 41D are an example of a second nitride semiconductor layer.

[0082] The insulating film 32 is located on the regrown layer 41S and the regrown layer 41D. The insulating film 32 is, for example, a SiN film. The insulating film 32 is formed with an opening 32S for the source, an opening 32D for the drain, and an opening 32G. A portion of the regrown layer 41S is exposed from the opening 32S, a portion of the regrown layer 41D is exposed from the opening 32D, and the first dielectric film 31 is exposed from the opening 32G. The entire first dielectric film 31 does not need to be exposed from the opening 32G, and a portion of the insulating film 32 may be located on the first dielectric film 31.

[0083] The second dielectric film 51 is located on the cap layer 25, the first dielectric film 31 and the insulating film 32. The second dielectric film 51 is located on the cap layer 25 inside the opening 31G. For example, the relative dielectric constant of the second dielectric film 51 is higher than the relative dielectric constant of SiO2. The second dielectric film 51 may also be a high dielectric constant film. The second dielectric film 51 is, for example, a dielectric oxide film or a dielectric nitride oxide film. The dielectric oxide film or the dielectric nitride oxide film may include at least one selected from the group consisting of hafnium (Hf), lanthanum (La) and zirconium (Zr). In addition, the dielectric oxide film or the dielectric nitride oxide film may also include at least one selected from the group consisting of silicon (Si) and aluminum (Al). For example, the second dielectric film 51 may also be a hafnium silicate (HfSiOx) film or a hafnium aluminate (HfAlOx) film. It should be noted that the second dielectric film 51 may also be an insulating dielectric film other than the dielectric oxide film and the dielectric nitride oxide film. The thickness of the second dielectric film 51 is, for example, not less than 1 nm and not more than 30 nm. An opening 51S for the source and an opening 51D for the drain are formed in the second dielectric film 51. The opening 51S is connected to the opening 32S, and the opening 51D is connected to the opening 32D.

[0084] The source electrode 42S is located on the regrown layer 41S in the opening 32S and the opening 51S, and the drain electrode 42D is located on the regrown layer 41D in the opening 32D and the opening 51D. The source electrode 42S is in contact with the regrown layer 41S, and the drain electrode 42D is in contact with the regrown layer 41D. The source electrode 42S is in ohmic contact with the regrown layer 41S, and the drain electrode 42D is in ohmic contact with the regrown layer 41D. The source electrode 42S and the drain electrode 42D are examples of ohmic electrodes.

[0085] The passivation film 52 covers the second dielectric film 51, the source electrode 42S, and the drain electrode 42D. The thickness of the passivation film 52 is, for example, 5 nm or more and 100 nm or less in the portion where the thickness is uniform on the second dielectric film 51. The passivation film 52 is formed with an opening 52S for the source electrode, an opening 52D for the drain electrode, and an opening 52G for the gate electrode. A portion of the source electrode 42S is exposed from the opening 52S, and a portion of the drain electrode 42D is exposed from the opening 52D. When viewed from above, the opening 52G is located inside the opening 31G.

[0086] The gate electrode 43 is located between the source electrode 42S and the drain electrode 42D in a plan view. The gate electrode 43 is located on the passivation film 52 and the second dielectric film 51 and is in contact with the second dielectric film 51 via the opening 52G.

[0087] Next, a method for manufacturing the semiconductor device 1 according to the embodiment will be described. Figures 2 to 15 It is a cross-sectional view showing a method for manufacturing the semiconductor device 1 according to the embodiment.

[0088] First, if Figure 2 As shown, a nitride semiconductor layer 20 is formed on a growth substrate 10 by metal organic chemical vapor deposition (MOCVD) method, for example. In the formation of the nitride semiconductor layer 20, a buffer layer 21, a barrier layer 22, a spacer layer 23, a channel layer 24 and a cap layer 25 are sequentially formed.

[0089] Then, if Figure 3 As shown, a first dielectric film 31 is formed on the nitride semiconductor layer 20. The first dielectric film 31 is formed by a thermal film forming method such as a thermal CVD method using a low pressure chemical vapor deposition (LPCVD) device. When a SiN film is formed as the first dielectric film 31, silane (SiH4) and ammonia (NH3) are used as raw materials, for example.

[0090] Then, if Figure 4 As shown, an opening 31S for the source and an opening 31D for the drain are formed in the first dielectric film 31, and a recess 40S for the source and a recess 40D for the drain are formed in the nitride semiconductor layer 20. The bottom of the recess 40S and the bottom of the recess 40D may be closer to the lower surface of the nitride semiconductor layer 20 than the upper surface 24A of the channel layer 24. That is, the recess 40S and the recess 40D may be formed deeper than the upper surface 24A of the channel layer 24. The bottom of the recess 40S and the bottom of the recess 40D may be located in the channel layer 24, in the spacer layer 23, or in the barrier layer 22.

[0091] The opening 31S, the opening 31D, the recess 40S, and the recess 40D can be formed, for example, by reactive ion etching (RIE) using a mask (not shown). For example, in the formation of the opening 31S and the opening 31D, a fluorine (F)-based gas is used as a reactive gas, and in the formation of the recess 40S and the recess 40D, a chlorine (Cl)-based gas is used as a reactive gas. In the RIE using the F-based gas, a large etching selectivity can be obtained between the first dielectric film 31 and the nitride semiconductor layer 20. Therefore, etching residues are not easily generated when the opening 31S and the opening 31D are formed.

[0092] Then, if Figure 5 As shown, a regrown layer 41S is formed in the recess 40S and on the channel layer 24, the spacer layer 23 or the barrier layer 22, and a regrown layer 41D is formed in the recess 40D and on the channel layer 24, the spacer layer 23 or the barrier layer 22. The regrown layer 41S and the regrown layer 41D can be formed by a physical vapor deposition (PVD) method such as an evaporation method, a sputtering method, or a molecular beam epitaxy (MBE) method. When forming the regrown layer 41S and the regrown layer 41D, a layer 41X made of the same material as the regrown layer 41S and the regrown layer 41D is formed on the first dielectric film 31. Unlike the regrown layer 41S and the regrown layer 41D, the layer 41X is not epitaxially grown on the first dielectric film 31.

[0093] Then, if Figure 6 As shown in FIG. 1 , an insulating film 32 is formed on the regrown layer 41S, the regrown layer 41D, and the layer 41X. The insulating film 32 is formed by, for example, a plasma CVD method.

[0094] Then, if Figure 7 As shown, an opening 32G is formed in the insulating film 32. The opening 32G can be formed, for example, by RIE using a mask (not shown). For example, F-based gas is used as a reactive gas in forming the opening 32G.

[0095] Then, if Figure 8 As shown, the layer 41X is removed. The layer 41X can be removed using tetramethylammonium hydroxide (TMAH), for example. Alkaline solutions such as sodium hydroxide (NaOH) and ammonium chloride (NH4Cl) can also be used to remove the layer 41X.

[0096] Then, if Fig. 9As shown, an opening 31G is formed in the first dielectric film 31. The opening 31G can be formed, for example, by RIE using a mask (not shown). For example, F-based gas is used as a reactive gas in forming the opening 31G.

[0097] Next, the portion of the cap layer 25 exposed from the opening 31G is reduced using pyrolyzed NH 3. For example, in order to pyrolyze NH 3, the temperature of the chamber may be set to a range of 700 degrees Celsius (° C.) or more and 900 degrees Celsius (° C.) or less. As a result, Fig.10 As shown, the surface portion of the cap layer 25 exposed from the opening 31G is removed to form the recessed portion 25G. Even if the surface portion of the cap layer 25 is damaged when the opening 31G is formed, the damaged portion can be removed by the reduction treatment. For example, after the damaged portion is removed, the new surface of the cap layer 25 has an arithmetic mean roughness Ra in the range of 0.4 nm to 1 nm.

[0098] Then, if Fig.11 As shown, a stacked film 59 having a plurality of insulating films is formed. The plurality of insulating films include, for example, a first oxide film including at least one selected from the group consisting of hafnium, lanthanum, and zirconium; and a second oxide film including at least one selected from the group consisting of silicon and aluminum. The stacked film 59 may also be a multilayer film in which the first oxide film and the second oxide film are alternately stacked. The first oxide film and the second oxide film are formed, for example, by an atomic layer deposition (ALD) method.

[0099] Then, if Fig.12 As shown, the stacked film 59 having a plurality of insulating films is subjected to heat treatment to form a composite insulating film as the second dielectric film 51. When the first insulating film is a hafnium oxide (HfOx) film and the second insulating film is a silicon oxide (SiOx) film, a HfSiOx film is formed as the second dielectric film 51. The temperature of the heat treatment is set to about 700°C, for example.

[0100] Then, if Fig.13As shown, an opening 51S for the source and an opening 51D for the drain are formed in the second dielectric film 51, and an opening 32S for the source and an opening 32D for the drain are formed in the insulating film 32. The opening 51S, the opening 51D, the opening 32S, and the opening 32D can be formed, for example, by RIE using a mask (not shown). For example, in the formation of the opening 51S and the opening 51D, a Cl-based gas is used as a reactive gas. In the formation of the opening 32S and the opening 32D, a F-based gas is used as a reactive gas. In the RIE using the Cl-based gas, a large etching selectivity can be obtained between the second dielectric film 51 and the insulating film 32. Therefore, etching residues are not easily generated when the opening 51S and the opening 51D are formed. In the RIE using the F-based gas, a large etching selectivity can be obtained between the insulating film 32 and the regrown layer 41S and the regrown layer 41D. Therefore, etching residues are not easily generated when the opening 32S and the opening 32D are formed. The insulating film 32 functions as an etching stopper when the opening 51S and the opening 51D are formed.

[0101] Then, if Fig.14 As shown, the source electrode 42S is formed in the opening 32S and the opening 51S and on the regrown layer 41S, and the drain electrode 42D is formed in the opening 32D and the opening 51D and on the regrown layer 41D. In forming the source electrode 42S and the drain electrode 42D, first, a metal layer (not shown) constituting the source electrode 42S and the drain electrode 42D is formed. When forming the metal layer, for example, a growth mask (not shown) having an opening formed in a region where the metal layer is to be formed is used to form a film, and then the growth mask is removed together with the metal layer (not shown) formed thereon. That is, lift-off is performed.

[0102] Then, if Fig.15 As shown in FIG. 1 , a passivation film 52 is formed on the second dielectric film 51 , the source electrode 42S, and the drain electrode 42D. The passivation film 52 covers the second dielectric film 51 , the source electrode 42S, and the drain electrode 42D.

[0103] Next, an opening 52G for a gate is formed in the passivation film 52 (see Figure 1 ). The opening 52G can be formed by, for example, RIE using a mask (not shown).

[0104] Next, the gate electrode 43 is formed on the passivation film 52 and the second dielectric film 51 so as to be in contact with the second dielectric film 51 through the opening 52G (see Figure 1). When forming the gate electrode 43, for example, a metal layer is formed using a growth mask (not shown) having an opening in a region where the gate electrode 43 is to be formed, and then the growth mask is removed together with the metal layer (not shown) formed thereon. That is, lift-off is performed.

[0105] Next, an opening 52S for the source and an opening 52D for the drain are formed in the passivation film 52 (see Figure 1 ). The opening 52S and the opening 52D can be formed by, for example, RIE using a mask (not shown).

[0106] In this way, the semiconductor device 1 can be manufactured.

[0107] In the semiconductor device 1 of the embodiment, the upper surfaces of the barrier layer 22 and the channel layer 24 have N polarity, thereby facilitating shortening the distance between the channel region 26 and the source electrode 42S and the drain electrode 42D, and facilitating lowering of resistance.

[0108] In addition, after the openings 31S and 31D for forming the regrown layers 41S and 41D are formed, the second dielectric film 51 that functions as a gate insulating film is formed, so that the second dielectric film 51 can be formed without etching the openings 31S and 31D. Depending on the materials of the first dielectric film 31 and the second dielectric film 51, the etching selectivity between the first dielectric film 31 and the second dielectric film 51 is small, but even in the case of a small etching selectivity, the openings 31S and 31D can be easily formed with high precision. Therefore, the increase in contact resistance associated with etching residues can be easily suppressed. In this way, according to this embodiment, the semiconductor device 1 can be easily manufactured.

[0109] When forming the recessed portions 40S and 40D, when forming the openings 51S and 51D, and when forming the openings 32S and 32D, etching residues are unlikely to be generated. Therefore, etching can be easily controlled even in these steps.

[0110] A composite insulating film such as a HfSiOx film is formed when forming the second dielectric film 51, thereby making it easier to obtain a high relative dielectric constant in the gate insulating film. The stacked film 59 includes: a first oxide film including at least one selected from the group consisting of Hf, La, and Zr; and a second oxide film including at least one selected from the group consisting of Si and Al, thereby making it easier to obtain a high relative dielectric constant in the gate insulating film.

[0111] Furthermore, after the opening 31G is formed, the portion of the cap layer 25 exposed from the opening 31G is reduced using pyrolyzed NH3 to form a recess 25G, thereby removing the damaged portion of the cap layer 25. The damaged portion itself may cause changes in the characteristics of the semiconductor device 1. In addition, during the heat treatment for forming the composite insulating film, atoms may diffuse from the damaged portion to the stacked film 59, causing the cap layer 25 to become too thin or an opening to be formed in the cap layer 25. In these cases, the threshold may change, or the pinch-off characteristic may deteriorate, or the gate leakage may increase. In contrast, the damaged portion is removed by a reduction treatment, thereby easily suppressing the diffusion of atoms constituting the cap layer 25. In addition, the surface of the cap layer 25 is modified by the N atoms contained in NH3. It should be noted that the reduction of the portion of the cap layer 25 exposed from the opening 31G may not be necessary.

[0112] The first dielectric film 31 is formed by a thermal film forming method using a raw material containing nitrogen. Thus, N atoms are supplied to the upper surface of the cap layer 25 during the formation of the first dielectric film 31 , thereby modifying the upper surface of the cap layer 25 .

[0113] The cap layer 25 is not limited to an AlGaN layer, and may also be an aluminum nitride (AlN) layer. When the cap layer 25 is an AlN layer, damage is not easily generated in the cap layer 25, and the recess 25G formed by the reduction treatment is easy to become shallow. When the cap layer 25 is an AlN layer, the thickness of the cap layer 25 may be greater than 0.2 nm and less than 2.0 nm.

[0114] The second dielectric film 51 does not need to include a composite insulating film including at least one selected from the group consisting of hafnium, lanthanum, and zirconium, and may include at least one selected from the group consisting of a SiN film, an aluminum oxide (Al2O3) film, and a silicon oxynitride (SiON) film. By having the second dielectric film 51 include at least one selected from the group consisting of a SiN film, an Al2O3 film, and a SiON film, a high relative dielectric constant can be obtained in the second dielectric film 51. The second dielectric film 51 may be formed in the same chamber as the chamber used for reducing the portion of the cap layer 25 exposed from the opening 31G without being exposed to the atmosphere, or may be formed in a chamber different from the chamber used for reducing the portion of the cap layer 25 exposed from the opening 31G. For example, the SiN film and the SiON film may be formed by a plasma CVD method, and the Al2O3 film may be formed by an ALD method. In the case where the second dielectric film 51 does not include a composite insulating film, the formation and heat treatment of the stacked film 59 are not required, and the second dielectric film 51 may be formed instead of the stacked film 59.

[0115] Even when both the first dielectric film 31 and the second dielectric film 51 are SiN films, the film quality is different between the first dielectric film 31 formed by the thermal film forming method and the second dielectric film 51 formed by the plasma CVD method. For example, the concentration of hydrogen (H) atoms in the first dielectric film 31 may be higher than the concentration of H atoms in the second dielectric film 51, and the resistivity of the second dielectric film 51 may be higher than the resistivity of the first dielectric film 31. Since the resistivity of the second dielectric film 51 is higher than the resistivity of the first dielectric film 31, the electron trap can be suppressed by the first dielectric film 31 to suppress the current collapse, and the gate leakage can be suppressed by the second dielectric film 51.

[0116] It should be noted that, regardless of the material, the resistivity of the second dielectric film 51 may be higher than the resistivity of the first dielectric film 31, and the relative dielectric constant of the second dielectric film 51 may be higher than the relative dielectric constant of the first dielectric film 31. In any case, the current collapse can be suppressed by the first dielectric film 31, and the gate leakage can be suppressed by the second dielectric film 51.

[0117] Next, modifications of the embodiment will be described. Fig.16 is a cross-sectional view showing a semiconductor device according to a modification of the embodiment.

[0118] The semiconductor device 2 of the modified example does not include the passivation film 52, and the gate electrode 43 is formed on the second dielectric film 51. The other configurations of the semiconductor device 2 are the same as those of the semiconductor device 1. The semiconductor device 2 can also achieve the same effects as those of the semiconductor device 1.

[0119] As mentioned above, although embodiment is described in detail, this disclosure is not limited to a specific embodiment, Various deformation|transformation and change are possible within the range described in a claim.

Claims

1. A method for manufacturing a semiconductor device, comprising the following steps: forming a first nitride semiconductor layer having a nitrogen polarity on its upper surface; forming a first dielectric film on the first nitride semiconductor layer; forming a first opening in the first dielectric film to expose a portion of the first nitride semiconductor layer; forming a second nitride semiconductor layer inside the first opening and on the first nitride semiconductor layer; After the step of forming the second nitride semiconductor layer, forming a second opening in the first dielectric film to expose a portion of the first nitride semiconductor layer; forming a second dielectric film inside the second opening and on the first nitride semiconductor layer; forming an ohmic electrode in ohmic contact with the second nitride semiconductor layer; as well as A gate electrode is formed above the second opening and on the second dielectric film.

2. The method for manufacturing a semiconductor device according to claim 1, wherein: The step of forming the second dielectric film includes the following steps: forming a plurality of insulating films on the first nitride semiconductor layer; and The plurality of insulating films are heat-treated to form a composite insulating film.

3. The method for manufacturing a semiconductor device according to claim 2, wherein: The plurality of insulating films include: The first oxide film includes at least one selected from the group consisting of hafnium, lanthanum, and zirconium; as well as The second oxide film includes at least one selected from the group consisting of silicon and aluminum.

4. The method for manufacturing a semiconductor device according to claim 2 or 3, wherein: The step of forming the second dielectric film includes the following steps: After the heat treatment step, the composite insulating film is nitrided.

5. The method for manufacturing a semiconductor device according to any one of claims 1 to 3, wherein: The following step is included between the step of forming the second opening and the step of forming the second dielectric film: The portion of the first nitride semiconductor layer exposed from the second opening is reduced using pyrolyzed ammonia.

6. The method for manufacturing a semiconductor device according to claim 1, wherein: The second dielectric film includes at least one selected from the group consisting of a silicon nitride film, an aluminum oxide film, and a silicon nitride oxide film.

7. The method for manufacturing a semiconductor device according to any one of claims 1 to 3, wherein: The first dielectric film is formed by a thermal film forming method using a raw material containing nitrogen.

8. A semiconductor device comprising: a first nitride semiconductor layer, wherein an upper surface of the first nitride semiconductor layer has nitrogen polarity; a first dielectric film on the first nitride semiconductor layer; A first opening and a second opening are formed in the first dielectric film to expose a portion of the first nitride semiconductor layer; a second nitride semiconductor layer inside the first opening and above the first nitride semiconductor layer; a second dielectric film inside the second opening and on the first nitride semiconductor layer; an ohmic electrode in ohmic contact with the second nitride semiconductor layer; as well as A gate electrode is located above the second opening and on the second dielectric film.

9. The semiconductor device according to claim 8, wherein: The resistivity of the second dielectric film is higher than the resistivity of the first dielectric film.

10. The semiconductor device according to claim 8 or 9, wherein: A relative dielectric constant of the second dielectric film is higher than a relative dielectric constant of the first dielectric film.

11. A method for manufacturing a semiconductor device, comprising the following steps: forming a first nitride semiconductor layer having a nitrogen polarity on its upper surface; forming a first dielectric film on the first nitride semiconductor layer; forming a gate opening in the first dielectric film to expose a portion of the first nitride semiconductor layer; reducing a portion of the first nitride semiconductor layer exposed from the gate opening using pyrolyzed ammonia; as well as A second dielectric film is formed inside the gate opening and on the first nitride semiconductor layer.

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