Deep buried junction SiC field effect transistor and preparation method thereof
By forming a deeply buried P-shield region in the SiC MOSFET and performing grounding treatment, the problem of easy breakdown of the corner gate oxide layer at the bottom of the trench in the SiC MOSFET is solved, and the long-term stability of the device and the protection ability of the P-shield region are improved.
Patent Information
- Application Number
- CN202411544386.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-31
- Publication Date
- 2025-03-04
AI Technical Summary
The gate oxide layer at the bottom corner of the trench gate in the SiC MOSFET is prone to premature breakdown failure, affecting long-term stable use.
By forming a deeply buried P-shield region in the SiC MOSFET, the P-shield region is set at the bottom deeper than the groove region, and etching the groove holes above the P-shield region and preparing ohmic contacts are made to achieve grounding processing of the P-shield region.
It effectively protects the gate oxide layer at the corner of the bottom of the trench, improves the reliability of the long-term stable use of the device, and further enhances the protection capability of the P-shield region.
Smart Images
Figure CN119562549A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor technology, and in particular to a deep buried junction SiC field effect transistor and a preparation method thereof. Background Art
[0002] At present, in the field of power electronics technology, in order to achieve higher power and better efficiency to adapt to the rapidly developing social environment, the third generation of wide bandgap semiconductor materials represented by SiC has emerged. Compared with traditional Si materials, SiC materials have many physical performance advantages, such as large bandgap width, high critical breakdown electric field, small intrinsic carrier concentration, fast saturation drift velocity, high melting point, high thermal conductivity, etc. These factors make SiC power devices have huge advantages in high voltage, high temperature, high frequency, high radiation and other application fields. Among SiC power devices, SiC MOSFET is the core product. It fully combines the excellent conduction characteristics and switching characteristics of both Si MOSFET and Si IGBT, and has been favored by the market and has begun to be used on a large scale.
[0003] SiC MOSFET is mainly divided into two types: planar gate structure and trench gate structure. Among them, planar gate structure is mainly based on planar structure due to its simple processing technology and high structural stability. However, in terms of chip area and cost, trench structure is still more advantageous, and trench structure has been identified as the future technical development direction by major manufacturers. However, currently only ROHM and Infineon's trench gate SiC MOSFET are used in batches on the market. The reason is that due to the electric field concentration phenomenon at the bottom corner of the trench inside the trench structure and the interface state problem of the gate oxide layer in SiC, the gate oxide layer at the bottom corner of the trench of the trench gate SiC MOSFET is very prone to premature breakdown failure, affecting long-term stable use. Summary of the invention
[0004] In view of the above problems, the present invention provides a deep buried junction SiC field effect transistor and a preparation method thereof, which can realize the protection of the gate oxide layer at the corner of the trench bottom and the grounding of the P-shield area to further improve the protection capability of the P-shield area.
[0005] The technical solution of the present invention is: A method for preparing a deep buried junction SiC field effect transistor comprises the following steps: S100, forming a SiC Drift layer on the top surface of the SiC Sub layer, and ion implanting on the top surface of the SiC Drift layer to form a P-shield region arranged at intervals; S200, forming a SiC Epi layer, a P-body region and a NP region in sequence on the top surface of the SiC Drift layer; S300, forming a plurality of first trench regions and a plurality of second trench regions on the top surface of the NP region by etching in sequence; the second trench regions are etched to the top surface of the P-shield region; and the second trench regions are etched to the SiC Epi layer; S400, forming a gate oxide layer and a Poly layer in sequence in the second trench region; S500, forming an isolation dielectric layer by deposition on the top surface of the second trench region and on the sidewalls of the first trench region; S600, forming an ohmic contact alloy layer on the top surface of the NP region and the P-shield region by thermal annealing after Ni metal deposition; S700, forming a front electrode metal layer on the top of the device by sputtering Ti and AlCu metals.
[0006] Specifically, in step S100, the thickness of the SiC Drift layer is 3um-10um, and the doping concentration is 1E15-5E16cm -2 .
[0007] Specifically, in step S100, the depth of the bottom surface of the P-shield region from the top surface of the SiC Drift layer is 0.3um-1um, and the doping concentration is 1E18-1E19cm -2 .
[0008] Specifically, the thickness of the SiC Epi layer in step S200 is 5um-15um, and the doping concentration is 1E15-1E17cm -2 .
[0009] Specifically, in step S200, the depth of the bottom surface of the P-body region from the top surface of the SiC Epi layer is 0.4um-1um, and the doping concentration is 1E17-3E18cm -2 .
[0010] Specifically, in step S200, the depth from the bottom surface of the NP region to the top surface of the SiC Epi layer is 0.2um-0.7um, and the doping concentration is 1E18-1E19cm -2 .
[0011] Specifically, in step S300 , the depth between the bottom surface of the second trench region and the top surface of the SiC Epi layer is 0.6 um-1.5 um.
[0012] A deep buried junction SiC field effect transistor, comprising a SiC Sub layer, a SiC Drift layer, a SiCEpi layer, a P-body region, an NP region, an ohmic contact alloy layer and a front electrode metal layer arranged in sequence from bottom to top; The top surface of the SiC Drift layer is provided with a plurality of P-shield regions extending downward at intervals; The top surface of the NP region is provided with a plurality of first groove regions etched downward to the top surface of the P-shield region and a plurality of second groove regions etched downward to the SiC Epi layer; a gap is provided between the bottom surface of the second groove region and the bottom surface of the SiC Epi layer; A gate oxide layer is provided in the second trench region; a Poly layer is provided on the gate oxide layer; The top surface of the NP region and the sidewall of the first trench region are respectively provided with an isolation dielectric layer; the bottom surface of the isolation dielectric layer on the NP region is respectively connected to the NP region, the second trench region and the Poly layer; The bottom of the ohmic contact alloy layer extends into the first trench region and is connected to the P-shield region, and the top is located at the side of the isolation dielectric layer.
[0013] Specifically, the bottom of the front electrode metal layer is connected to the ohmic contact alloy layer and the isolation dielectric layer respectively.
[0014] The present invention forms a P-shield region with a deep buried junction in a trench gate SiC MOSFET device, and sets the P-shield region at a bottom deeper than the trench region, so that during the use of the device, the depletion layer formed by the P-shield region with a deep buried junction and the SiCDrift layer and the Epi layer is extended to the bottom corner of the trench, thereby protecting the gate oxide layer at the bottom corner of the trench and improving the long-term stable use reliability of the device. At the same time, by etching a trench opening above the P-shield region and preparing an ohmic contact, the P-shield region is grounded, further improving the protection capability of the P-shield region. BRIEF DESCRIPTION OF THE DRAWINGS
[0015] Figure 1 Schematic diagram of the structure of the trench gate SiC MOSFET of the present invention; Figure 2 is a structural schematic diagram of step S100 of the present invention; Figure 3 is a schematic structural diagram of step S200 of the present invention; Figure 4 is a schematic structural diagram of step S300 of the present invention; Figure 5 is a structural schematic diagram of step S400 of the present invention; Figure 6 is a schematic structural diagram of step S500 of the present invention; Figure 7 is a schematic diagram of the structure of step S700 of the present invention; Figure 8 is a structural schematic diagram of step S800 of the present invention; Fig. 9 is a structural schematic diagram of step S900 of the present invention; Fig.10 is a structural schematic diagram of step S1000 of the present invention; Fig.11 is a schematic diagram of the structure of step S1100 of the present invention; Fig.12 is a schematic diagram of the structure of step S1200 of the present invention; Fig.13 is a schematic diagram of the structure of step S1300 of the present invention; In the figure, 1 is SiC Sub layer, 2 is SiCDrift layer, 3 is P-shield area, 4 is SiC Epi layer, 5 is P-body area, 6 is NP area, 7 is the first trench area, 8 is the second trench area, 9 is gate oxide layer, 10 is Poly layer, 11 is isolation dielectric layer, 12 is ohmic contact alloy layer, and 13 is front electrode metal layer. DETAILED DESCRIPTION
[0016] The present invention is described in detail below in conjunction with specific practical cases. Examples of the embodiments are shown in the accompanying drawings, and the schematic implementation methods of the present invention and their descriptions are only used to explain the present invention and are not intended to limit the present invention.
[0017] In the description of the present invention, it should be understood that the terms "upper", "lower", "left", "right", "vertical", "horizontal", etc. indicate positions or positional relationships based on the positions or positional relationships shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific position, be constructed and operated in a specific position, and therefore cannot be understood as limiting the present invention. In the description of the present invention, unless otherwise specified, "plurality" means two or more.
[0018] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.
[0019] A method for preparing a deep buried junction SiC field effect transistor comprises the following steps: S100, forming a SiC Drift layer 2 on the top surface of the SiC Sub layer 1 by epitaxial deposition; The thickness of SiC Sub layer 1 in step S100 is 100um-400um, and the doping concentration is 5E18-3E19cm-2 , SiCDrift layer 2 thickness is 3um-10um, doping concentration is 1E15-5E16cm -2 .
[0020] S200, forming a P-shield region 3 arranged at intervals on the top surface of the SiC Drift layer 2 by Al ion implantation; The depth of the bottom surface of the P-shield region 3 from the top surface of the SiC Drift layer 2 in step S200 is 0.3um-1um, and the doping concentration is 1E18-1E19cm -2 .
[0021] S300, forming a SiC Epi layer 4 on the top surface of the SiC Drift layer 2 again by epitaxial deposition; The thickness of the SiC Epi layer 4 in step S300 is 5um-15um, and the doping concentration is 1E15-1E17cm -2 .
[0022] S400, forming a P-body region 5 on the top surface of the SiC Epi layer 4 by Al ion implantation; The depth of the bottom surface of the P-body region 5 from the top surface of the SiC Epi layer 4 in step S400 is 0.4um-1um, and the doping concentration is 1E17-3E18cm -2 .
[0023] S500, forming a NP region 6 on the top surface of the P-body region 5 by N ion implantation; The depth of the bottom surface of the NP region 6 from the top surface of the SiC Epi layer 4 in step S500 is 0.2um-0.7um, and the doping concentration is 1E18-1E19cm -2 .
[0024] S600, the P-shield region 3, the P-body region 5 and the NP region 6 are activated and formed by high temperature ion annealing; The high temperature ion annealing temperature in step S600 is 1600° C.-1900° C.
[0025] S700, etching downwards on the top surface of the NP region 6 to form a plurality of first trench regions 7 etched to the top surface of the P-shield region 3; S800, etching downwards on the top surface of the NP region 6 to form a plurality of second trench regions 8 etched into the SiC Epi layer 4; In step S800 , the depth between the bottom surface of the second trench region 8 and the top surface of the SiC Epi layer 4 is 0.6 um-1.5 um.
[0026] S900, introducing oxygen into the second trench region 8 to form a gate oxide layer 9 by dry oxygen oxidation; The thickness of the gate oxide layer 9 in step S900 is 30 nm-100 nm.
[0027] S1000, forming a Poly layer 10 in the second trench region 8 by polysilicon deposition; S1100, forming an isolation dielectric layer 11 on the top surface of the NP region 6 and the Poly layer 10 and the top surface of the P-shield region 3 by oxide deposition; In step S1100 , the isolation dielectric layer 11 on the top surface of the P-shield region 3 completely covers the sidewalls of the first trench region 7 .
[0028] S1200, forming an ohmic contact alloy layer 12 on the top surface of the NP region 6 and the P-shield region 3 by thermal annealing after Ni metal deposition; The Ni metal thickness in step S1200 is 0.3um-1um.
[0029] S1300, at the top of the device by Ti and AlCu metal sputtering to form a front electrode metal layer 13; The thickness of the Ti metal in step S1300 is 0.1um-0.6um, and the thickness of the AlCu metal is 2um-5um.
[0030] A deep buried junction SiC field effect transistor, comprising a SiC Sub layer 1, a SiC Drift layer 2, a SiC Epi layer 4, a P-body region 5, an NP region 6, an ohmic contact alloy layer 12 and a front electrode metal layer 13 arranged in sequence from bottom to top; The top surface of the SiC Drift layer 2 is provided with a plurality of P-shield regions 3 extending downward at intervals; The top surface of the NP region 6 is provided with a plurality of first trench regions 7 etched downward to the top surface of the P-shield region 3 and a plurality of second trench regions 8 etched downward to the SiC Epi layer 4; There is a gap between the bottom surface of the second trench region 8 and the bottom surface of the SiC Epi layer 4; the first trench region 7 is located between adjacent second trench regions 8; A gate oxide layer 9 is provided in the second trench region 8, and the cross section of the gate oxide layer 9 is a U-shaped structure; a Poly layer 10 is provided on the gate oxide layer 9; and the top surface of the Poly layer 10 is in the same plane as the top surface of the NP region 6; An isolation dielectric layer 11 is provided on the top surface of the NP region 6 and the sidewall of the first trench region 7, respectively; the bottom surface of the isolation dielectric layer 11 on the NP region 6 is connected to the NP region 6, the second trench region 8 and the Poly layer 10, respectively; the bottom of the isolation dielectric layer 11 in the first trench region 7 is connected to the P-shield region 3, and the side is connected to the NP region 6, the P-body region 5 and the SiC Epi layer 4, respectively; The bottom of the ohmic contact alloy layer 12 extends into the first trench region 7 and is connected to the P-shield region 3 , and the top is located at the side of the isolation dielectric layer 11 .
[0031] The bottom of the front electrode metal layer 13 is connected to the ohmic contact alloy layer 12 and the isolation dielectric layer 11 respectively.
[0032] The corners at the bottom of the trench in the prior art trench gate SiC MOSFET are very likely to cause electric field concentration, and the gate oxide layer formed by SiC thermal oxidation growth has poor quality due to the large interface state density. These factors make the gate oxide layer at the bottom corner of the trench of the trench gate SiC MOSFET prone to premature breakdown failure during use, affecting long-term stable use. The present invention is aimed at this problem. Figure 1 As shown, in the trench gate SiC MOSFET, a P-shield region 3 with a deep buried junction is formed, and the P-shield region 3 is set at a bottom deeper than the trench region, so that during the use of the device, the depletion layer formed by the P-shield region 3 with a deep buried junction and the SiC Drift layer 2 and the Epi layer 4 is extended to the bottom corner of the trench, thereby protecting the gate oxide layer at the bottom corner of the trench and improving the long-term stable use reliability of the device. At the same time, by etching a trench opening above the P-shield region 3 and preparing an ohmic contact, the P-shield region 3 is grounded, further improving the protection capability of the P-shield region 3.
Claims
1. A method for preparing a deep buried junction SiC field effect transistor, characterized in that: The steps include: S100, forming a SiC Drift layer (2) on the top surface of the SiC Sub layer (1), and implanting ions on the top surface of the SiC Drift layer (2) to form a P-shield region (3) arranged at intervals; S200, forming a SiC Epi layer (4), a P-body region (5) and a NP region (6) in sequence on the top surface of the SiC Drift layer (2); S300, forming a plurality of first trench regions (7) and a plurality of second trench regions (8) on the top surface of the NP region (6) by etching in sequence; the second trench regions (8) are etched to the top surface of the P-shield region (3); and the second trench regions (8) are etched to the inside of the SiC Epi layer (4); S400, forming a gate oxide layer (9) and a Poly layer (10) in sequence in the second trench region (8); S500, forming an isolation dielectric layer (11) by deposition on the top surface of the second trench region (8) and on the sidewalls of the first trench region (7); S600, forming an ohmic contact alloy layer (12) on the top surface of the NP region (6) and the P-shield region (3) by thermal annealing after Ni metal deposition; S700, forming a front electrode metal layer (13) on the top of the device by sputtering Ti and AlCu metals.
2. The method for preparing a deep buried junction SiC field effect transistor according to claim 1, characterized in that: In step S100, the thickness of the SiC Drift layer (2) is 3um-10um, and the doping concentration is 1E15-5E16cm -2 .
3. The method for preparing a deep buried junction SiC field effect transistor according to claim 1, characterized in that: In step S100, the depth of the bottom surface of the P-shield region (3) from the top surface of the SiC Drift layer (2) is 0.3um-1um, and the doping concentration is 1E18-1E19cm -2 .
4. The method for preparing a deep buried junction SiC field effect transistor according to claim 1, characterized in that: The thickness of the SiC Epi layer (4) in step S200 is 5um-15um, and the doping concentration is 1E15-1E17cm -2 .
5. The method for preparing a deep buried junction SiC field effect transistor according to claim 1, characterized in that: In step S200, the depth of the bottom surface of the P-body region (5) from the top surface of the SiC Epi layer (4) is 0.4um-1um, and the doping concentration is 1E17-3E18cm -2 .
6. The method for preparing a deep buried junction SiC field effect transistor according to claim 1, characterized in that: In step S200, the depth of the bottom surface of the NP region (6) from the top surface of the SiC Epi layer (4) is 0.2um-0.7um, and the doping concentration is 1E18-1E19cm -2 .
7. The method for preparing a deep buried junction SiC field effect transistor according to claim 1, characterized in that: The thickness of the SiC Sub layer (1) in step S100 is 100um-400um, and the doping concentration is 5E18-3E19cm -2 .
8. The method for preparing a deep buried junction SiC field effect transistor according to claim 1, characterized in that: In step S300, the depth between the bottom surface of the second trench region (8) and the top surface of the SiC Epi layer (4) is 0.6 um-1.5 um.
9. A deep buried junction SiC field effect transistor, prepared by the method for preparing a deep buried junction SiC field effect transistor according to any one of claims 1 to 8, characterized in that: It includes a SiC Sub layer (1), a SiC Drift layer (2), a SiC Epi layer (4), a P-body region (5), an NP region (6), an Ohmic contact alloy layer (12), and a front electrode metal layer (13) which are arranged in sequence from bottom to top; The top surface of the SiC Drift layer (2) is provided with a plurality of P-shield regions (3) extending downward at intervals; The top surface of the NP region (6) is provided with a plurality of first groove regions (7) etched downward to the top surface of the P-shield region (3) and a plurality of second groove regions (8) etched downward to the inside of the SiC Epi layer (4); a gap is provided between the bottom surface of the second groove region (8) and the bottom surface of the SiC Epi layer (4); A gate oxide layer (9) is provided in the second trench region (8); a Poly layer (10) is provided on the gate oxide layer (9); An isolation dielectric layer (11) is provided on the top surface of the NP region (6) and the side wall of the first trench region (7); the bottom surface of the isolation dielectric layer (11) on the NP region (6) is connected to the NP region (6), the second trench region (8) and the Poly layer (10) respectively; The bottom of the ohmic contact alloy layer (12) extends into the first groove area (7) and is connected to the P-shield area (3), and the top is located on the side of the isolation dielectric layer (11).
10. The deep buried junction SiC field effect transistor according to claim 9, characterized in that: The bottom of the front electrode metal layer (13) is respectively connected to the ohmic contact alloy layer (12) and the isolation dielectric layer (11).