Multi-phase power converter circuit layout to minimize drive loop inductance and power loop inductance

Abstract

A multi-phase power converter includes a printed circuit board having a plurality of conductive layers in spaced apart and parallel relationship. The plurality of conductive layers includes a plurality of power planes in an interleaved configuration with alternating positive and negative voltages and configured to conduct a relatively high current for supply to a load. The multiphase power converter also includes a plurality of switching transistors disposed on the upper surface of the printed circuit board and configured to selectively conduct a relatively high current. The conductive layer includes at least one signal plane disposed between the plurality of power planes and a surface of the printed circuit board, the at least one signal plane transmitting a signal for controlling operation of the plurality of switching transistors. The power converter phase includes a high-side transistor, a low-side transistor, and a driver circuit disposed adjacent the transistors.

Description

Technical Field

[0001] The present disclosure generally relates to physical circuit layouts for power converters, such as multi-phase DC-DC power converters. Background Art

[0002] Power converters can be used in a variety of different applications, for example, LVdc-dc converters in server power supplies and electric vehicles (EVs). In many such applications, the power converter may have an output current of up to hundreds to thousands of amperes, which may become a bottleneck for improving converter efficiency. In this case, multiphase technology is often used to reduce conduction losses and improve efficiency. By distributing the large output current to several parallel phases, the current in each phase is reduced. Therefore, the conduction loss associated with the square of the current is reduced. For the printed circuit board layout of such a multiphase converter, the power loop and the drive loop are coupled to a higher degree when compared to the single-phase case. Such coupling in a multiphase power converter may result in undesirable parasitic drive loop and power loop inductance. Parasitic inductance in the drive loop may result in oscillation, which may damage or destroy the transistor.

[0003] Several different designs have been used to optimize the printed circuit board (PCB) layout of multiphase power converters. In one such design, the transistors, drivers, and decoupling capacitors are placed separately in a single line. The driver is then placed between the transistor and the capacitor. The inner layer is used for the power loop. Space is needed between the driver and the decoupling capacitor to route the drive signal. The drive loop inductance is minimized, but the power loop inductance is compromised.

[0004] In another design, through-hole transistors of different phases are placed in different lines. In each phase, decoupling capacitors are placed next to the transistors to minimize the power loop inductance. The drivers are placed on the bottom side next to the transistors to minimize the drive loop inductance. This layout is not suitable for surface mount transistors.

[0005] In another design, the driver and transistor are integrated into a single package, which is placed next to the decoupling capacitors. Due to the integration, the driver loop inductance is minimized. At the same time, the power loop is not compromised. However, this layout is not suitable for the general case where the driver and transistor are set in different packages. Summary of the invention

[0006] The present disclosure provides a multiphase power converter. The multiphase power converter includes a printed circuit board having a plurality of conductive layers in a spaced-apart and parallel relationship, wherein the plurality of conductive layers include a plurality of power planes, the plurality of power planes are in an interlaced configuration with alternating positive and negative voltages, and are configured to conduct a relatively high current for supplying to a load. The multiphase power converter also includes a plurality of switching transistors, the plurality of switching transistors are disposed on an upper surface of the printed circuit board, and are configured to selectively conduct a relatively high current for supplying to a load. The plurality of conductive layers include at least one signal plane disposed between the plurality of power planes and a surface of the printed circuit board, the at least one signal plane transmitting a signal for controlling the operation of the plurality of switching transistors.

[0007] The present disclosure also provides a multiphase power converter. The multiphase power converter includes a printed circuit board and a power converter phase. The power converter phase includes a first bridge branch, and the first bridge branch includes a first high-side transistor and a first low-side transistor. The first high-side transistor is configured to selectively guide current between the positive terminal of the input bus and the first intermediate node, and the first low-side transistor is configured to selectively guide current between the first intermediate node and the negative terminal of the input bus. The power converter phase also includes a first driver circuit arranged adjacent to the first bridge branch. The first driver circuit is configured to generate a drive signal for controlling the operation of each of the first high-side transistor and the first low-side transistor. The power converter phase also includes a plurality of other power components arranged adjacent to the first bridge branch and opposite to the first driver circuit. A plurality of other power components are connected to the first intermediate node to receive power from the first intermediate node.

[0008] The present disclosure also provides a method for operating a multiphase power converter. The method includes: conducting a current for supplying to a load through a plurality of power planes of a plurality of conductive layers in a printed circuit board, wherein the plurality of conductive layers are arranged in a spaced-apart and parallel relationship, and the plurality of power planes are arranged in a staggered configuration with alternating positive and negative voltages; selectively conducting the current for supplying to the load through a plurality of switching transistors disposed on an upper surface of the printed circuit board; and transmitting a signal for controlling the operation of the plurality of switching transistors through at least one signal plane of the plurality of conductive layers, wherein the at least one signal plane is disposed between the plurality of power planes and a surface of the printed circuit board. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Further details, features and advantages of the inventive design emerge from the following description of an embodiment example with reference to the associated drawings.

[0010] Figure 1 shows a schematic diagram of a multiphase power converter;

[0011] Figure 2 Shows Figure 1 A schematic diagram of a switch driver circuit of a multi-phase power converter;

[0012] Figure 3 shows a schematic diagram of a two-phase LLC power converter;

[0013] Figure 4 shows a top view of a printed circuit board (PCB) layout for a multiphase power converter according to the present disclosure;

[0014] Figure 5 shows a cross-sectional side view showing layers in a PCB according to some embodiments of the present disclosure; and

[0015] Figure 6 shows a power loop of a multi-phase converter using a PCB layout according to the present disclosure;

[0016] Figure 7 shows a generalized power loop of a multi-phase converter using a PCB layout according to the present disclosure; and

[0017] Figure 8 A flow chart illustrating steps in a method of operating a multi-phase power converter is shown. DETAILED DESCRIPTION

[0018] With reference to the accompanying drawings, the present invention will be described in detail according to the following embodiments.

[0019] The present disclosure provides a novel printed circuit board (PCB) layout scheme for a multiphase power converter to minimize both the drive loop inductance and the power loop inductance. The scheme minimizes the drive loop inductance by placing the driver next to the transistor. The power loop inductance may increase the voltage stress of the transistor and may also damage the transistor. The scheme minimizes the power loop inductance by minimizing the power loop area as much as possible and providing as many paths as possible for high-frequency current. The PCB layout design of the present disclosure is applicable to both surface mount transistors and through-hole transistors in half-bridge and full-bridge configurations.

[0020] Figure 1 to Figure 2 The power loop and drive loop in a typical multi-phase converter including a switching network and other power components (eg, inductors, capacitors, and transformers) are shown.

[0021] Figure 1 A schematic diagram of a multi-phase power converter 20 is shown. Figure 1The multiphase power converter 20 is configured to receive DC power from an input bus 22 having a positive terminal 23 defining a positive bus voltage HV_P and a negative terminal 24 defining a negative bus voltage HV_N. An input capacitor 25 is connected across the positive terminal 23 and the negative terminal 24 of the input bus 22. The multiphase power converter 20 supplies power to an output bus 26 at an output voltage Vo that may be different from an input voltage Vin on the input bus 22. The multiphase power converter 20 includes a plurality of power converter phases 28a, 28b, 28c. In Figure 1 In the example configuration shown, three power converter phases 28a, 28b, 28c are shown. However, the multiphase power converter 20 may have any number n of phases, where n is greater than one.

[0022] Each power converter phase 28a, 28b, 28c of the multiphase power converter 20 can have a similar or identical construction. In order to simplify the present disclosure, the first power converter phase 28a is described in detail. The first power converter phase 28a includes an input capacitor 30 connected across the input bus 22. The first power converter phase 28a also includes a switch network 32 connected to the input bus 22. The switch network 32 may also be referred to as an inverter stage, and may include one or more switches, such as switching transistors, which are used to switch the input power at an operating frequency to generate a switching power of an approximate alternating current (AC) waveform. The switch network 32 can be implemented in a half-bridge configuration or a full-bridge configuration. During operation, a power loop 33 can be generated in a conductor between the input capacitor 30 and the switch network 32.

[0023] The first power converter phase 28a also includes other power components 34 powered by the switch network 32. The other power components 34 may include one or more transformers, one or more inductors and / or capacitors, and / or one or more switches or diodes forming a rectifier. The other power components 34 may supply the DC output power to the output bus 26. The first power converter phase 28a also includes an output capacitor 36 connected across the output bus 26 for smoothing ripples in the output voltage Vo that may be generated by the operation of the switch network 32 and / or other power components 34.

[0024] Figure 2 Shows Figure 1Schematic diagram of a switch driver circuit 38 of a multi-phase power converter 20. The switch driver circuit 38 includes a driver 40 coupled to a switch transistor 42 (e.g., a field effect transistor 42). The driver 40 generates a control signal that is applied to the gate of the switch transistor 42 for controlling the operation of the switch transistor 42. The switch driver circuit 38 defines a drive loop 43, which is a current loop for the control signal applied to the gate of the switch transistor 42. An input resistance Rds is also shown in the drive loop 43, which may include a drain-source resistance of the switch transistor 42. The input resistance Rds may be a feature of the switch transistor 42 rather than a separate physical device.

[0025] Figure 3 A two-phase inductor-inductor-capacitor (LLC) power converter 50 is shown, which includes a first LLC power converter phase 58a and a second LLC power converter phase 58b. This is merely an example, and the principles of the present disclosure can be applied to several different types of power converters having different numbers of phases (e.g., two phases, three phases, four phases, etc.).

[0026] LLC power converter 50 may display Figure 1 A specific implementation of a more general multi-phase power converter 20 is provided. Figure 3 An LLC power converter 50 is shown including a first LLC power converter phase 58a and a second LLC power converter phase 58b. Each of the LLC converter phases has a switch network 32 having a full-bridge configuration and providing a corresponding power loop 33. Figure 3 A driving loop 43 is also shown in each of the switching networks 32. However, the LLC power converter 50 may include a driving loop 43 for each of the switching transistors included in the driving loop.

[0027] The parasitic inductance in the drive loop 43 may cause the gate voltage of the transistor to oscillate. The oscillation at the turn-on moment may damage the gate of the transistor. And the oscillation at the turn-off moment may cause the transistor to be turned on unintentionally, which may cause a short circuit of the two transistors through the bridge branch, which may damage the two transistors. The parasitic inductance in the power loop 33 may cause the drain-to-source voltage of the transistor to oscillate, thereby increasing their voltage stress, which is associated with the on-state resistance Rds (on) and price. In addition, the oscillation may increase the electromagnetic emission and radiation level of the device, which may be harmful to other devices. Therefore, minimizing the drive loop inductance and the power loop inductance are two main goals in PCB layout.

[0028] The proposed multiphase converter PCB layout scheme minimizes both the drive loop inductance and the power loop inductance and is suitable for both surface mount and through-hole transistors in half-bridge or full-bridge configurations. The proposed PCB layout scheme provides reduced drive loop inductance by placing the driver next to the transistor. When compared to conventional designs, the proposed PCB layout scheme also provides reduced power loop inductance by minimizing the power loop area and providing many different paths for high frequency currents.

[0029] Structure and Design of Multiphase Converter PCB Layout

[0030] The PCB layout of the present disclosure is configured to minimize the drive loop inductance and the power loop inductance at the same time. An example of the structure and design of the proposed multi-phase converter PCB layout is described in detail below. Although this example uses a full-bridge structure for the switch network, where a dual-channel driver is used for high-side and low-side transistors, and a surface mount technology (SMT) package for transistors is used, it should be noted that the proposed layout can also be applied to a switch network 32 with a half-bridge configuration, a single-channel driver for high-side and low-side components, and a transistor with through-hole technology (THT).

[0031] Figure 4A top view of a PCB layout 100 for a multiphase converter according to one aspect of the present disclosure is shown. The PCB layout 100 includes a plurality of switch transistors 110, such as FETs, arranged in a row. The plurality of switch transistors 110 are arranged in a bridge branch 112. Each bridge branch 112 includes a high-side transistor and a low-side transistor. The high-side transistor is configured to selectively guide current between the positive terminal HV_P of the input bus and the intermediate node 114. The low-side transistor is configured to selectively guide current between the intermediate node 114 and the negative terminal HV_N of the input bus. The switch transistors 110 in the switch network are placed in a row, wherein the high-side transistors and the low-side transistors are staggered. The high-side transistor is a transistor connected to the positive bus voltage (HV_P), and the low-side transistor is a transistor connected to the negative bus voltage (HV_N). A local decoupling capacitor 116 is located between each bridge branch including the high-side and low-side transistors to provide high-frequency current, whether the bridge branches are in the same phase or different phases. Instead of or in addition to the input capacitor 30 connected across the positive terminal HV_P and the negative terminal HV_N of the input bus 22, a local decoupling capacitor 116 can be used. Due to these local decoupling capacitors 116, a large-capacity capacitor supplying low-frequency current can be placed away from the switching transistor 110. The copper area with the HV_P or HV_N net is connected to the inner HV_P and HV_N layers through vias. The driver 40 branch is placed above the bridge branch 112 and as close as possible to the bridge branch 112, so that the inductance of the drive loop 43 is minimized. Other components 118 such as inductors, capacitors, etc. are placed below the bridge branch 112. By doing this, the signal area and the power area are decoupled, which significantly reduces the difficulty of routing even if the power area has a high voltage.

[0032] Figure 5 A cross-sectional side view of a PCB stack-up showing the proposed PCB layout is shown. A multi-layer PCB 150 is used for this solution.

[0033] The multilayer PCB 150 includes an upper surface 152 and a lower surface 154 opposite to the upper surface 152. Components are placed on the upper surface 152 and / or the lower surface 154. The outer layers adjacent to the upper surface 152 and / or the lower surface 154 can be used for signals such as drive, protection and control signals and HV_P or HV_N bus voltages. In the outer layers, the signal area in the top view is used for signals, and the power area is used for HV_P or HV_N bus voltages. The number of signal layers can be determined according to the complexity of the signal and cost constraints. Signal grounding can also be obtained in the signal area of ​​these layers to improve signal quality. Local drive grounding can be used under the driver to further minimize the drive loop inductance. The inner layer is used for HV_P and HV_N bus voltages. The number of HV_P and HV_N voltages is selected according to the rated current and cost constraints. All layers are used for HV_P or HV_N bus voltages. The HV_P layer and the HV_N layer are staggered as much as possible to maximize the parasitic capacitance between HV_P and HV_N. These parasitic capacitances provide additional paths for very high frequency currents of the power loop (and may supplement the local decoupling capacitors 116) so that the power loop inductance is further minimized in addition to the mechanisms explained below.

[0034] Figure 6 The power loop of the proposed multi-phase converter PCB layout is shown. Figure 7 An associated abstract power loop is shown. It should be noted that the accompanying drawings are associated with SMT transistors and through-hole transistors with bottom-side cooling. The copper under the transistor may not be available for distributing the HV_P and HV_N bus voltages because of the thermal vias or through-hole pads installed under the transistor for bottom cooling. For this configuration, the power loop including the bridge branch and the local decoupling capacitor 116 is closed by the lateral HV_P or HV_N copper area. The local decoupling capacitor 116 can provide high-frequency current not only for the bridge branch adjacent to the capacitor, but also for the bridge branch away from the capacitor. By doing so, the power loop area is minimized. In addition, as many paths as possible are provided for high-frequency current. Therefore, the power loop inductance is minimized. For SMT transistors with top-side cooling, the copper area under the transistor can be used for HV_P and HV_N voltages. The power loop inductance can be further minimized.

[0035] In summary, by placing the driver next to the transistor, the driver loop inductance is minimized. By minimizing the power loop area and providing many different paths for high frequency currents, the power loop inductance is minimized. In this scheme, both the driver loop inductance and the power loop inductance are minimized at the same time.

[0036] The present disclosure provides a multiphase power converter. The multiphase power converter includes a printed circuit board having a plurality of conductive layers in a spaced-apart and parallel relationship, wherein the plurality of conductive layers include a plurality of power planes, the plurality of power planes are in an interlaced configuration with alternating positive and negative voltages, and are configured to conduct a relatively high current for supplying to a load. The multiphase power converter also includes a plurality of switching transistors, the plurality of switching transistors are disposed on an upper surface of the printed circuit board, and are configured to selectively conduct a relatively high current for supplying to a load. The plurality of conductive layers include at least one signal plane disposed between the plurality of power planes and a surface of the printed circuit board, the at least one signal plane transmitting a signal for controlling the operation of the plurality of switching transistors.

[0037] In some embodiments, the multi-phase power converter further includes a plurality of power components disposed on an upper surface of the printed circuit board and on a lower surface opposite to the upper surface of the printed circuit board.

[0038] In some implementations, at least one signal plane includes a power region configured to conduct a significantly higher current than a signal used to control operation of the plurality of switching transistors.

[0039] In some embodiments, the at least one signal plane includes two or more signal planes disposed adjacent to each other.

[0040] In some embodiments, the multi-phase power converter further includes a second signal plane disposed between the plurality of power planes and a lower surface of the printed circuit board opposite the upper surface of the printed circuit board.

[0041] The present disclosure provides a multiphase power converter, which includes a printed circuit board and a power converter phase. The power converter phase includes a first bridge branch. The first bridge branch includes a first high-side transistor and a first low-side transistor. The first high-side transistor is configured to selectively conduct current between a positive terminal of an input bus and a first intermediate node, and the first low-side transistor is configured to selectively conduct current between the first intermediate node and a negative terminal of the input bus. The power converter phase also includes a first driver circuit, which is arranged adjacent to the first bridge branch and is configured to generate a drive signal for controlling the operation of each of the first high-side transistor and the first low-side transistor. The power converter phase also includes a plurality of other power components, which are arranged adjacent to the first bridge branch and opposite to the first driver circuit, and the plurality of other power components are connected to the first intermediate node to receive power therefrom. The multiphase power converter can be in Figure 4 shown in and described herein.

[0042] In some embodiments, the power converter phase also includes a second bridge branch, the second bridge branch includes a second high-side transistor and a second low-side transistor, the second high-side transistor is configured to selectively guide current between the positive terminal of the input bus and the second intermediate node, and the second low-side transistor is configured to selectively guide current between the second intermediate node and the negative terminal of the input bus. The power converter phase may also include a second driver circuit, the second driver circuit is arranged adjacent to the second bridge branch, and is configured to generate a drive signal for controlling the operation of each of the second high-side transistor and the second low-side transistor. A plurality of other power components can be arranged adjacent to the second bridge branch and opposite to the second driver circuit, and a plurality of other power components are connected to the second intermediate node to receive power therefrom.

[0043] In some embodiments, the power converter phase is one of a plurality of power converter phases each disposed on a printed circuit board.

[0044] In some implementations, a plurality of power converter phases each include a corresponding switching transistor arranged along a straight line.

[0045] In some implementations, a plurality of power converter phases each include a corresponding driver circuit arranged on a same side of the straight line of switching transistors.

[0046] In some embodiments, the first bridge branch is one of a plurality of groups of switching transistors, each group of switching transistors defines a corresponding bridge branch, and the multi-phase power converter includes a local decoupling capacitor, which is located between each group of switching transistors in the plurality of groups of switching transistors and is configured to supply a high-frequency current to each group of switching transistors.

[0047] exist Figure 8 A method 200 of operating a multiphase power converter is shown in a flowchart of FIG. As can be appreciated from the present disclosure, the order of operations within the method is not limited to the following. Figure 8 The embodiments are not performed in the order shown, but may be performed in one or more alternate orders as applicable and in accordance with the present disclosure.

[0048] Method 200 includes, at step 202, conducting current for supplying a load through a plurality of power planes of a plurality of conductive layers in a printed circuit board, wherein the plurality of conductive layers are arranged in a spaced-apart and parallel relationship and the plurality of power planes are arranged in a staggered configuration having alternating positive and negative voltages.

[0049] The method 200 further includes, at step 204 , selectively conducting current for supplying to a load through a plurality of switching transistors disposed on an upper surface of the printed circuit board.

[0050] The method 200 further includes, at step 206 , transmitting signals for controlling operation of the plurality of switching transistors through at least one signal plane in the plurality of conductive layers, wherein the at least one signal plane is disposed between the plurality of power planes and a surface of the printed circuit board.

[0051] The method 200 also includes, at step 208 , conducting a current through the power region of the at least one signal plane that is substantially higher than a signal used to control operation of the plurality of switching transistors.

[0052] In some embodiments, the at least one signal plane includes two or more signal planes disposed adjacent to each other.

[0053] In some embodiments, the printed circuit board further includes a second signal plane disposed between the plurality of power planes and a lower surface of the printed circuit board opposite the upper surface of the printed circuit board.

[0054] The foregoing description is not intended to be exhaustive or limit the present disclosure. Each element or feature of a particular embodiment is generally not limited to that particular embodiment, but is interchangeable where applicable, and can be used in a selected embodiment, even if not specifically shown or described. It can also change in many ways. Such a change should not be considered as departing from the present disclosure, and all such modifications are intended to be included within the scope of the present disclosure.

Claims

1. A multiphase power converter, comprising: a printed circuit board having a plurality of conductive layers in a spaced-apart and parallel relationship, wherein the plurality of conductive layers include a plurality of power planes in a staggered configuration having alternating positive and negative voltages and configured to conduct relatively high currents for supply to a load; and a plurality of switching transistors disposed on an upper surface of the printed circuit board and configured to selectively conduct the relatively high current for supplying the load, The plurality of conductive layers include at least one signal plane disposed between the plurality of power planes and a surface of the printed circuit board, the at least one signal plane transmitting a signal for controlling operations of the plurality of switch transistors. 2 . The multiphase power converter according to claim 1 , further comprising a plurality of power components disposed on an upper surface of the printed circuit board and on a lower surface opposite to the upper surface of the printed circuit board.

3. The multiphase power converter according to claim 1, wherein: The at least one signal plane includes a power region configured to conduct a significantly higher current than the signal used to control operation of the plurality of switching transistors.

4. The multiphase power converter according to claim 1, wherein: The at least one signal plane includes two or more signal planes disposed adjacent to each other. 5 . The multiphase power converter of claim 1 , further comprising a second signal plane disposed between the plurality of power planes and a lower surface of the printed circuit board opposite to the upper surface of the printed circuit board.

6. A multiphase power converter comprising: Printed circuit boards; as well as Power converter phases, including: a first bridge branch, the first bridge branch comprising a first high-side transistor and a first low-side transistor, the first high-side transistor being configured to selectively conduct current between a positive terminal of an input bus and a first intermediate node, and the first low-side transistor being configured to selectively conduct current between the first intermediate node and a negative terminal of the input bus; a first driver circuit disposed adjacent to the first bridge branch and configured to generate a drive signal for controlling operation of each of the first high-side transistor and the first low-side transistor; and A plurality of other power components are disposed adjacent to the first bridge branch and opposite to the first driver circuit, and are connected to the first intermediate node to receive power from the first intermediate node.

7. The multiphase power converter according to claim 6, wherein: The power converter phase further comprises: a second bridge branch, the second bridge branch comprising a second high-side transistor and a second low-side transistor, the second high-side transistor being configured to selectively conduct current between a positive terminal of the input bus and a second intermediate node, and the second low-side transistor being configured to selectively conduct current between the second intermediate node and a negative terminal of the input bus; and a second driver circuit disposed adjacent to the second bridge branch and configured to generate a drive signal for controlling operation of each of the second high-side transistor and the second low-side transistor, The plurality of other power components are arranged adjacent to the second bridge branch and opposite to the second driver circuit, and the plurality of other power components are connected to the second intermediate node to receive power from the second intermediate node.

8. The multiphase power converter according to claim 6, wherein: The power converter phase is one of a plurality of power converter phases each disposed on the printed circuit board.

9. The multiphase power converter according to claim 8, wherein: The plurality of power converter phases each include a corresponding switching transistor arranged along a line.

10. The multiphase power converter according to claim 9, wherein: The plurality of power converter phases each include a corresponding driver circuit arranged on a same side of the straight line of switching transistors.

11. The multiphase power converter according to claim 6, wherein: The first bridge branch is one of a plurality of groups of switching transistors, each group of switching transistors defining a corresponding bridge branch; and A local decoupling capacitor is located between each group of switching transistors in the plurality of groups of switching transistors and is configured to supply a high frequency current to each group of switching transistors.

12. A method of operating a multiphase power converter, comprising: conducting current for supplying a load through a plurality of power planes of a plurality of conductive layers in a printed circuit board, wherein the plurality of conductive layers are arranged in a spaced-apart and parallel relationship and the plurality of power planes are arranged in a staggered configuration having alternating positive and negative voltages; selectively conducting current for supply to the load through a plurality of switching transistors disposed on an upper surface of the printed circuit board; and Signals for controlling operation of the plurality of switching transistors are transmitted through at least one signal plane of the plurality of conductive layers, wherein the at least one signal plane is disposed between the plurality of power planes and a surface of the printed circuit board.

13. The method according to claim 12, further comprising: A power region through the at least one signal plane conducts a significantly higher current than a signal used to control operation of the plurality of switching transistors.

14. The method according to claim 12, wherein: The at least one signal plane includes two or more signal planes disposed adjacent to each other.

15. The method according to claim 12, wherein: The printed circuit board also includes a second signal plane disposed between the plurality of power planes and a lower surface of the printed circuit board opposite the upper surface of the printed circuit board.

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