Wafer surface treatment method and application thereof

Abstract

The invention provides a wafer surface treatment method and application thereof, and belongs to the technical field of semiconductor manufacturing. The surface treatment method comprises the following steps that the step position of the surface of a wafer to be polished is determined; performing etching treatment on the step so as to form a groove structure at the step; and carrying out chemical mechanical polishing treatment on the etched wafer. By introducing the etching step before CMP, the groove structure is formed at the step, so that the subsequent CMP process is optimized, the removal amount of materials is reduced, the uniformity of the wafer edge is improved, and the overall processing efficiency is improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor manufacturing technology, and in particular to a surface treatment method for a wafer and its application. Background Art

[0002] Chemical Mechanical Polishing (CMP) is a key process for flattening the wafer surface in semiconductor manufacturing and is widely used in polishing materials such as oxide layers and metal layers. Its function is to provide a flat substrate for subsequent process steps and improve process accuracy.

[0003] Since MEMS (Micro-Electro-Mechanical Systems) products have complex structures, with multiple layers of material stacking and high steps, CMP needs to remove more material in certain areas to achieve flattening. However, when facing complex structures, the existing technology is difficult to control the removal amount and uniformity, especially in areas with large steps, the surface uniformity after polishing is poor, affecting subsequent processes and product performance. Summary of the invention

[0004] In view of this, the embodiment of the present application is dedicated to providing a surface treatment method of a wafer, comprising the following steps:

[0005] Determining the step position on the surface of the wafer to be polished;

[0006] Performing etching on the step to form a groove structure at the step;

[0007] The etched wafer is subjected to chemical mechanical polishing.

[0008] Optionally, the surface of the wafer to be polished further includes a reference surface connected to the step, and the height difference between the bottom surface of the groove structure and the reference surface ranges from 0 μm to 0.2 μm.

[0009] Optionally, a ratio of a cross-sectional width of the groove structure to that of the step is in a range of 1:2 to 3:4.

[0010] Optionally, the depth of the groove structure ranges from 0.1 μm to 1 μm.

[0011] Optionally, the groove structure has an opening, the width of the opening is greater than the width of the bottom of the groove structure, and the plane where the opening is located is flush with the upper surface of the step.

[0012] Optionally, the groove structure is in an inverted trapezoidal shape, and a side wall angle of the groove structure ranges from 30° to 60°.

[0013] Optionally, the sidewall of the groove structure includes a plurality of steps which are parallel to each other and have height differences.

[0014] Optionally, the bottom surface of the groove structure has a nanometer-scale surface roughness.

[0015] Optionally, the step is an epitaxial layer step of a wafer.

[0016] In particular, the present invention also provides an application of the surface treatment method as described above, which is applied to the manufacture of micro-electromechanical systems or integrated circuits.

[0017] The traditional CMP process often needs to remove too much material when processing higher metal steps such as 1.2μm, resulting in uneven thickness at the edge of the wafer. In the solution of the present invention, an etching step is introduced before CMP to form a groove structure at the step, thereby optimizing the subsequent CMP process, reducing the amount of material removed, improving the uniformity of the wafer edge, and improving the overall processing efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 A schematic flow chart of a surface treatment method for a wafer according to an embodiment of the present invention is shown;

[0019] Figure 2 A schematic structural diagram of a wafer to be polished before surface treatment according to an embodiment of the present invention is shown;

[0020] Figure 3 A schematic structural diagram showing a groove structure formed at a step according to an embodiment of the present invention is shown;

[0021] Figure 4 shows a schematic structural diagram of a wafer after surface treatment according to an embodiment of the present invention;

[0022] Figure 5 A wafer full surface uniformity performance diagram of a wafer after surface treatment according to an embodiment of the present invention is shown; In the figure: 1-silicon substrate, 2-epitaxial layer, 21-metal layer, 22-oxide layer, 3-step, 31-groove structure, 311-bottom surface, 312-opening, 313-sidewall structure, 4-reference plane. DETAILED DESCRIPTION

[0023] In order to make the above-mentioned purposes, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are described in detail below in conjunction with the accompanying drawings. It is to be understood that the specific embodiments described herein are only used to explain the present application, rather than to limit the present application. It should also be noted that, for ease of description, only some structures related to the present application are shown in the accompanying drawings, rather than all structures. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0024] The word “exemplary” is used exclusively herein to mean “serving as an example, example, or illustration.” Any embodiment described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments.

[0025] In addition, in order to better illustrate the present invention, numerous specific details are provided in the following specific embodiments. It should be understood by those skilled in the art that the present invention can also be implemented without certain specific details. In some examples, methods, means, components and circuits well known to those skilled in the art are not described in detail in order to highlight the subject matter of the present disclosure.

[0026] It should be understood that the term "and / or" in this article is only a description of the association relationship of the associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article indicates that the associated objects before and after are in an "or" relationship.

[0027] The "multiple" in the embodiments of the present invention refers to two or more. The first, second, etc. descriptions in the embodiments of the present invention are only used for illustration and distinction of the described objects, and have no order, nor do they represent a special limitation on the number in the embodiments of the present invention, and cannot constitute any limitation on the embodiments of the present invention.

[0028] In the prior art, those skilled in the art generally believe that the CMP process can effectively improve the flatness of the wafer by adjusting the grinding pressure and speed without additional pretreatment. Therefore, the view that the wafer flatness is achieved solely by the CMP process has formed a technical prejudice to a certain extent. The present application overcomes this technical prejudice and proposes a new method for achieving wafer flatness, which achieves a large amount of material removal (greater than 2μm).

[0029] Figure 1 FIG. 1 is a schematic flow chart of a surface treatment method for a wafer according to an embodiment of the present invention. Figure 1 As shown, the surface treatment method includes:

[0030] Step S100, determining the step position on the surface of the wafer to be polished;

[0031] Step S200, etching the step to form a groove structure at the step;

[0032] Step S300, performing chemical mechanical polishing on the etched wafer.

[0033] Figure 2 FIG. 2 shows a schematic structural diagram of a wafer to be polished before surface treatment according to an embodiment of the present invention. Figure 2 As shown, in step S100, the wafer to be polished includes a silicon substrate 1 and an epitaxial layer 2. The epitaxial layer 2 may include a metal layer 21 and an oxide layer 22. In one embodiment, an etching stop layer may be formed between the metal layer 21 and the oxide layer 22. In other embodiments, the epitaxial layer 2 may not include the metal layer 21 or may be a layer of other materials. The step 3 refers to a height variation area formed on the surface of the wafer to be polished due to the thickness difference between different material layers. This height variation may be caused by the growth of the epitaxial layer 2, the deposition of the metal layer 21 or other process steps, and usually results in the formation of an obvious step 3 structure on the wafer surface. The height and shape of the step 3 will affect the subsequent polishing process and the flatness and uniformity of the final product.

[0034] Figure 3 FIG. 2 shows a schematic structural diagram of forming a groove structure 31 at a step 3 according to an embodiment of the present invention. Figure 3 As shown, by etching, a groove structure 31 can be formed at the step 3. In one embodiment, the etching method can be any existing method that can form a groove structure 31 that meets the requirements at the step 3, such as wet etching, dry etching, plasma etching or laser etching.

[0035] In step S300, if Figure 4 As shown, the upper surface of the wafer is flat after CMP. If the wafer has a metal layer 21 and an oxide layer 22, then CMP removes part of the material of the oxide layer 22, and after CMP, there is a certain distance between the upper surface of the wafer and the metal layer 21.

[0036] See also Figure 3In one embodiment, the surface of the wafer to be polished also includes a reference plane 4 connected to the step 3. The height difference h between the bottom surface 311 of the groove structure 31 and the reference plane 4 ranges from 0μm to 0.2μm, for example, it can be 0μm, 0.05μm, 0.1μm, 0.15μm or 0.2μm, or any other value between 0μm and 0.2μm. By setting the height difference between the bottom surface 311 of the groove structure 31 and the reference plane 4 to be within the above range, as much material as possible from the raised portion of the step 3 can be removed. The reference plane 4 can be understood as a surface corresponding to the non-step area.

[0037] To ensure that the bottom surface 311 of the groove structure 31 is etched to the target depth, the etching process can select a one-time deep etching method or a multiple step etching method. One-time etching can simplify the process flow, while step etching helps to improve the accuracy and uniformity of the etching process by removing materials layer by layer, and reduce the stress and potential defects caused by the etching process. The choice of etching method depends on the specific process requirements and the control requirements for surface quality and etching depth accuracy.

[0038] In a specific embodiment, the etching depth of the step 3 is required to be 1 μm, and the bottom surface of the groove finally formed is required to be highly accurate to achieve the surface uniformity requirements after the CMP process. In this example, a multiple layered etching method is selected instead of a one-time deep etching to better control the sidewall structure 313 and the surface quality. The multiple layered etching method includes two etchings. The first etching controls the etching rate by plasma etching (RIE) to ensure that the bottom surface 311 of the groove structure 31 is uniform, and the etching depth is 0.5 μm. The second etching continues to control the etching rate by plasma etching (RIE) to ensure that the bottom surface 311 of the groove structure 31 is uniform, and the etching depth is 0.5 μm. The etching rates of the first etching and the second etching are both between 100 nm / min and 200 nm / min.

[0039] In actual products, the upper surfaces of the step area and the non-step area are not necessarily ideal flat surfaces, and may appear as curved surfaces or other irregular surfaces. Therefore, in order to obtain good flatness in the subsequent CMP process, the reference plane 4 can be understood as the ideal plane expected to be achieved after CMP. The purpose of the etching process is to approach this target reference plane 4 by reducing the height difference of the step 3, thereby optimizing the polishing efficiency and uniformity of CMP. In this way, the surface height difference of the step area and the non-step area can be effectively reduced, which helps to improve the overall flatness of the wafer surface and reduce the local unevenness generated during the polishing process.

[0040] The groove structure 31 can be understood as being formed by etching downward from the upper surface of the step 3. The size of the opening 312 of the groove is usually smaller than the overall size of the step 3, so that part of the step 3 material is retained after etching to form a wall-like sidewall structure 313. In the subsequent CMP process, the focus of polishing is on the sidewall structure 313 of the step 3 part. Since the material in other areas has been removed by etching, CMP only needs to grind the remaining sidewalls. This not only reduces the amount of material removed by CMP, but also optimizes the uniformity and efficiency of the polishing process, thereby improving the flatness and overall quality of the wafer surface.

[0041] The distance between the two opposite sidewall structures 313 of the same step 3 is the maximum cross-sectional width w1 of the groove structure 31. Reasonable design of the maximum cross-sectional width w1 helps to optimize the grinding pressure distribution, thereby improving the uniformity and smoothness of the wafer surface. In one embodiment, the ratio of the maximum cross-sectional width w1 of the groove structure 31 to the cross-sectional width w2 of the step 3 is in the range of 1:2 to 3:4, for example, it can be 1:2, 2.5:4 or 3:4, or any other ratio from 1:2 to 3:4. It can be understood that when the maximum cross-sectional width w1 of the groove structure 31 and the cross-sectional width w2 of the step 3 are proportionally set, the two are located on the same horizontal plane, so that the comparison of the width ratio can be ensured to be comparable. Setting the ratio range of the maximum cross-sectional width w1 of the groove structure 31 to the cross-sectional width w2 of the step 3 within the above-mentioned ratio range can ensure that the opening 312 of the groove structure 31 is appropriate, which can effectively guide the material removal in the subsequent CMP process, reduce the grinding pressure, and improve the flatness. Moreover, a reasonable width ratio helps maintain the stability of the sidewalls, prevents over-grinding or collapse during the polishing process, and ensures surface quality. This setting can also reduce material waste while ensuring polishing efficiency, optimize production costs, and ultimately improve product reliability and performance. In addition, etching problems caused by inaccurate mask alignment can be effectively avoided. By maintaining an appropriate width ratio, the groove structure 31 can still maintain its function even in the case of alignment deviations, ensuring that materials can be effectively removed during the CMP process, thereby reducing potential defect risks.

[0042] In some embodiments, the depth of the groove structure 31 ranges from 0.1 μm to 1 μm, for example, 0.1 μm, 0.2 μm, 0.5 μm, 0.8 μm, and 1 μm. An appropriate depth range can ensure that sufficient material is removed while avoiding excessive grinding and reducing the impact on other areas of the wafer, thereby improving polishing uniformity.

[0043] In one embodiment, the groove structure 31 has an opening 312, the width of the opening 312 is greater than the width w3 of the bottom of the groove structure 31, wherein the width of the opening 312 is the maximum cross-sectional width w1 of the groove structure 31, and the plane where the opening 312 is located is flush with the upper surface of the step 3. During the etching process, especially anisotropic etching or partially anisotropic etching, the etched sidewalls usually present a certain tilt angle, i.e., a "hollowing out" effect, and this process characteristic causes the width of the opening 312 to be greater than the width of the bottom.

[0044] In this embodiment, the design that the width of the opening 312 is larger than the bottom width helps to optimize the subsequent CMP process. Due to the inclined structure of the sidewall, the sidewall material can be smoothly ground off layer by layer during the CMP process to avoid the formation of overly steep edges, thereby improving the uniformity and controllability of polishing and reducing the generation of surface defects. In addition, the narrower groove bottom width helps to reduce the residue of the bottom material, which improves the cleanliness and quality of the surface after etching and reduces the pollution or unevenness that may be caused in subsequent processes. The wider opening 312 design can also provide sufficient process space to prevent the deformation or collapse of the sidewall structure 313 due to etching unevenness, thereby ensuring the stability of the groove structure 31, especially in the subsequent processing steps. The structural failure is not prone to occur. In addition, the larger opening 312 width also increases the tolerance in the mask alignment process. Even if there is a slight alignment deviation, it will not significantly affect the final effect of etching, thereby improving the stability and yield of the overall process.

[0045] In one embodiment, the groove structure 31 is in an inverted trapezoidal shape, and the sidewall angle of the groove structure 31 ranges from 30° to 60°. The sidewall angle of the groove structure 31 can be, for example, 30°, 40°, 50° or 60°, or any other value between 30° and 60°. The inverted trapezoidal groove design adopts a sidewall angle of 30° to 60°, so that the material can be removed smoothly layer by layer during the CMP process. The selection of this angle effectively prevents the sudden peeling or over-grinding of the material, thereby improving the uniformity and stability of the grinding process and avoiding the problem of over-polishing or under-polishing. At the same time, a moderate sidewall angle can reduce the formation of steep edges, thereby reducing stress concentration in the edge area during polishing, reducing the generation of surface defects, ensuring a smoother surface, and reducing the need for rework or defect repair in subsequent processes. In addition, the design of the inverted trapezoidal structure enhances the stability of the groove, avoids the collapse or deformation of the sidewall during etching or CMP, ensures the integrity and mechanical stability of the groove, and reduces the risk of structural failure. Due to the inclined design of the sidewalls, even if there is a slight alignment deviation during the etching process, the inverted trapezoidal structure can accommodate these errors and improve the tolerance of etching accuracy. At the same time, the larger sidewall angle range provides flexibility for the optimization of the etching process and can adapt to the needs of different materials and processes. Since the bottom of the groove is relatively narrow, this design also helps to reduce the residue of the bottom material during the etching process, thereby improving the surface cleanliness after etching and reducing the occurrence of contamination or unevenness.

[0046] In one embodiment, the sidewall of the groove structure 31 includes a plurality of steps 3 that are parallel to each other and have a height difference. The sidewall of the groove structure 31 is composed of a plurality of steps 3 with a height difference, and this layered design brings about many effects. First, the layer-by-layer structure can make the material removal process more gradual and controllable, thereby effectively reducing the phenomenon of over-grinding or under-grinding during grinding, and improving the consistency of the polishing effect. Secondly, this design helps to evenly distribute stress, reduce local stress concentration, enhance the stability of the sidewall, and avoid collapse or deformation during etching or CMP. In addition, the structure with a height difference can better adapt to different process requirements, improve processing accuracy, and ensure that the geometry of complex surfaces is maintained. By reducing stress concentration in the edge area, the design also effectively reduces the generation of surface defects during polishing, thereby improving the flatness and smoothness of the final product. At the same time, this structure improves the tolerance of mask alignment, so that slight deviations during alignment will not significantly affect the etching accuracy, thereby improving the stability and yield of the process. Finally, the layered sidewall design provides better material flow and distribution space for subsequent process processing, helping to reduce the possibility of residual material, improve surface cleanliness after etching, and reduce potential contamination risks.

[0047] In one embodiment, the bottom surface 311 of the groove structure 31 has a nanometer-scale surface roughness, which may be in the range of 10 nm to 300 nm, for example, 10 nm, 50 nm, 100 nm, 200 nm or 300 nm.

[0048] A variety of etching methods can be used to achieve a nanoscale surface roughness on the bottom surface 311 of the groove structure 31, for example, reactive ion etching technology and / or wet etching technology can be selected. In a specific embodiment, in the reactive ion etching technology, gases such as SF6, O2 or Cl2 can be used. When the etching gas is selected as SF6, the flow rate is set to 20sccm. When the etching gas is selected as O2, the flow rate is set to 10sccm. Among them, the etching power is 500W to ensure that there is enough energy for effective etching. The etching time is controlled at 60-120 seconds. In the wet etching technology, HF or KOH etching solution is used, for example, an HF etching solution with a concentration of 1% to 10% can be selected, and the processing time is 1-5 minutes. In this way, a bottom surface 311 with nanoscale surface roughness can be obtained.

[0049] By setting the surface roughness of the bottom surface 311 of the groove structure 31 to the nanometer level, the efficiency and effect of the subsequent CMP process can be significantly improved. The nanometer-level surface roughness helps to improve the cutting ability of the material during the grinding process, thereby achieving a smoother polishing effect and reducing the particles and defects generated during the polishing process. In addition, the fine surface roughness can improve the fluidity and distribution of the liquid polishing agent, ensuring that it evenly covers the entire surface, thereby improving the polishing uniformity and overall surface quality. This optimization not only improves the smoothness of the final product, but also reduces the rework rate caused by surface unevenness in the subsequent process, thereby improving production efficiency and yield rate.

[0050] In one embodiment, the step 3 is an epitaxial layer step 3 of a wafer.

[0051] In conventional technology, the oxide layer 22 is directly CMPed from 3um to the target thickness, with a removal amount greater than 2um. After CMP, the wafer full map uniformity (Nu Range) is greater than 500nm, which is poor uniformity. Figure 5 As shown, after the surface of the wafer to be polished is treated by the method of the embodiment of the present invention, the Nu Range obtained is from Significantly improved to It shows that the surface treatment method of the embodiment of the present invention greatly improves the surface uniformity. In addition, the thickness distribution of the oxide layer after CMP is more convergent, and the uniformity is further improved. This improvement not only reflects the effectiveness of the polishing process, but also provides a more uniform and stable foundation for subsequent processes, which helps to improve the final quality and performance of the product. The embodiment of the present invention also provides an application of the above-mentioned surface treatment method, which is applied to the manufacture of micro-electromechanical systems or integrated circuits.

[0052] The above are only some specific implementation methods of the present application. Any other improvements made based on the concept of the present application are deemed to be within the protection scope of the present application.

Claims

1. A method for surface treatment of a wafer, characterized in that: The steps include: Determining the step position on the surface of the wafer to be polished; Performing etching on the step to form a groove structure at the step; The etched wafer is subjected to chemical mechanical polishing.

2. The surface treatment method according to claim 1, characterized in that: The surface of the wafer to be polished also includes a reference surface connected to the step, and the height difference between the bottom surface of the groove structure and the reference surface ranges from 0 μm to 0.2 μm.

3. The surface treatment method according to claim 2, characterized in that: The ratio of the maximum cross-sectional width of the groove structure to the cross-sectional width of the step is in a range of 1:2 to 3:

4.

4. The surface treatment method according to claim 3, characterized in that: The depth of the groove structure ranges from 0.1 μm to 1 μm.

5. The surface treatment method according to any one of claims 1 to 4, characterized in that: The groove structure has an opening, the width of the opening is greater than the width of the bottom of the groove structure, and the plane where the opening is located is flush with the upper surface of the step.

6. The surface treatment method according to claim 5, characterized in that: The groove structure is in an inverted trapezoidal shape, and the side wall angle of the groove structure ranges from 30° to 60°.

7. The surface treatment method according to claim 5, characterized in that: The sidewall of the groove structure includes a plurality of steps which are parallel to each other and have height differences.

8. The surface treatment method according to claim 1, characterized in that: The bottom surface of the groove structure has a nanometer-scale surface roughness.

9. The surface treatment method according to claim 1, characterized in that: The step is an epitaxial layer step of the wafer.

10. An application of the surface treatment method according to any one of claims 1 to 9, characterized in that: Applied to the manufacture of micro-electromechanical systems or integrated circuits.

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