Thermal resistance testing method and device for semiconductor packaging structure

Abstract

The present disclosure relates to a thermal resistance testing method and device for a semiconductor packaging structure. The thermal resistance testing method includes: passing a measurement current through a chip to obtain an initial voltage drop on both sides of the chip, as well as the front initial shell temperature and the back initial shell temperature of the packaging shell; providing a target ambient temperature, and collecting the front target shell temperature and the back target shell temperature of the packaging shell and the target voltage drop on both sides of the chip; determining the series-parallel proportionality coefficient of the semiconductor packaging structure based on the initial voltage drop, the front initial shell temperature, the back initial shell temperature, the target voltage drop, the front target shell temperature and the back target shell temperature. The thermal resistance testing method also includes: obtaining a target heat flow through the chip; determining the series thermal resistance of the semiconductor packaging structure based on the front target shell temperature, the back target shell temperature and the target heat flow; determining the parallel thermal resistance of the semiconductor packaging structure according to the series thermal resistance and the series-parallel proportionality coefficient.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor packaging technology, and in particular to a method and device for testing thermal resistance of a semiconductor packaging structure. Background Art

[0002] With the development of semiconductor technology, electronic devices are moving towards miniaturization, light weight, high performance and multi-function. Due to the rapid increase in chip integration, the heat generated per unit area of ​​integrated circuits is getting bigger and bigger. In order to quickly dissipate the heat, higher requirements are placed on the heat dissipation performance of semiconductor packaging structures. Among them, whether the thermal resistance of semiconductor packaging structures can be effectively measured is also likely to affect the improvement of the heat dissipation performance of semiconductor packaging structures. Summary of the invention

[0003] Based on this, the embodiments of the present disclosure provide a method and device for testing the thermal resistance of a semiconductor packaging structure, which facilitates precise control of the packaging electrode thickness, electrical properties, and heat dissipation properties of the semiconductor packaging structure.

[0004] In order to achieve the above objectives, in a first aspect, some embodiments of the present disclosure provide a method for testing the thermal resistance of a semiconductor packaging structure. The semiconductor packaging structure includes a chip and a packaging shell covering the chip. The thermal resistance testing method includes the following steps.

[0005] A measurement current is passed through the chip to obtain the initial voltage drop on both sides of the chip, as well as the initial case temperature of the front side and the initial case temperature of the back side of the package case.

[0006] Provide the target ambient temperature and collect the target case temperature on the front and back of the package case as well as the target voltage drop on both sides of the chip.

[0007] The series-parallel proportionality coefficient of the semiconductor package structure is determined based on the initial voltage drop, the front initial shell temperature, the back initial shell temperature, the target voltage drop, the front target shell temperature and the back target shell temperature.

[0008] In some embodiments of the present disclosure, the thermal resistance testing method further includes the following steps.

[0009] Obtain the target heat flow through the chip.

[0010] The series thermal resistance of the semiconductor package structure is determined based on the front target case temperature, the back target case temperature, and the target heat flux.

[0011] The parallel thermal resistance of the semiconductor package structure is determined according to the series thermal resistance and the series-parallel proportionality coefficient.

[0012] In some embodiments of the present disclosure, determining the series-parallel proportional coefficient of the semiconductor packaging structure based on the initial voltage drop, the front initial shell temperature, the back initial shell temperature, the target voltage drop, the front target shell temperature and the back target shell temperature may include the following steps.

[0013] The calculation formula for the junction temperature of the chip at the target ambient temperature is determined based on the initial voltage drop, the front initial case temperature, the back initial case temperature, the target voltage drop, the front target case temperature and the back target case temperature.

[0014] The series-parallel proportional coefficient of the semiconductor packaging structure is determined according to the calculation formula of the junction temperature of the chip at the target ambient temperature.

[0015] In some embodiments of the present disclosure, the initial voltage drop, the front initial shell temperature, and the back initial shell temperature satisfy the following formula: ; Among them, V AK0 is the initial voltage drop, T h0 is the initial shell temperature on the front side, T c0 is the initial shell temperature at the back side, T vj0 is the initial junction temperature of the chip, k is the proportional coefficient of voltage changing with temperature, .

[0016] In some embodiments of the present disclosure, the target ambient temperature includes a first ambient temperature and a second ambient temperature. The target voltage drop at the first ambient temperature is the first target voltage drop, the junction temperature of the chip at the first ambient temperature is the first target junction temperature, the front target shell temperature of the package shell at the first ambient temperature is the front first target shell temperature, and the back target shell temperature of the package shell at the first ambient temperature is the back first target shell temperature. The target voltage drop at the second ambient temperature is the second target voltage drop, the junction temperature of the chip at the second ambient temperature is the second target junction temperature, the front target shell temperature of the package shell at the second ambient temperature is the front second target shell temperature, and the back target shell temperature of the package shell at the second ambient temperature is the back second target shell temperature.

[0017] Accordingly, the calculation formula for determining the junction temperature of the chip at the target ambient temperature based on the initial voltage drop, the front initial shell temperature, the back initial shell temperature, the target voltage drop, the front target shell temperature and the back target shell temperature includes: determining the calculation formula for the target voltage drop of the chip at the target ambient temperature is as follows: .

[0018] Among them, V AK1 is the first target voltage drop, T vj1 is the first target junction temperature, V AK0 is the initial voltage drop, T h0 is the initial shell temperature on the front side, T c0 is the initial shell temperature at the back, V AK2 is the second target voltage drop, Tvj2 is the second target junction temperature.

[0019] And, the calculation formula for determining the junction temperature of the chip at the target ambient temperature is as follows: .

[0020] Among them, T h1 is the first target shell temperature on the front side, T c1 is the first target shell temperature on the back side, T h2 is the second target shell temperature on the front side, T c2 is the second target shell temperature on the back side, and β is the series-parallel proportional coefficient of the semiconductor packaging structure.

[0021] In some other embodiments of the present disclosure, the target voltage drop when the semiconductor package structure is placed forward is the first target voltage drop, the junction temperature of the chip when the semiconductor package structure is placed forward is the first target junction temperature, the front target shell temperature of the package shell when the semiconductor package structure is placed forward is the front first target shell temperature, and the back target shell temperature of the package shell when the semiconductor package structure is placed forward is the back first target shell temperature. The target voltage drop when the semiconductor package structure is placed reversely is the second target voltage drop, the junction temperature of the chip when the semiconductor package structure is placed reversely is the second target junction temperature, the front target shell temperature of the package shell when the semiconductor package structure is placed reversely is the front second target shell temperature, and the back target shell temperature of the package shell when the semiconductor package structure is placed reversely is the back second target shell temperature.

[0022] Accordingly, the calculation formula for determining the junction temperature of the chip at the target ambient temperature based on the initial voltage drop, the front initial shell temperature, the back initial shell temperature, the target voltage drop, the front target shell temperature and the back target shell temperature includes:

[0023] The calculation formula to determine the target voltage drop of the chip at the target ambient temperature is as follows: .

[0024] Among them, V AK1 is the first target voltage drop, T vj1 is the first target junction temperature, V AK0 is the initial voltage drop, T h0 is the initial shell temperature on the front side, T c0 is the initial shell temperature at the back, V AK2 is the second target voltage drop, T vj2 is the second target junction temperature.

[0025] And, the calculation formula for determining the junction temperature of the chip at the target ambient temperature is as follows: .

[0026] Among them, T h1is the first target shell temperature on the front side, T c1 is the first target shell temperature on the back side, T h2 is the second target shell temperature on the front side, T c2 is the second target shell temperature on the back side, and β is the series-parallel proportional coefficient of the semiconductor packaging structure.

[0027] In some embodiments of the present disclosure, determining the series-parallel proportional coefficient of the semiconductor package structure according to the calculation formula of the junction temperature of the chip at the target ambient temperature includes:

[0028] The equations for the difference between the target voltage drop and the initial voltage drop are as follows: .

[0029] The equation group is solved according to the measured data of the initial voltage drop, the front initial shell temperature, the back initial shell temperature, the target voltage drop, the front target shell temperature and the back target shell temperature to determine the proportional coefficient and the series-parallel proportional coefficient.

[0030] In some embodiments of the present disclosure, the initial voltage drop and the target voltage drop are acquired based on a voltage acquisition card; the voltage acquisition accuracy of the voltage acquisition card is at least 0.1 mV.

[0031] In a second aspect, some embodiments of the present disclosure further provide a thermal resistance testing device for a semiconductor package structure, which can be used to implement the thermal resistance testing method for a semiconductor package structure described in any of the above embodiments. The thermal resistance testing device includes a power supply module, a temperature control module, a collection module, and a processing module.

[0032] The power supply module is used to supply a measuring current to the chip of the semiconductor packaging structure.

[0033] The temperature control module is used to provide at least two target ambient temperatures.

[0034] The acquisition module is used to collect the initial voltage drop on both sides of the chip after the measurement current is passed, the initial shell temperature of the front side and the initial shell temperature of the back side of the package shell, as well as the target shell temperature of the front side and the target shell temperature of the back side of the package shell at the target ambient temperature, and the target voltage drop on both sides of the chip.

[0035] The processing module is used to determine the series-parallel proportionality coefficient of the semiconductor packaging structure according to the initial voltage drop, the front initial shell temperature, the back initial shell temperature, the target voltage drop, the front target shell temperature and the back target shell temperature.

[0036] In some embodiments of the present disclosure, the acquisition module is further used to obtain a target heat flow through the chip. The processing module is further used to determine the series thermal resistance of the semiconductor package structure according to the front target shell temperature, the back target shell temperature and the target heat flow, and to determine the parallel thermal resistance of the semiconductor package structure according to the series thermal resistance and the series-parallel proportionality coefficient.

[0037] The embodiments of the present disclosure may or at least have the following advantages:

[0038] In the embodiment of the present disclosure, after the measurement current is passed through the chip, the initial voltage drop on both sides of the chip and the initial shell temperature of the front side and the initial shell temperature of the back side of the package shell can be obtained, and after the target ambient temperature is provided, the target shell temperature of the front side and the target shell temperature of the back side of the package shell under the target ambient temperature and the target voltage drop on both sides of the chip can be obtained. On this basis, the embodiment of the present disclosure can determine the series-parallel proportionality coefficient of the semiconductor package structure based on the aforementioned initial voltage drop, the initial shell temperature of the front side, the initial shell temperature of the back side, the target voltage drop, the target shell temperature of the front side and the target shell temperature of the back side.

[0039] Furthermore, after obtaining the target heat flow through the chip, the embodiment of the present disclosure can also determine the series thermal resistance of the semiconductor packaging structure based on the aforementioned front target shell temperature, back target shell temperature and target heat flow, and determine the parallel thermal resistance of the semiconductor packaging structure based on the series thermal resistance and the series-parallel proportional coefficient.

[0040] From the above, the thermal resistance testing method and device provided by the embodiments of the present disclosure can effectively measure the series-parallel proportionality coefficient and thermal resistance of the semiconductor packaging structure, especially the series-parallel proportionality coefficient and thermal resistance of the asymmetric structure power semiconductor device, thereby facilitating the precise control of the packaging electrode thickness of the semiconductor packaging structure and its electrical properties and heat dissipation performance.

[0041] The details of one or more embodiments of the present disclosure are set forth in the following drawings and description. Other features, objects, and advantages of the present disclosure will become apparent from the description, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0043] Figure 1 A schematic flow chart of a method for testing thermal resistance of a semiconductor package structure provided in some embodiments;

[0044] Figure 2 A schematic flow chart of another method for testing thermal resistance of a semiconductor package structure provided in some embodiments;

[0045] Figure 3 is a flow chart of step S300 in a method for testing thermal resistance of a semiconductor package structure provided in some embodiments;

[0046] Figure 4 A structural block diagram of a thermal resistance testing device for a semiconductor packaging structure provided in some embodiments;

[0047] Figure 5 A structural block diagram of another thermal resistance testing device for a semiconductor packaging structure provided in some embodiments.

[0048] Description of reference numerals:

[0049] 1-power supply module, 2-temperature control module, 3-acquisition module, 4-processing module, 31-temperature acquisition module, 32-voltage acquisition module, 33-heat flow acquisition module. DETAILED DESCRIPTION

[0050] In order to facilitate understanding of the present disclosure, the present disclosure will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present disclosure are shown in the drawings. However, the present disclosure can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present disclosure more thorough and comprehensive.

[0051] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. The terms used herein in the specification of the present disclosure are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure.

[0052] It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer or part discussed below can be represented as a second element, component, region, layer or part.

[0053] It should be understood that when an element is considered to be "connected" to another element, it can be directly connected to the other element, or connected to the other element through an intermediate element. In addition, the "connection" in the following embodiments should be understood as "electrical connection", "communication connection", etc. if there is transmission of electrical signals or data between the connected objects.

[0054] It should be understood that the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0055] In the related art, press-fit power semiconductor devices are usually designed as a symmetrical structure, that is, the chip is set in the center of the device, and the cathode electrode and the anode electrode are symmetrically arranged on both sides of the chip. In this way, after the chip generates heat, the heat can be dissipated along the upper and lower paths of the chip to ensure the heat dissipation requirements of the power semiconductor device. However, the power semiconductor device adopts a symmetrical structure, and it is difficult to further reduce the thermal resistance of the device and improve the current carrying capacity of the device. Based on this, the power semiconductor device adopts an asymmetric structure, which can effectively improve the heat transfer efficiency of the device electrode, reduce the device junction-shell thermal resistance, and make the chip junction temperature lower when the device is working, so as to improve the rated current carrying capacity of the device, thereby meeting the further heat dissipation requirements of the press-fit power semiconductor device.

[0056] Some embodiments of the present disclosure provide a thermal resistance testing method and a thermal resistance testing device for a semiconductor packaging structure, which can effectively measure the thermal resistance of a semiconductor packaging structure, especially the thermal resistance of an asymmetric power semiconductor device, so as to accurately control the packaging electrode thickness of the semiconductor packaging structure and its electrical properties and heat dissipation performance.

[0057] It can be understood that the semiconductor packaging structure generally includes a chip and a packaging shell covering the chip. The packaging shell includes, for example: a shell base with a cathode electrode, a shell cover with an anode electrode, and a shell sleeved around the chip and connecting the shell base and the shell cover. For the convenience of description, in some of the following examples, the outer surface of the shell cover away from the shell base is the front side of the packaging shell, and the outer surface of the shell base away from the shell cover is the back side of the packaging shell.

[0058] For example, when the semiconductor package structure adopts an asymmetric structure, the thickness of the anode electrode and the cathode electrode are different. Moreover, taking the case where the cathode electrode is located on the first side of the chip and the anode electrode is located on the second side of the chip as an example, if the thermal resistance on the first side of the chip is the first thermal resistance and the thermal resistance on the second side of the chip is the second thermal resistance, then the ratio of the series thermal resistance of the first thermal resistance and the second thermal resistance to their parallel thermal resistance is the series-parallel proportional coefficient of the semiconductor package structure. When the semiconductor package structure adopts an asymmetric structure, the series-parallel proportional coefficient is greater than 4.

[0059] See also Figure 1, and combined with the above content, it can be understood that the thermal resistance testing method of the semiconductor package structure provided by the embodiment of the present disclosure may include the following steps S100 to S500.

[0060] Step S100 , passing a measurement current through the chip to obtain an initial voltage drop on both sides of the chip, as well as an initial front shell temperature and an initial back shell temperature of the package shell.

[0061] Step S200 , providing a target ambient temperature, and collecting the front target shell temperature and the back target shell temperature of the package shell under the target ambient temperature, as well as the target voltage drop at both sides of the chip.

[0062] Step S300, determining a series-parallel proportionality coefficient of a semiconductor package structure based on an initial voltage drop, a front initial shell temperature, a back initial shell temperature, a target voltage drop, a front target shell temperature, and a back target shell temperature.

[0063] For further information, see Figure 2 In some embodiments of the present disclosure, the thermal resistance testing method also includes the following steps.

[0064] Step S400, obtaining a target heat flow through the chip.

[0065] Step S500 , determining the series thermal resistance of the semiconductor package structure based on the front target shell temperature, the back target shell temperature and the target heat flux.

[0066] Step S600: determining the parallel thermal resistance of the semiconductor package structure according to the series thermal resistance and the series-parallel proportionality coefficient.

[0067] See also Figure 3 In some embodiments of the present disclosure, step S300 determines the series-parallel proportional coefficient of the semiconductor packaging structure based on the initial voltage drop, the front initial shell temperature, the back initial shell temperature, the target voltage drop, the front target shell temperature and the back target shell temperature, which may include the following steps S310 and S320.

[0068] Step S310, determining a calculation formula for the junction temperature of the chip at a target ambient temperature based on the initial voltage drop, the front initial shell temperature, the back initial shell temperature, the target voltage drop, the front target shell temperature and the back target shell temperature.

[0069] Step S320, determining the series-parallel proportionality coefficient of the semiconductor package structure according to a calculation formula for the junction temperature of the chip at the target ambient temperature.

[0070] It should be added that, optionally, the initial voltage drop and target voltage drop of the above chip can be expressed as the positive cathode forward voltage drop V AK , Gate cathode forward voltage drop V GK Or any voltage drop such as the gate cathode reverse avalanche breakdown voltage can be used as a temperature-sensitive parameter.

[0071] In the embodiment of the present disclosure, after the measurement current is passed through the chip, the initial voltage drop on both sides of the chip and the initial shell temperature of the front and back of the package shell can be obtained, and after the target ambient temperature is provided, the target shell temperature of the front and back of the package shell at the target ambient temperature and the target voltage drop on both sides of the chip can be obtained. On this basis, the embodiment of the present disclosure can determine the junction temperature calculation formula of the chip at the target ambient temperature based on the aforementioned initial voltage drop, the initial shell temperature of the front, the initial shell temperature of the back, the target voltage drop, the target shell temperature of the front and the target shell temperature of the back, and the series-parallel proportionality coefficient of the semiconductor package structure according to the junction temperature calculation formula of the chip at the target ambient temperature.

[0072] Furthermore, after obtaining the target heat flow through the chip, the embodiment of the present disclosure can also determine the series thermal resistance of the semiconductor packaging structure based on the aforementioned front target shell temperature, back target shell temperature and target heat flow, and determine the parallel thermal resistance of the semiconductor packaging structure based on the series thermal resistance and the series-parallel proportional coefficient.

[0073] From the above, the thermal resistance testing method and device provided by the embodiments of the present disclosure can effectively measure the series-parallel proportionality coefficient and thermal resistance of the semiconductor packaging structure, especially the series-parallel proportionality coefficient and thermal resistance of the asymmetric structure power semiconductor device, thereby facilitating the precise control of the packaging electrode thickness of the semiconductor packaging structure and its electrical properties and heat dissipation performance.

[0074] In some embodiments of the present disclosure, the value range of the measurement current passed into the chip in step S100 includes 100mA~500mA.

[0075] Optionally, the measurement current may be 100 mA, 150 mA, 200 mA, 250 mA, 300 mA, 350 mA, 400 mA, 450 mA or 500 mA.

[0076] In the disclosed embodiment, the measurement current is controlled within the range of 100mA to 500mA, and the aforementioned thermal resistance test method can be completed under the premise of ensuring that the chip does not actually generate heat, so as to simplify the calculation and processing process of the measurement data and effectively improve the accuracy of the thermal resistance measurement.

[0077] In addition, in some embodiments of the present disclosure, the measurement current passed into the chip in step S100 can make the chip operate in a saturation state.

[0078] In some embodiments of the present disclosure, the initial voltage drop on both sides of the chip in step S100, as well as the initial shell temperature of the front side and the initial shell temperature of the back side of the package shell are measured at room temperature.

[0079] Here, normal temperature refers to room temperature of 20°C to 25°C.

[0080] In some embodiments of the present disclosure, the initial voltage drop and the target voltage drop are acquired based on a voltage acquisition card.

[0081] For example, the voltage acquisition accuracy of the voltage acquisition card is at least 0.1 mV.

[0082] In the disclosed embodiment, by selecting a voltage acquisition card with higher acquisition accuracy, after accurately measuring the voltage drop on both sides of the chip, the chip's saturation voltage drop can be used as its temperature-sensitive electrical parameter to obtain the chip junction temperature.

[0083] It should be noted that the chip junction temperature refers to the highest actual temperature of the chip in the semiconductor packaging structure.

[0084] In some embodiments of the present disclosure, the front target shell temperature and the back target shell temperature of the package shell at the target ambient temperature in step S200, the target voltage drop on both sides of the chip, and the target heat flow in step S400 are all measured based on the steady-state heat flow method.

[0085] Here, the steady-state heat flow method means: firstly, the semiconductor package structure is heated by a temperature control device (such as a heat source), and after a stable ambient temperature (i.e., temperature distribution) is formed inside the semiconductor package structure, a measurement current is then passed through the chip for measurement.

[0086] For example, the target ambient temperature provided in step S200 may be one or at least two.

[0087] In some embodiments of the present disclosure, the initial voltage drop, the front initial shell temperature, and the back initial shell temperature obtained in step S100 may satisfy the following formula:

[0088] ;

[0089] Among them, V AK0 is the initial voltage drop, T h0 is the initial shell temperature on the front side, T c0 is the initial shell temperature at the back side, T vj0 is the initial junction temperature of the chip, k is the proportional coefficient of voltage changing with temperature, .

[0090] In some embodiments of the present disclosure, the target ambient temperature provided in step S200 includes a first ambient temperature and a second ambient temperature. For example, the first ambient temperature includes but is not limited to 80° C., and the second ambient temperature includes but is not limited to 120° C. It is understood that when different target ambient temperatures are provided, the placement of the semiconductor package structure remains fixed, for example, it is always placed in the forward direction, or it is always placed in the reverse direction.

[0091] Accordingly, the front target shell temperature and the back target shell temperature of the package shell at different target ambient temperatures collected in step S200, as well as the target voltage drop on both sides of the chip, include: the first front target shell temperature, the first back target shell temperature, and the first target voltage drop on both sides of the chip at the first ambient temperature, and the second front target shell temperature, the second back target shell temperature, and the second target voltage drop on both sides of the chip at the second ambient temperature. That is, the target voltage drop at the first ambient temperature is the first target voltage drop, the front target shell temperature of the package shell at the first ambient temperature is the first front target shell temperature, and the back target shell temperature of the package shell at the first ambient temperature is the first back target shell temperature; the target voltage drop at the second ambient temperature is the second target voltage drop, the front target shell temperature of the package shell at the second ambient temperature is the second front target shell temperature, and the back target shell temperature of the package shell at the second ambient temperature is the second back target shell temperature.

[0092] Accordingly, the junction temperature of the chip at the first ambient temperature is the first target junction temperature, and the junction temperature of the chip at the second ambient temperature is the second target junction temperature. In step S310, based on the initial voltage drop, the front initial shell temperature, the back initial shell temperature, the target voltage drop, the front target shell temperature, and the back target shell temperature, a calculation formula for the junction temperature of the chip at the target ambient temperature is determined, which may include the following steps S311 and S312.

[0093] Step S311, the calculation formula for determining the target voltage drop of the chip at the target ambient temperature is as follows: ;

[0094] Among them, V AK1 is the first target voltage drop, T vj1 is the first target junction temperature, V AK0 is the initial voltage drop, T h0 is the initial shell temperature on the front side, T c0 is the initial shell temperature at the back, V AK2 is the second target voltage drop, T vj2 is the second target junction temperature.

[0095] Step S312, determining the junction temperature of the chip at the target ambient temperature using the following calculation formula: ;

[0096] Among them, T h1 is the first target shell temperature on the front side, T c1 is the first target shell temperature on the back side, T h2 is the second target shell temperature on the front side, T c2 is the second target shell temperature on the back side, and β is the series-parallel proportional coefficient of the semiconductor packaging structure.

[0097] In some other embodiments of the present disclosure, the target ambient temperature provided in step S200 is one, for example, 120°C. The acquisition of the front target shell temperature and the back target shell temperature of the package shell at the target ambient temperature, as well as the target voltage drop on both sides of the chip in step S200, can be performed as follows: acquiring at least two sets of data corresponding to the forward placement of the semiconductor package structure and the reverse placement of the semiconductor package structure at the same target ambient temperature. For example, the target voltage drop when the semiconductor package structure is placed forward is the first target voltage drop, the junction temperature of the chip when the semiconductor package structure is placed forward is the first target junction temperature, the front target shell temperature of the package shell when the semiconductor package structure is placed forward is the front first target shell temperature, and the back target shell temperature of the package shell when the semiconductor package structure is placed forward is the back first target shell temperature; the target voltage drop when the semiconductor package structure is placed reversely is the second target voltage drop, the junction temperature of the chip when the semiconductor package structure is placed reversely is the second target junction temperature, the front target shell temperature of the package shell when the semiconductor package structure is placed reversely is the front second target shell temperature, and the back target shell temperature of the package shell when the semiconductor package structure is placed reversely is the back second target shell temperature.

[0098] Accordingly, step S310 determines the calculation formula for the junction temperature of the chip at the target ambient temperature based on the initial voltage drop, the front initial shell temperature, the back initial shell temperature, the target voltage drop, the front target shell temperature and the back target shell temperature, which may include the following steps S311' and S312'.

[0099] Step S311', the calculation formula for determining the target voltage drop of the chip at the target ambient temperature is as follows: ;

[0100] Among them, V AK1 is the first target voltage drop, T vj1 is the first target junction temperature, V AK0 is the initial voltage drop, T h0 is the initial shell temperature on the front side, T c0 is the initial shell temperature at the back, V AK2 is the second target voltage drop, T vj2 is the second target junction temperature.

[0101] Step S312', determining the junction temperature of the chip at the target ambient temperature using the following calculation formula: ;

[0102] Among them, T h1 is the first target shell temperature on the front side, T c1 is the first target shell temperature on the back side, T h2 is the second target shell temperature on the front side, T c2 is the second target shell temperature on the back side, and β is the series-parallel proportional coefficient of the semiconductor packaging structure.

[0103] In specific implementation, if the semiconductor package structure is placed forward, the heat flow flows from the anode to the cathode. Assuming that the chip is closer to the anode, the chip is closer to the heat source and the junction temperature of the chip is higher. If the semiconductor package structure is placed reversely, the heat flow flows from the cathode to the anode, the chip is closer to the cold source, and the junction temperature of the chip is lower. It can be seen that when the semiconductor package structure (especially the semiconductor package structure with the chip offset) is placed forward and reverse, even at the same ambient temperature, there will be differences in the aforementioned data that can be sampled by the two, and the size of the difference can reflect the size of the series-parallel proportional coefficient of the semiconductor package structure.

[0104] From the above, the calculation formulas for the voltage drop and junction temperature of the chip at the target ambient temperature provided by the embodiments of the present disclosure can be obtained by solving the simultaneous equations based on the difference between at least two sets of sampled data.

[0105] Based on the above embodiments, in some embodiments of the present disclosure, determining the series-parallel proportional coefficient of the semiconductor package structure according to the calculation formula of the junction temperature of the chip at the target ambient temperature in step S320 may include the following steps S321 and S322.

[0106] Step S321, the equation group of the difference between the target voltage drop and the initial voltage drop is as follows: .

[0107] Step S322, solving the equation group according to the measurement data of the initial voltage drop, the front initial shell temperature, the back initial shell temperature, the target voltage drop, the front target shell temperature and the back target shell temperature, and determining the proportionality coefficient k and the series-parallel proportionality coefficient β.

[0108] It is worth mentioning that in some embodiments of the present disclosure, the series thermal resistance of the semiconductor package structure is determined based on the front target shell temperature, the back target shell temperature and the target heat flow in step S500, which can be expressed as: the series thermal resistance of the semiconductor package structure is determined by the ratio of the difference between the front target shell temperature and the back target shell temperature to the corresponding target heat flow.

[0109] Exemplarily, the target heat flow through the chip in step S400 may be obtained by: after the semiconductor package structure is temperature-controlled by a temperature control device (such as a heat source or a heating and cooling system) and the semiconductor package structure reaches thermal equilibrium, the first heat flow P flowing through the anode side of the chip is obtained. A1 and a second heat flux P flowing through the cathode side of the chip K1 ; Among them, the first heat flow P A1 The second heat flux P can be obtained by calculating the ratio of the temperature difference between the chip contact interface on the anode side of the chip and the anode contact interface to the corresponding thermal resistance. K1It can be obtained by calculating the ratio of the temperature difference between the chip contact interface and the cathode contact interface on the cathode side of the chip to the corresponding thermal resistance.

[0110] Accordingly, the series thermal resistance of the semiconductor package structure ; Where T is the temperature difference between the two sides of the chip.

[0111] Optionally, based on the number of target ambient temperatures being multiple, the series thermal resistance corresponding to each target ambient temperature may be obtained respectively.

[0112] Accordingly, in some embodiments of the present disclosure, determining the parallel thermal resistance of the semiconductor package structure according to the series thermal resistance and the series-parallel proportionality coefficient in step S600 can be expressed as: determining the parallel thermal resistance of the semiconductor package structure by the ratio of the series thermal resistance to the series-parallel proportionality coefficient.

[0113] For example, the parallel thermal resistance ; Among them, R s is the series thermal resistance, and β is the series-parallel connection coefficient.

[0114] For example, the anode side thermal resistance of the chip .

[0115] Thermal resistance of the cathode side of the chip .

[0116] It should be understood that although Figure 1 and Figure 2 The steps in the flowchart are shown in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Moreover, Figure 1 and Figure 2 At least part of the steps may include multiple steps or multiple stages. These steps or stages are not necessarily performed at the same time, but can be performed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed in turn or alternately with other steps or at least part of the steps or stages in other steps.

[0117] In a second aspect, some embodiments of the present disclosure further provide a thermal resistance testing device for a semiconductor package structure, which can be used to implement the thermal resistance testing method for a semiconductor package structure described in any of the above embodiments. The thermal resistance testing device also has the technical advantages of the above thermal resistance testing method. The embodiments of the present disclosure will not elaborate on this.

[0118] See also Figure 4 The thermal resistance testing device includes a power supply module 1, a temperature control module 2, a collection module 3 and a processing module 4.

[0119] For example, the power supply module 1 is used to supply a measurement current to a chip of a semiconductor package structure. The power supply module 1 is, for example, a controllable power supply circuit.

[0120] In some examples, the value range of the measured current includes 100 mA to 500 mA. The measured current may be, for example, 100 mA, 150 mA, 200 mA, 250 mA, 300 mA, 350 mA, 400 mA, 450 mA, or 500 mA.

[0121] In some examples, measuring the current may cause the chip to operate in a saturation state.

[0122] Illustratively, the temperature control module 2 is used to provide one or more target ambient temperatures.

[0123] In some examples, the temperature control module 2 includes, but is not limited to, a heat source.

[0124] In some examples, the temperature control module 2 can provide two target ambient temperatures, namely, a first ambient temperature and a second ambient temperature. Optionally, the first ambient temperature includes but is not limited to 80°C, and the second ambient temperature includes but is not limited to 120°C.

[0125] For example, the acquisition module 3 is used to collect the initial voltage drop on both sides of the chip after the measurement current is passed, the front initial shell temperature and the back initial shell temperature of the packaging shell, as well as the front target shell temperature and the back target shell temperature of the packaging shell at the target ambient temperature, and the target voltage drop on both sides of the chip.

[0126] As a further example, the acquisition module 3 is also used to acquire the target heat flow flowing through the chip.

[0127] In some embodiments of the present disclosure, please refer to Figure 5 The acquisition module 3 includes, for example, a temperature acquisition module 31, a voltage acquisition module 32, and a heat flow acquisition module 33. The temperature acquisition module 31 is used to acquire the front initial shell temperature, the back initial shell temperature, the front target shell temperature, and the back target shell temperature. The voltage acquisition module 32 is used to acquire the initial voltage drop and the target voltage drop. The heat flow acquisition module 33 is used to acquire the target heat flow flowing through the chip at the target ambient temperature.

[0128] Optionally, the temperature acquisition module 31 includes but is not limited to a temperature sensor. There may be multiple temperature acquisition modules 31, which can be respectively arranged on the front side of the package shell, the back side of the package shell and the surrounding environment of the chip.

[0129] Optionally, the voltage acquisition module 32 includes a voltage acquisition card.

[0130] Optionally, the voltage acquisition accuracy of the voltage acquisition card is at least 0.1 mV.

[0131] Optionally, the heat flow acquisition module 33 may be composed of a temperature sensor and a preset calculation module.

[0132] For example, the processing module 4 is used to determine the series-parallel proportionality coefficient of the semiconductor package structure according to the initial voltage drop, the front initial shell temperature, the back initial shell temperature, the target voltage drop, the front target shell temperature and the back target shell temperature.

[0133] As a further example, the processing module 4 is also used to determine the series thermal resistance of the semiconductor package structure according to the front target shell temperature, the back target shell temperature and the target heat flow, and to determine the parallel thermal resistance of the semiconductor package structure according to the series thermal resistance and the series-parallel proportionality coefficient.

[0134] In some embodiments, the processing module 4 may first determine the junction temperature calculation formula of the chip at the target ambient temperature according to the initial voltage drop, the front initial shell temperature, the back initial shell temperature, the target voltage drop, the front target shell temperature and the back target shell temperature, and then determine the series-parallel proportional coefficient of the semiconductor package structure according to the junction temperature calculation formula of the chip at the target ambient temperature. The processing process of the processing module 4 may be performed with reference to the relevant steps in the thermal resistance test method of the aforementioned embodiment, and will not be described in detail here.

[0135] In the thermal resistance test device provided in some of the above embodiments, the processing module 4 can be used to represent a computer-related entity, hardware, firmware, a combination of hardware and software, software, or software in execution. For example, the processing module 4 can be, but is not limited to: a process running on a processor, a processor, an object, an executable file, an execution thread, a program, and / or a computer. For example, the processing module 4 can be executed by various computer-readable media having various data structures stored thereon.

[0136] In addition, in the above embodiments provided in the present disclosure, it should be understood that the disclosed "modules" can be implemented in other ways. For example, the modules described above are merely schematic. For example, the division of modules is only a division of logical functions, and there may be other division methods in actual implementation, such as multiple modules can be combined or integrated into another module, or some features can be ignored or not executed. The connection between each other described can be through some interfaces, indirect coupling or communication connection of modules, which can be electrical, mechanical or other forms. The modules described separately may or may not be physically separated. Some or all of the modules can be selected according to actual needs to achieve the purpose of the embodiment scheme of the present disclosure.

[0137] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features of the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0138] The above-described embodiments only express several implementation methods of the present disclosure, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present disclosure, and these all belong to the protection scope of the present disclosure. Therefore, the protection scope of the patent of the present disclosure shall be subject to the attached claims.

Claims

1. A method for testing thermal resistance of a semiconductor packaging structure, characterized in that: The semiconductor packaging structure comprises a chip and a packaging shell covering the chip; The thermal resistance test method comprises: Passing a measurement current through the chip to obtain an initial voltage drop at two sides of the chip, and an initial shell temperature of the front side and the initial shell temperature of the back side of the package shell; Providing a target ambient temperature, and collecting a target shell temperature on the front side and a target shell temperature on the back side of the package shell and a target voltage drop on both sides of the chip; Determine a calculation formula for the junction temperature of the chip at the target ambient temperature based on the initial voltage drop, the front initial shell temperature, the back initial shell temperature, the target voltage drop, the front target shell temperature, and the back target shell temperature; Determining the series-parallel proportional coefficient of the semiconductor package structure according to a calculation formula for the junction temperature of the chip at the target ambient temperature includes: The equations for combining the target voltage drop and the initial voltage drop are as follows: ; Among them, V AK0 is the initial voltage drop, T h0 is the initial shell temperature of the front side, T c0 is the initial shell temperature of the back side, k is the proportional coefficient of voltage changing with temperature, V AK1 is the first target voltage drop, V AK2 is the second target voltage drop, T h1 is the first target shell temperature on the front side, T c1 is the first target shell temperature on the back side, T h2 is the second target shell temperature on the front side, T c2 is the second target shell temperature on the back side, and β is the series-parallel proportional coefficient of the semiconductor packaging structure; Solving the equation group according to the measurement data of the initial voltage drop, the front initial shell temperature, the back initial shell temperature, the target voltage drop, the front target shell temperature and the back target shell temperature to determine the proportional coefficient and the series-parallel proportional coefficient; obtaining a target heat flow through the chip; Determining a series thermal resistance of the semiconductor package structure based on the front target shell temperature, the back target shell temperature, and the target heat flux; The parallel thermal resistance of the semiconductor package structure is determined according to the series thermal resistance and the series-parallel proportionality coefficient.

2. The thermal resistance testing method of a semiconductor package structure according to claim 1, characterized in that: The initial voltage drop, the front initial shell temperature, and the back initial shell temperature satisfy the following formula: ; Among them, V AK0 is the initial voltage drop, T h0 is the initial shell temperature of the front side, T c0 is the initial shell temperature of the back side, T vj0 is the initial junction temperature of the chip, k is the proportional coefficient of voltage changing with temperature, .

3. The thermal resistance testing method of a semiconductor package structure according to claim 2, wherein: The target ambient temperature includes a first ambient temperature and a second ambient temperature; the target voltage drop at the first ambient temperature is a first target voltage drop, the junction temperature of the chip at the first ambient temperature is a first target junction temperature, the front target shell temperature of the package shell at the first ambient temperature is a front first target shell temperature, and the back target shell temperature of the package shell at the first ambient temperature is a back first target shell temperature; The target voltage drop at the second ambient temperature is a second target voltage drop, the junction temperature of the chip at the second ambient temperature is a second target junction temperature, the front target shell temperature of the package shell at the second ambient temperature is a front second target shell temperature, and the back target shell temperature of the package shell at the second ambient temperature is a back second target shell temperature; The calculation formula for determining the junction temperature of the chip at the target ambient temperature based on the initial voltage drop, the front initial shell temperature, the back initial shell temperature, the target voltage drop, the front target shell temperature, and the back target shell temperature includes: The calculation formula for determining the target voltage drop of the chip at the target ambient temperature is as follows: ； Among them, V AK1 For the first target voltage drop, T vj1 is the first target junction temperature, V AK0 is the initial voltage drop, T h0 is the initial shell temperature of the front side, T c0 is the initial shell temperature of the back side, V AK2 For the second target voltage drop, T vj2 is the second target junction temperature; And, the calculation formula for determining the junction temperature of the chip at the target ambient temperature is as follows: ； Among them, T h1 is the first target shell temperature of the front side, T c1 is the first target shell temperature on the back side, T h2 is the second target shell temperature of the front side, T c2 is the second target shell temperature of the back side, and β is the series-parallel proportional coefficient of the semiconductor packaging structure.

4. The thermal resistance testing method of a semiconductor package structure according to claim 2, wherein: The target voltage drop when the semiconductor package structure is placed forward is a first target voltage drop, the junction temperature of the chip when the semiconductor package structure is placed forward is a first target junction temperature, the front target shell temperature of the package shell when the semiconductor package structure is placed forward is a front first target shell temperature, and the back target shell temperature of the package shell when the semiconductor package structure is placed forward is a back first target shell temperature; The target voltage drop when the semiconductor package structure is placed in reverse is the second target voltage drop, the junction temperature of the chip when the semiconductor package structure is placed in reverse is the second target junction temperature, the front target shell temperature of the package shell when the semiconductor package structure is placed in reverse is the front second target shell temperature, and the back target shell temperature of the package shell when the semiconductor package structure is placed in reverse is the back second target shell temperature; The calculation formula for determining the junction temperature of the chip at the target ambient temperature based on the initial voltage drop, the front initial shell temperature, the back initial shell temperature, the target voltage drop, the front target shell temperature, and the back target shell temperature includes: The calculation formula for determining the target voltage drop of the chip at the target ambient temperature is as follows: ； Among them, V AK1 For the first target voltage drop, T vj1 is the first target junction temperature, V AK0 is the initial voltage drop, T h0 is the initial shell temperature of the front side, T c0 is the initial shell temperature of the back side, V AK2 For the second target voltage drop, T vj2 is the second target junction temperature; And, the calculation formula for determining the junction temperature of the chip at the target ambient temperature is as follows: ； Among them, T h1 is the first target shell temperature of the front side, T c1 is the first target shell temperature on the back side, T h2 is the second target shell temperature of the front side, T c2 is the second target shell temperature of the back side, and β is the series-parallel proportional coefficient of the semiconductor packaging structure.

5. The thermal resistance testing method of a semiconductor package structure according to claim 1, wherein: The determining of the series thermal resistance of the semiconductor package structure based on the front target shell temperature, the back target shell temperature and the target heat flow comprises: The series thermal resistance of the semiconductor package structure is determined by the ratio of the difference between the front target shell temperature and the back target shell temperature to the corresponding target heat flow.

6. The thermal resistance testing method of a semiconductor package structure according to claim 1, wherein: The determining the parallel thermal resistance of the semiconductor package structure according to the series thermal resistance and the series-parallel proportionality coefficient comprises: The parallel thermal resistance of the semiconductor packaging structure is determined by the ratio of the series thermal resistance to the series-parallel proportionality coefficient.

7. The thermal resistance testing method of a semiconductor package structure according to claim 1, wherein: The initial voltage drop and the target voltage drop are acquired based on a voltage acquisition card; the voltage acquisition accuracy of the voltage acquisition card is at least 0.1 mV.

8. The thermal resistance testing method of a semiconductor package structure according to claim 1, wherein: The measurement current has a value range of 100mA to 500mA.

9. The thermal resistance testing method of a semiconductor package structure according to claim 1, wherein: The front target shell temperature, the back target shell temperature, the target voltage drop at both sides of the chip, and the target heat flow are all measured and obtained based on a steady-state heat flow method.

10. A thermal resistance testing device for a semiconductor packaging structure, characterized in that: The semiconductor packaging structure comprises a chip and a packaging shell covering the chip; The thermal resistance testing device comprises: A power supply module, used for supplying a measurement current to a chip of a semiconductor packaging structure; A temperature control module, used to provide a target ambient temperature; An acquisition module is used to: acquire an initial voltage drop on both sides of the chip after the measurement current is passed, an initial front shell temperature and an initial back shell temperature of the package shell, a target front shell temperature and a target back shell temperature of the package shell at the target ambient temperature, a target voltage drop on both sides of the chip, and acquire a target heat flow flowing through the chip; Processing modules for: Determine a calculation formula for the junction temperature of the chip at the target ambient temperature according to the initial voltage drop, the front initial shell temperature, the back initial shell temperature, the target voltage drop, the front target shell temperature, and the back target shell temperature; The series-parallel proportional coefficient of the semiconductor package structure is determined according to the calculation formula of the junction temperature of the chip at the target ambient temperature, including: the equation group of the difference between the target voltage drop and the initial voltage drop is combined as follows: ； Among them, V AK0 is the initial voltage drop, T h0 is the initial shell temperature of the front side, T c0 is the initial shell temperature of the back side, k is the proportional coefficient of voltage changing with temperature, V AK1 is the first target voltage drop, V AK2 is the second target voltage drop, T h1 is the first target shell temperature on the front side, T c1 is the first target shell temperature on the back side, T h2 is the second target shell temperature on the front side, T c2 is the second target shell temperature on the back side, and β is the series-parallel proportional coefficient of the semiconductor package structure; solving the equation group according to the measurement data of the initial voltage drop, the front initial shell temperature, the back initial shell temperature, the target voltage drop, the front target shell temperature and the back target shell temperature to determine the proportional coefficient and the series-parallel proportional coefficient; Determining a series thermal resistance of the semiconductor package structure according to the front target shell temperature, the back target shell temperature, and the target heat flux; And, the parallel thermal resistance of the semiconductor package structure is determined according to the series thermal resistance and the series-parallel proportionality coefficient.

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