Chip testing method, device, electronic device and readable storage medium

Abstract

The present application discloses a chip testing method, device, electronic device and readable storage medium, and relates to the field of electronic chip technology. The method first enables the chip to be tested to run a test program at an initial frequency, thereby obtaining a first running result and a first running duration, and determining a first level of the chip to be tested based on the first running result; determining a first preset time range based on the first level; and determining that the first running result of the chip to be tested is abnormal when it is detected that the first running duration exceeds the first preset time range. When it is detected that the first running duration is within the first preset time range and the first level is greater than the preset level, the chip to be tested runs the test program at a limit frequency, obtains a second running result, and thereby determines a second level of the chip to be tested based on the second running result. The present application tests the chip, grades the chip, and verifies the chip grading, thereby reducing the risk of chip grading errors.

Description

Technical Field

[0001] The present application relates to the technical field of electronic chips, and in particular to a chip testing method, device, electronic device and readable storage medium. Background Art

[0002] After the production of electronic chips is completed, the chips need to be functionally tested. However, due to defects in the manufacturing process, chips manufactured by the same process may have the same functions but different performances, and chips with different performances have different application scenarios. Therefore, it is necessary not only to test whether the chip is qualified, but also to grade the chip performance if the chip is qualified. However, in the chip testing method of the related art, chip grading errors are prone to occur. Summary of the invention

[0003] The present application aims to solve at least one of the technical problems existing in the prior art. To this end, the present application proposes a chip testing method, device, electronic device and readable storage medium, which can test the chip, classify the chip, and verify the classification of the chip, thereby reducing the risk of chip classification errors.

[0004] According to the first aspect of the present application, a chip testing method includes:

[0005] Sending a test program to the chip under test, setting the operating frequency of the chip under test to an initial frequency, and controlling the chip under test to run the test program at the initial frequency;

[0006] Obtaining a first running result and a first running time of the test program when the chip under test runs the test program at the initial frequency;

[0007] Determine a first level of the chip under test based on the first operation result;

[0008] determining a first preset time range based on the first level;

[0009] Performing detection and processing on the first running time based on the first preset time range;

[0010] When it is detected that the first operation time exceeds the first preset time range, determining that the first operation result of the chip to be tested is abnormal, and generating a first abnormality alarm;

[0011] When it is detected that the first running time is within the first preset time range and the first level is greater than a preset level, setting the operating frequency of the chip under test to a limit frequency, and controlling the chip under test to run the test program at the limit frequency;

[0012] Obtain a second running result of the chip under test running the test program at the limit frequency;

[0013] A second grade of the chip under test is determined based on the second operation result.

[0014] According to the chip testing method of the embodiment of the present application, at least the following beneficial effects are achieved: the chip testing method of the embodiment of the present application firstly makes the chip to be tested run the test program at the initial frequency, thereby obtaining the first running result and the first running time, and determining the first level of the chip to be tested based on the first running result; determining the first preset time range based on the first level; in the case where it is detected that the first running time exceeds the first preset time range, it indicates that the test process of the chip to be tested is abnormal, and the chip classification is inaccurate, so the first running result of the chip to be tested is determined to be abnormal, and a first abnormal alarm is generated. When it is detected that the first running time is within the first preset time range and the first level is greater than the preset level, the chip to be tested runs the test program at the limit frequency, obtains the second running result, and thus determines the second level of the chip to be tested based on the second running result. In this way, when it is determined that the classification of the first level is correct, the second running result characterizes the performance of the chip to be tested at the limit frequency, and can further determine a more refined classification of the chip to be tested. In this way, the present application tests the chip, and grades the chip, and verifies the classification of the chip based on the first running time, reduces the risk of chip classification errors, and makes the chip classification more refined. In addition, the present application performs testing according to the initial frequency and the limit frequency. For chips whose first level is lower than the preset level, there is no need to perform high-frequency testing at the limit frequency. Only chips whose first level is higher than the preset level are tested at the limit frequency, thereby improving the test efficiency.

[0015] According to some embodiments of the first aspect of the present application, after determining the second level of the chip under test based on the second operation result, the method further includes:

[0016] Obtaining a second running time of the test program executed by the chip under test at the limit frequency;

[0017] a second preset time range determined based on the second level;

[0018] Performing detection processing on the second running time based on the second preset time range;

[0019] When it is detected that the second operation time exceeds the second preset time range, determining that the second operation result of the chip under test is abnormal, and generating a second abnormal alarm;

[0020] When it is detected that the second operating time is within the second preset time range, the second level is used as the target level of the chip under test.

[0021] According to some embodiments of the first aspect of the present application, determining the first preset time range based on the first level includes:

[0022] Acquire a first historical duration data set of the first level; wherein the first historical duration data set includes the running time of a plurality of the first chips running the test program at the initial frequency;

[0023] Calculating a first average value of the first historical duration data set, and calculating a first standard deviation of the first historical duration data set;

[0024] The first preset time range is determined as ,in, is the first average value; Characterize the first standard deviation.

[0025] According to some embodiments of the first aspect of the present application, the second preset time range determined based on the second level includes:

[0026] Acquire a second historical duration data set of the second level; wherein the second historical duration data set includes the running time of a plurality of the second chips running the test program at the limit frequency;

[0027] Calculating a second average value of the second historical duration data set, and calculating a second standard deviation of the second historical duration data set;

[0028] The second preset time range is determined as ,in, is the second average value; Characterize the second standard deviation.

[0029] According to some embodiments of the first aspect of the present application, after the first running time is detected based on the first preset time range, the method further includes:

[0030] When it is detected that the first operating time is within the first preset time range and the first level is less than or equal to the preset level, taking the first level as the target level of the chip under test;

[0031] The target level is written into the unique identification code of the chip to be tested.

[0032] According to some embodiments of the first aspect of the present application, applied to a host computer, the method further includes:

[0033] In the process of the chip under test running the test program, receiving test data transmitted by the chip under test through the host computer, and determining the first operation result or the second operation result based on the test data;

[0034] When it is detected that the host computer has not received the test data within a preset time period, a communication timeout alarm is generated.

[0035] According to some embodiments of the first aspect of the present application, after determining that the first operating result of the chip to be tested is abnormal and generating a first abnormal alarm, the method further includes:

[0036] Sending the first abnormal alarm to a preset terminal that is communicatively connected to the host computer;

[0037] After determining that the second operation result of the chip to be tested is abnormal and generating a second abnormal alarm, the method further includes:

[0038] Sending the second abnormality alarm to the preset terminal;

[0039] After generating a communication timeout alarm, the method further includes:

[0040] The communication timeout alarm is sent to the preset terminal.

[0041] A second aspect of the present application provides a chip testing device, including:

[0042] A program sending module, used for sending a test program to the chip under test, setting the operating frequency of the chip under test to an initial frequency, and controlling the chip under test to run the test program at the initial frequency;

[0043] A first acquisition module, used for acquiring a first running result and a first running time of the test program when the chip under test runs the test program at the initial frequency;

[0044] A first determining module, configured to determine a first level of the chip to be tested based on the first operating result;

[0045] A second determining module, configured to determine a first preset time range based on the first level;

[0046] A first detection module, configured to detect and process the first running time based on the first preset time range;

[0047] A second detection module is used to determine that the first operation result of the chip to be tested is abnormal and generate a first abnormality alarm when it is detected that the first operation time exceeds the first preset time range;

[0048] A third detection module is used to set the operating frequency of the chip under test to a limit frequency and control the chip under test to run the test program at the limit frequency when it is detected that the first operating time is within the first preset time range and the first level is greater than a preset level;

[0049] A second acquisition module is used to obtain a second running result of the chip under test running the test program at the limit frequency;

[0050] The third determining module is used to determine the second level of the chip under test based on the second operating result.

[0051] A third aspect of the present application provides an electronic device, comprising a memory and a processor, wherein the memory stores a computer program, and the processor implements the chip testing method described in any one of the first aspect embodiments when executing the computer program.

[0052] The fourth aspect of the present application provides a computer-readable storage medium, wherein the storage medium stores a computer program, and when the computer program is executed by a processor, the chip testing method described in any one of the first aspect embodiments is implemented.

[0053] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0054] The present application is further described below with reference to the accompanying drawings and embodiments, wherein:

[0055] Figure 1 A schematic diagram of the steps of the chip testing method according to an embodiment of the present application;

[0056] Figure 2 This is a schematic diagram of the steps after step S190 of the chip testing method according to an embodiment of the present application;

[0057] Figure 3 for Figure 1 Schematic diagram of the specific steps of step S140;

[0058] Figure 4 for Figure 2 Detailed step flow chart of step S220;

[0059] Figure 5 This is a schematic diagram of a sub-process after step S150 of the method of the embodiment of the present application;

[0060] Figure 6 A schematic diagram of a sub-process of the chip testing method according to an embodiment of the present application;

[0061] Figure 7 A schematic diagram of the structure of a chip testing device according to an embodiment of the present application;

[0062] Figure 8 A schematic diagram of the hardware structure of an electronic device according to an embodiment of the present application. DETAILED DESCRIPTION

[0063] The embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be understood as limiting the present application.

[0064] In the description of the present application, it should be understood that descriptions involving orientation, such as up, down, front, back, left, right, etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0065] In the description of this application, "several" means more than one, "more" means more than two, "greater than", "less than", "exceed", etc. are understood to exclude the number itself, and "above", "below", "within", etc. are understood to include the number itself. If there is a description of "first" or "second", it is only used for the purpose of distinguishing technical features, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features or implicitly indicating the order of the indicated technical features.

[0066] In the description of this application, unless otherwise clearly defined, terms such as setting, installing, connecting, etc. should be understood in a broad sense, and technicians in the relevant technical field can reasonably determine the specific meanings of the above terms in this application based on the specific content of the technical solution.

[0067] In the description of the present application, the description with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0068] In the chip testing method of the related art, chip grading errors are prone to occur due to abnormalities of the test board or other factors. In addition, the chip is usually tested only at the normal working frequency of the chip, which can only simply test whether the chip is qualified and simply grade the chip. The grading is relatively rough, resulting in the inability to distinguish chips that can be used in high-demand scenarios.

[0069] Based on this, the present application proposes a chip testing method, device, electronic device and readable storage medium, which can test the chip, classify the chip, and verify the classification of the chip, reduce the risk of chip classification errors, and make the chip classification more refined. The present application tests the chip to be tested at the chip's extreme frequency, and based on the second level, can determine whether the chip to be tested can be used in high-demand scenarios.

[0070] The chip testing method of the embodiment of the present application can be applied to a host computer, which can be a terminal or a server. In some embodiments, the terminal can be a smart phone, a tablet computer, a laptop computer, a desktop computer, etc.; the server can be configured as an independent physical server, or it can be configured as a server cluster or a distributed system composed of multiple physical servers. It can also be configured as a cloud server that provides basic cloud computing services such as cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communications, middleware services, domain name services, security services, CDN, and big data and artificial intelligence platforms; the software can be an application that implements the chip testing method, etc., but is not limited to the above forms.

[0071] The present application can be used in many general or special computer system environments or configurations. For example: personal computers, server computers, handheld or portable devices, tablet devices, multiprocessor systems, microprocessor-based systems, set-top boxes, programmable consumer electronics, network PCs, minicomputers, mainframe computers, distributed computing environments including any of the above systems or devices, etc. The present application can be described in the general context of computer-executable instructions executed by a computer, such as program modules. Generally, program modules include routines, programs, objects, components, data structures, etc. that perform specific tasks or implement specific abstract data types. The present application can also be practiced in distributed computing environments, in which tasks are performed by remote processing devices connected through a communication network. In a distributed computing environment, program modules can be located in local and remote computer storage media including storage devices.

[0072] The first aspect of the present application provides a chip testing method. Figure 1 , Figure 1 The chip testing method of the embodiment of the present application is a schematic diagram of the steps of the process flow. The chip testing method may include but is not limited to the following steps:

[0073] Step S110, sending a test program to the chip under test, setting the operating frequency of the chip under test to an initial frequency, and controlling the chip under test to run the test program at the initial frequency;

[0074] It is worth noting that the chip testing method of the embodiment of the present application is applied to the host computer. When testing, the chip to be tested is installed on the test board and electrically connected to the test board. The host computer is electrically connected to the test board, so that the host computer is connected to the chip to be tested through the test board. The host computer sends a test program to the chip to be tested and sets the operating frequency of the chip to be tested to the initial frequency to control the chip to be tested to run the test program at the initial frequency.

[0075] It should be noted that the test program is a pre-set program for testing the functions of the chip to be tested, and this application does not make any specific limitations on the test program.

[0076] A test board, also known as a test carrier or test fixture, is a circuit board that can fix and connect the device under test (DUT) and connect to the test system through a specific test interface. Its main function is to provide a stable test environment for the chip to ensure the accuracy and reliability of the test results. During the test process, the test board can simulate the actual working environment of the chip and conduct a comprehensive test of the various performance indicators of the chip.

[0077] It should be noted that the operating frequency refers to the clock frequency of the chip under test; and the initial frequency is the clock frequency of the chip under test when it is working normally. Those skilled in the art can set the initial frequency according to actual conditions.

[0078] Step S120, obtaining a first running result and a first running time of the test program when the chip under test runs the test program at the initial frequency;

[0079] It is worth noting that the first running time refers to the time from the start of the test program running to the end of the test program running at the initial frequency of the chip under test.

[0080] Step S130, determining a first level of the chip to be tested based on the first operation result;

[0081] It is worth noting that the first operation result includes a first parameter set, and the first parameter set includes data fed back to the host computer when the chip under test runs the test program and the parameters of the chip under test. For example, the first operation result includes the power consumption and temperature of the chip under test, and also includes the quality of the signal fed back to the host computer, etc. The level of the chip under test is bin level, and each bin level corresponds to a preset range of the first parameter set. The first level of the chip under test can be obtained by comparing the first operation result with the preset range of each first parameter set. The present application does not limit the specific first parameter set of the first operation result. The first parameter sets of different types of chips under test are different. Those skilled in the art can set the first parameter set according to actual conditions.

[0082] It should be noted that, in one embodiment, the bin levels of the chip to be tested are level 1, level 2 and level 3 from low to high, and each level of the chip to be tested is used to provide to different suppliers. Level 3 is further divided into multiple sub-levels, and the multiple sub-levels are 3.1, level 3.2, and level 3.3 from low to high. The higher the level, the better the performance of the chip. In step S130, only the level of the chip to be tested can be preliminarily determined, and the first level is one of level 1, level 2, and level 3. The above chip level category is only an example and cannot be understood as a limitation of this application. Those skilled in the art set the chip level category according to actual needs.

[0083] Step S140, determining a first preset time range based on the first level;

[0084] It is worth noting that the first preset time range is determined by the running time of multiple first-level chips executing the test program at the initial frequency. When the first running time exceeds the first preset time range, it means that the first running time of the chip under test is significantly different from the running time of other chips, indicating that there is an abnormality in the test process of the chip under test.

[0085] Step S150, detecting and processing the first running time based on the first preset time range;

[0086] Step S160, when it is detected that the first operation time exceeds the first preset time range, determining that the first operation result of the chip to be tested is abnormal, and generating a first abnormal alarm;

[0087] In one embodiment, the first abnormal alarm is a first prompt text composed of a first abnormal prompt word, a unique identification code of the chip to be tested, and a number of a test board corresponding to the chip to be tested, and the unique identification code is used to uniquely indicate the chip to be tested. Usually, the prompt text is displayed in the display of the host computer in the form of a pop-up window, so that when the relevant staff observes the first prompt text, the abnormal chip to be tested and the test board can be determined based on the first prompt text. Those skilled in the art can set the first abnormal prompt word according to actual needs.

[0088] Step S170, when it is detected that the first operating time is within the first preset time range and the first level is greater than the preset level, the operating frequency of the chip under test is set to the limit frequency, and the chip under test is controlled to run the test program at the limit frequency;

[0089] It should be noted that those skilled in the art can freely set the preset level according to production quality requirements.

[0090] Step S180, obtaining a second running result of the chip under test running the test program at the limit frequency;

[0091] It should be noted that the second operation result includes a second parameter set, and the second parameter set includes the data fed back to the host computer when the chip to be tested runs the test program and the parameters of the chip to be tested. For example, the second operation result includes the power consumption and temperature of the chip to be tested, and also includes the quality of the signal fed back to the host computer, etc. Each level corresponds to a preset range of a second parameter set, and the second level of the chip to be tested can be obtained by comparing the second operation result with the preset range of each second parameter set. The present application does not limit the specific second parameter set of the second operation result, and the second parameter sets of different types of chips to be tested are different. The second parameter set may be the same as the first parameter set, or it may be different from the first parameter set. Those skilled in the art can set the second parameter set according to actual conditions.

[0092] Step S190: determining a second level of the chip to be tested based on the second operation result.

[0093] It is worth noting that in step S130, only the level of the chip to be tested can be preliminarily determined. When the first level is greater than the preset level, it is necessary to further determine the subdivision level of the chip to be tested. Exemplarily, the preset level is level 2. If the first level is level 2 or level 1, there is no need to perform steps S170 to S190, and the target level of the chip to be tested is set to the first level. If the first level is level 3, that is, the first level is greater than the preset level, the operating frequency of the chip to be tested is set to the limit frequency, and the chip to be tested is controlled to run the test program at the limit frequency, and the second running result of the chip to be tested running the test program at the limit frequency is obtained. The second level of the chip to be tested is determined based on the second running result, and the second level is one of level 3.1, level 3.2 and level 3.3.

[0094] It should be noted that the chip under test is set with a frequency range of operating frequency, the initial frequency is usually set at the middle value of the frequency range, and the limit frequency is the upper limit value of the frequency range. When the chip under test is controlled to run the test program at the limit frequency, the performance of the chip under test at the limit frequency can be obtained based on the second running result.

[0095] The chip testing method of the embodiment of the present application firstly makes the chip to be tested run the test program at the initial frequency through the above steps S110 to S190, thereby obtaining the first running result and the first running time, determining the first level of the chip to be tested based on the first running result; determining the first preset time range based on the first level; in the case where it is detected that the first running time exceeds the first preset time range, it means that the test process of the chip to be tested is abnormal, and the chip classification is inaccurate, so the first running result of the chip to be tested is determined to be abnormal, and a first abnormal alarm is generated. When it is detected that the first running time is within the first preset time range and the first level is greater than the preset level, the chip to be tested runs the test program at the limit frequency, obtains the second running result, and thus determines the second level of the chip to be tested based on the second running result. In this way, when it is determined that the classification of the first level is correct, the second running result characterizes the performance of the chip to be tested at the limit frequency, and can further determine a more refined classification of the chip to be tested. In this way, the present application tests the chip, grades the chip, and verifies the classification of the chip, reduces the risk of chip classification errors, and makes the chip classification more refined. In addition, the present application performs testing according to the initial frequency and the limit frequency. For chips whose first level is lower than the preset level, there is no need to perform high-frequency testing at the limit frequency. Only chips whose first level is higher than the preset level are tested at the limit frequency, thereby improving the test efficiency.

[0096] In one embodiment, referring to Figure 2 , Figure 2The chip testing method of the embodiment of the present application is a flowchart of the steps after step S190. After step S190, the following steps are also included:

[0097] Step S210, obtaining a second running time of the test program running at the limit frequency of the chip under test;

[0098] It should be noted that the second running time refers to the time from the start of the test program running to the end of the test program running at the limit frequency of the chip under test.

[0099] Step S220, a second preset time range determined based on the second level;

[0100] It is worth noting that the second preset time range is determined by the running time of multiple second-level chips executing the test program at the initial frequency. When the second running time exceeds the second preset time range, it means that the second running time of the chip under test is significantly different from the running time of other chips, indicating that there is an abnormality in the test process of the chip under test.

[0101] Step S230, detecting and processing the second running time based on the second preset time range;

[0102] Step S240, when it is detected that the second operation time exceeds the second preset time range, determining that the second operation result of the chip to be tested is abnormal, and generating a second abnormal alarm;

[0103] In one embodiment, the second abnormal alarm is a second prompt text composed of a second abnormal prompt word, a unique identification code of the chip to be tested, and a number of a test board corresponding to the chip to be tested, and the unique identification code is used to uniquely indicate the chip to be tested. Usually, the second prompt text is displayed in the display of the host computer in the form of a pop-up window, so that when the relevant staff observes the second prompt text, the abnormal chip to be tested and the test board can be determined based on the second prompt text. Those skilled in the art can set the second abnormal prompt word according to actual needs.

[0104] Step S250: When it is detected that the second operating time is within the second preset time range, the second level is used as the target level of the chip to be tested.

[0105] It is worth noting that the embodiment of the present application can further verify whether the test process of the chip to be tested is abnormal through steps S210 to S250. When it is detected that the second operation time exceeds the second preset time range, it is determined that the second operation result of the chip to be tested is abnormal, and a second abnormal alarm is generated; when it is detected that the second operation time is within the second preset time range, it means that there is no abnormality in the test process of the chip to be tested, so the second level is used as the target level of the chip to be tested.

[0106] In one embodiment, after step S250, the target level needs to be written into the unique identification code of the chip to be tested, so as to update the original unique identification code of the chip to be tested.

[0107] In one embodiment, referring to Figure 3 , Figure 3 for Figure 1 Detailed step flow chart of step S140 in FIG. Step S140 may include but is not limited to the following steps:

[0108] Step S310, obtaining a first historical duration data set of a first level; wherein the first historical duration data set includes the running duration of a plurality of first chips running a test program at an initial frequency;

[0109] Step S320, calculating a first average value of the first historical duration data set, and calculating a first standard deviation of the first historical duration data set;

[0110] Step S330: determine the first preset time range as ,in, is the first average value; Characterizes the first standard deviation.

[0111] In the embodiment of the present application, through step S310 to step S330, a first preset time range can be determined, and the first preset time range is determined by a first average value and a first standard deviation of the first historical time data set. The first average value and the first standard deviation are two important parameters that describe the central trend and the degree of dispersion of the first historical time data set. Specifically, the running time of the test program running at the initial frequency of the plurality of first chips conforms to the normal distribution. It can be used as an identification interval for abnormal values. When the first running time of the chip under test exceeds , then the first running time is considered to be an abnormal value, and therefore it is determined that the first running result of the chip to be tested is abnormal.

[0112] In one embodiment, referring to Figure 4 , Figure 4 for Figure 2 Detailed step flow diagram of step S220 in FIG. Step S220 may include but is not limited to the following steps:

[0113] Step S410, obtaining a second historical duration data set of the second level; wherein the second historical duration data set includes the running duration of the test program running at the limit frequency of the plurality of second chips;

[0114] Step S420, calculating a second average value of the second historical duration data set, and calculating a second standard deviation of the second historical duration data set;

[0115] Step S430, determine the second preset time range as ,in, is the second average value; Characterizes the second standard deviation.

[0116] In the embodiment of the present application, through step S410 to step S430, a second preset time range can be determined, and the second preset time range is determined by a second mean value and a second standard deviation of the second historical duration data set. The second mean value and the second standard deviation are two important parameters describing the central trend and the degree of dispersion of the second historical duration data set. Specifically, the running time of the plurality of second chips running the test program at the initial frequency conforms to a normal distribution. It can be used as an identification interval for abnormal values. When the first running time of the chip under test exceeds , the second running time is considered to be an abnormal value, and therefore it is determined that the second running result of the chip to be tested is abnormal.

[0117] In one embodiment, referring to Figure 5 , Figure 5 This is a schematic diagram of a sub-flow chart of the method according to the embodiment of the present application after step S150. The chip testing method according to the embodiment of the present application further comprises the following steps after step S150:

[0118] Step S510, when it is detected that the first running time is within a first preset time range and the first level is less than or equal to the preset level, the first level is used as the target level of the chip to be tested;

[0119] Step S520, writing the target level into the unique identification code of the chip to be tested.

[0120] It is worth noting that if the first running time is within the first preset range, it means that there is no abnormality in the first running result, and if the first level is less than or equal to the preset level, it means that the level of the chip to be tested is low and no further testing is required. Therefore, the first level is used as the target level of the chip to be tested. After the test is completed, the target level is written into the unique identification code of the chip to be tested, and the unique identification code of the chip to be tested is updated. For example, if the target level is A and the original unique identification code of the chip to be tested is B, then B and A are spliced ​​to obtain a new unique identification code. In this way, when the test is completed, the chips to be tested need to be sorted based on the level, so that relevant personnel can determine the level of the chip by seeing the unique identification code of the chip.

[0121] In one embodiment, referring to Figure 6 , Figure 6 A schematic diagram of a sub-process of the chip testing method according to an embodiment of the present application. Figure 6 The schematic process includes the following steps:

[0122] Step S610, during the process of the chip under test running the test program, receiving test data transmitted by the chip under test through the host computer, and determining a first running result or a second running result based on the test data;

[0123] Step S620: When it is detected that the host computer does not receive the test data within a preset time period, a communication timeout alarm is generated.

[0124] It is worth noting that in step S110 or step S170, during the process of the chip under test running the test program, the chip under test will continuously feed back test data to the host computer, and the first operation result is composed of the test data fed back by the chip under test during step S110. The second operation result is composed of the test data fed back by the chip under test during step S170. During the process of the chip under test running the test program, it is indicated that the operation of the chip under test is abnormal, or the communication between the chip under test and the host computer is abnormal, so a communication timeout alarm is generated. The present application does not make specific limitations on the preset time period, and those skilled in the art set the preset time period according to actual conditions.

[0125] In one embodiment, after determining that the first operation result of the chip to be tested is abnormal and generating a first abnormal alarm, the method further includes:

[0126] Sending the first abnormal alarm to a preset terminal connected to the host computer for communication;

[0127] After determining that the second operation result of the chip to be tested is abnormal and generating a second abnormal alarm, the method further includes:

[0128] Sending the second abnormal alarm to a preset terminal;

[0129] After a communication timeout alarm is generated, it also includes:

[0130] Sends a communication timeout alarm to a preset terminal.

[0131] It is worth noting that the preset terminal is connected to the host computer by communication, for example, through the Internet, which can be a wired connection or a wireless connection. The preset terminal can be a terminal device such as a mobile phone or a laptop computer. The first abnormal alarm, the second abnormal alarm and the communication timeout alarm are sent to the preset terminal so that the user of the preset terminal can view the first abnormal alarm, the second abnormal alarm and the communication timeout alarm, thereby reminding the user of the preset terminal to handle it.

[0132] The second aspect of the present application provides a chip testing device. Figure 7 , Figure 7 The chip testing device of the embodiment of the present application is a schematic diagram of the structure of the chip testing device. The chip testing device includes:

[0133] The program sending module 710 is used to send the test program to the chip under test, set the working frequency of the chip under test to the initial frequency, and control the chip under test to run the test program at the initial frequency;

[0134] A first acquisition module 720 is used to acquire a first running result and a first running time of the test program running at an initial frequency of the chip under test;

[0135] A first determination module 730, configured to determine a first level of the chip to be tested based on a first operation result;

[0136] A second determination module 740, configured to determine a first preset time range based on the first level;

[0137] A first detection module 750, configured to detect and process the first running time based on a first preset time range;

[0138] The second detection module 760 is used to determine that the first operation result of the chip to be tested is abnormal and generate a first abnormality alarm when it is detected that the first operation time exceeds the first preset time range;

[0139] The third detection module 770 is used to set the operating frequency of the chip under test to the limit frequency and control the chip under test to run the test program at the limit frequency when it is detected that the first operating time is within the first preset time range and the first level is greater than the preset level;

[0140] A second acquisition module 780 is used to obtain a second running result of the test program running at the limit frequency of the chip under test;

[0141] The third determination module 790 is used to determine the second level of the chip to be tested based on the second operation result.

[0142] The chip testing device of the embodiment of the present application is used to execute the chip testing method of the embodiment of the first aspect of the present application. When executing the method, the chip to be tested is first made to run the test program at the initial frequency, so as to obtain the first running result and the first running time, and the first level of the chip to be tested is determined based on the first running result; the first preset time range is determined based on the first level; when it is detected that the first running time exceeds the first preset time range, it means that the test process of the chip to be tested is abnormal, and the chip classification is inaccurate, so the first running result of the chip to be tested is determined to be abnormal, and a first abnormal alarm is generated. When it is detected that the first running time is within the first preset time range and the first level is greater than the preset level, the chip to be tested is made to run the test program at the limit frequency, and the second running result is obtained, so as to determine the second level of the chip to be tested based on the second running result. In this way, when it is determined that the classification of the first level is correct, the second running result characterizes the performance of the chip to be tested at the limit frequency, and can further determine a more refined classification of the chip to be tested. In this way, the present application tests the chip, grades the chip, and verifies the classification of the chip, reduces the risk of chip classification errors, and makes the chip classification more refined. In addition, the present application performs testing according to the initial frequency and the limit frequency. For chips whose first level is lower than the preset level, there is no need to perform high-frequency testing at the limit frequency. Only chips whose first level is higher than the preset level are tested at the limit frequency, thereby improving the test efficiency.

[0143] It should be noted that the specific implementation of the chip testing device is basically the same as the specific implementation of the chip testing method in the above-mentioned embodiment, and will not be repeated here. On the premise of meeting the requirements of the embodiment of this application, the chip testing device can also be provided with other functional modules to implement the chip testing method in the above-mentioned embodiment.

[0144] The third aspect of the present application provides an electronic device, the electronic device includes a memory and a processor, the memory stores a computer program, and the processor implements the chip testing method of the above embodiment when executing the computer program. The electronic device can be any smart terminal including a tablet computer, a car computer, etc.

[0145] In one embodiment, referring to Figure 8 , Figure 8 The hardware structure of the electronic device of the embodiment of the present application is illustrated, and the electronic device includes:

[0146] The processor 801 may be implemented by a general-purpose CPU (Central Processing Unit), a microprocessor, an application-specific integrated circuit (Application Specific Integrated Circuit, ASIC), or one or more integrated circuits, and is used to execute relevant programs to implement the technical solutions provided in the embodiments of the present application;

[0147] The memory 802 can be implemented in the form of a read-only memory (ROM), a static storage device, a dynamic storage device, or a random access memory (RAM). The memory 802 can store an operating system and other application programs. When the technical solution provided in the embodiment of this specification is implemented by software or firmware, the relevant program code is stored in the memory 802, and the processor 801 calls and executes the chip testing method of the embodiment of this application;

[0148] Input / output interface 803, used to implement information input and output;

[0149] The communication interface 804 is used to realize the communication interaction between the device and other devices. The communication can be realized through wired means (such as USB, network cable, etc.) or wireless means (such as mobile network, WIFI, Bluetooth, etc.);

[0150] A bus 805 that transmits information between various components of the device (e.g., the processor 801, the memory 802, the input / output interface 803, and the communication interface 804);

[0151] The processor 801 , the memory 802 , the input / output interface 803 and the communication interface 804 are connected to each other in communication within the device via a bus 805 .

[0152] The fourth aspect of the present application is a computer-readable storage medium, which stores a computer program. When the computer program is executed by a processor, the chip testing method of the first aspect is implemented.

[0153] The memory, as a non-transient computer-readable storage medium, can be used to store non-transient software programs and non-transient computer executable programs. In addition, the memory may include a high-speed random access memory, and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage device. In some embodiments, the memory may optionally include a memory remotely disposed relative to the processor, and these remote memories may be connected to the processor via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0154] The embodiments described in the embodiments of the present application are intended to more clearly illustrate the technical solutions of the embodiments of the present application and do not constitute a limitation on the technical solutions provided in the embodiments of the present application. Those skilled in the art will appreciate that with the evolution of technology and the emergence of new application scenarios, the technical solutions provided in the embodiments of the present application are also applicable to similar technical problems.

[0155] Those skilled in the art will appreciate that the technical solutions shown in the figures do not constitute a limitation on the embodiments of the present application, and may include more or fewer steps than shown in the figures, or a combination of certain steps, or different steps.

[0156] The device embodiments described above are merely illustrative, and the units described as separate components may or may not be physically separated, that is, they may be located in one place or distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0157] Those skilled in the art will appreciate that all or some of the steps in the methods disclosed above, and the functional modules / units in the systems and devices may be implemented as software, firmware, hardware, or a suitable combination thereof.

[0158] The terms "first", "second", "third", "fourth", etc. (if any) in the specification of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0159] It should be understood that in the present application, "at least one (item)" means one or more, and "plurality" means two or more. "And / or" is used to describe the association relationship of associated objects, indicating that three relationships may exist. For example, "A and / or B" can mean: only A exists, only B exists, and A and B exist at the same time, where A and B can be singular or plural. The character " / " generally indicates that the objects associated before and after are in an "or" relationship. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a, b or c can mean: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, c can be single or multiple.

[0160] In the several embodiments provided in the present application, it should be understood that the disclosed systems and methods can be implemented in other ways. For example, the system embodiments described above are merely schematic. For example, the division of the above units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, devices or units, which can be electrical, mechanical or other forms.

[0161] The units described above as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0162] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0163] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including multiple instructions to enable a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of various embodiments of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (Read-Only Memory, referred to as ROM), random access memory (Random Access Memory, referred to as RAM), disk or optical disk and other media that can store programs.

[0164] The preferred embodiments of the present invention are described above with reference to the accompanying drawings, but the scope of the rights of the present invention is not limited thereto. Any modification, equivalent substitution and improvement made by a person skilled in the art without departing from the scope and essence of the present invention should be within the scope of the rights of the present invention.

Claims

1. A chip testing method, characterized in that: include: Sending a test program to the chip under test, setting the operating frequency of the chip under test to an initial frequency, and controlling the chip under test to run the test program at the initial frequency; Obtaining a first running result and a first running time of the test program when the chip under test runs the test program at the initial frequency; Determine a first level of the chip under test based on the first operation result; determining a first preset time range based on the first level; Performing detection and processing on the first running time based on the first preset time range; When it is detected that the first operation time exceeds the first preset time range, determining that the first operation result of the chip to be tested is abnormal, and generating a first abnormality alarm; When it is detected that the first running time is within the first preset time range and the first level is greater than a preset level, setting the operating frequency of the chip under test to a limit frequency, and controlling the chip under test to run the test program at the limit frequency; Obtain a second running result of the chip under test running the test program at the limit frequency; A second grade of the chip under test is determined based on the second operation result.

2. The chip testing method according to claim 1, characterized in that: After determining the second level of the chip under test based on the second operation result, the method further includes: Obtaining a second running time of the test program executed by the chip under test at the limit frequency; a second preset time range determined based on the second level; Performing detection processing on the second running time based on the second preset time range; When it is detected that the second operation time exceeds the second preset time range, determining that the second operation result of the chip under test is abnormal, and generating a second abnormal alarm; When it is detected that the second operating time is within the second preset time range, the second level is used as the target level of the chip under test.

3. The chip testing method according to claim 1, characterized in that: The determining a first preset time range based on the first level includes: Acquire a first historical duration data set of the first level; wherein the first historical duration data set includes the running time of the test program run by a plurality of first chips at the initial frequency; Calculating a first average value of the first historical duration data set, and calculating a first standard deviation of the first historical duration data set; The first preset time range is determined as ,in, is the first average value; Characterize the first standard deviation.

4. The chip testing method according to claim 2, characterized in that: The second preset time range determined based on the second level includes: Acquire a second historical duration data set of the second level; wherein the second historical duration data set includes the running time of a plurality of second chips running the test program at the limit frequency; Calculating a second average value of the second historical duration data set, and calculating a second standard deviation of the second historical duration data set; The second preset time range is determined as ,in, is the second average value; Characterize the second standard deviation.

5. The chip testing method according to claim 1, characterized in that: After the first running time is detected based on the first preset time range, the method further includes: When it is detected that the first operating time is within the first preset time range and the first level is less than or equal to the preset level, taking the first level as the target level of the chip under test; The target level is written into the unique identification code of the chip to be tested.

6. The chip testing method according to claim 2, characterized in that: Applied to a host computer, the method further includes: In the process of the chip under test running the test program, receiving test data transmitted by the chip under test through the host computer, and determining the first operation result or the second operation result based on the test data; When it is detected that the host computer has not received the test data within a preset time period, a communication timeout alarm is generated.

7. The chip testing method according to claim 6, characterized in that: After determining that the first operation result of the chip to be tested is abnormal and generating a first abnormal alarm, the method further includes: Sending the first abnormal alarm to a preset terminal that is communicatively connected to the host computer; After determining that the second operation result of the chip to be tested is abnormal and generating a second abnormal alarm, the method further includes: Sending the second abnormality alarm to the preset terminal; After generating a communication timeout alarm, the method further includes: The communication timeout alarm is sent to the preset terminal.

8. A chip testing device, characterized in that: include: A program sending module, used for sending a test program to the chip under test, setting the operating frequency of the chip under test to an initial frequency, and controlling the chip under test to run the test program at the initial frequency; A first acquisition module, used for acquiring a first running result and a first running time of the test program when the chip under test runs the test program at the initial frequency; A first determining module, configured to determine a first level of the chip to be tested based on the first operating result; A second determining module, configured to determine a first preset time range based on the first level; A first detection module, configured to detect and process the first running time based on the first preset time range; A second detection module is used to determine that the first operation result of the chip to be tested is abnormal and generate a first abnormality alarm when it is detected that the first operation time exceeds the first preset time range; A third detection module is used to set the operating frequency of the chip under test to a limit frequency and control the chip under test to run the test program at the limit frequency when it is detected that the first operating time is within the first preset time range and the first level is greater than a preset level; A second acquisition module is used to obtain a second running result of the chip under test running the test program at the limit frequency; The third determining module is used to determine the second level of the chip under test based on the second operating result.

9. An electronic device, characterized in that: The electronic device comprises a memory and a processor, the memory stores a computer program, and the processor implements the chip testing method according to any one of claims 1 to 7 when executing the computer program.

10. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the chip testing method according to any one of claims 1 to 7 is implemented.

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