Method, system and device for checking correctness of NAND data and medium
By preparing non-repetitive data in CPU memory, writing batches to NAND memory, and using random read commands and information comparison tables for data verification, the problem of limited testing environment in traditional methods is solved, and efficient NAND data verification is achieved.
Patent Information
- Application Number
- CN202411687927.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-25
- Publication Date
- 2025-03-07
AI Technical Summary
The traditional NAND data verification method is limited in the test environment. Since the CPU memory space is much smaller than the NAND memory capacity, it is difficult to perform data verification effectively. Especially when the Block unit is not full, reading the written WL may cause data errors, increasing the verification difficulty.
By preparing non-repetitive data of at least 1 Block size in the CPU memory of the test system, it is written to the NAND memory in batches, and the write information comparison table is recorded. Randomly generate read commands, read data and record read information comparison tables, and finally compare the data based on the two tables to confirm the correctness of the data.
This method simplifies the test process, significantly improves the testing efficiency, and can effectively verify the accuracy of NAND data in an environment with small CPU memory space, reducing the requirements for the test environment.
Smart Images
Figure CN119576234A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a NAND data correctness verification method, system, device and medium, belonging to the technical field of memory verification. Background Art
[0002] With the continuous development of storage technology, NAND memory, as one of the current mainstream storage media, has greatly improved its capacity. The capacity of a single NAND memory chip currently on the market has generally reached several hundred GB, which provides more possibilities for data storage. However, as the capacity of NAND memory increases, higher requirements are also placed on the correctness verification of its data.
[0003] Traditional NAND data verification methods often require preparing test data in the CPU memory of the test system that is equivalent to or larger than the capacity of the NAND memory, and then performing write and read operations one by one to verify the correctness of the data. However, in actual test environments, the available memory of the CPU in general test system environments is generally tens of GB, which is far less than the capacity of the NAND memory, which greatly limits the traditional verification method in practical applications.
[0004] In addition, due to the structural characteristics of NAND memory, its internal units can be subdivided into multiple levels such as CE, LUN, Block and WL, among which the WL unit is the smallest unit of NAND write operation. If the Block unit is not fully written, reading the written WL inside it may cause data errors, which undoubtedly increases the difficulty of data verification.
[0005] Therefore, how to effectively verify the data in the NAND memory under the limited test environment, that is, when the CPU memory space is much smaller than the NAND memory capacity, has become an urgent problem to be solved. Summary of the invention
[0006] The purpose of the present invention is to provide a NAND data correctness verification method and system, device, and medium, which effectively meet the NAND data correctness test requirements and improve the test efficiency.
[0007] In order to achieve the above object, the present invention is implemented through the following technical solutions: A method for checking the correctness of NAND data comprises the following steps: Prepare non-repetitive data with a capacity of at least 1 Block in the CPU memory of the test system; Writing the data generated in the preparation phase to the Block numbered 0 under all CE and LUN units in the NAND memory; During the writing process, the correspondence between the data in each PBA in each Block and the memory data location is recorded to form a write information comparison table; Generate random read commands in batches, randomly select different PBAs to read data, store the read data in a non-conflicting location in the memory, and record the location in the memory where the data is read, the location of the PBA, and the length of the read data to form a read information comparison table; After all read commands are sent, the data corresponding to the memory address pointing to the same PBA is compared according to the read information comparison table and the write information comparison table to confirm the correctness of the data; Iterate the above steps until all blocks are verified.
[0008] Preferably, the number of random read commands is smaller than the data storage capacity of the Block, the size of the non-repetitive data is the Block capacity of a CE and LUN unit; the multiple CE and LUN units refer to all CE and LUN units in the NAND memory.
[0009] Preferably, the read command ensures that the distribution function satisfies the average distribution through a random algorithm, so that all WordLines in the Block have the same probability of being read.
[0010] Preferably, the method performs write and read operations on the data to be tested in multiple blocks each time.
[0011] Preferably, the random batch generation read command is generated by a pseudo-random number generation module; The pseudo-random number generation module generates a random number, and the remainder obtained by taking the modulus of the value obtained by the random number modulus and the total number of PBAs is the number of the target PBA; and the random number and the target PBA number are recorded at the same time to form a mapping table; The write information comparison table is formed by the position relationship of the data in each PBA in all blocks to form a mapping table; the read information comparison table is formed by the position relationship of each read data in the memory address to form a mapping table.
[0012] A NAND data correctness verification system, comprising: Memory preparation data module: prepares non-repetitive data with a capacity of at least 1 Block in the CPU memory of the test system; Write information table construction module: write the data generated in the preparation stage to the Block numbered 0 under all CE and LUN units in the NAND memory; during the writing process, record the correspondence between the data in each PBA in each Block and the memory data position to form a write information comparison table; Read information table construction module: randomly generates several read commands in batches, randomly selects different PBAs for data reading, stores the read data in a non-conflicting location in the memory, and records the location of the data in the memory, the location of the PBA, and the length of the read data to form a read information comparison table; Read information table extraction module: After all read commands are sent, the data corresponding to the memory address pointing to the same PBA is compared according to the read information comparison table and the write information comparison table to confirm the correctness of the data.
[0013] A NAND data correctness checking device comprises a processor and a memory storing program instructions, wherein the processor is configured to execute the NAND data correctness checking method when running the program instructions.
[0014] A computer-readable storage medium stores a computer program, which implements the NAND data correctness verification method when executed by a processor.
[0015] The advantages of the present invention are as follows: when testing NAND memory, the traditional method is often limited by the CPU memory space of the test system. When the capacity of the NAND memory is much larger than the available space of the CPU memory, the traditional method is difficult to effectively verify the data. However, the present invention designs an efficient testing scheme by utilizing the structural characteristics of the NAND chip, which greatly reduces the requirements for the test environment. Even when the CPU memory space is small, the correctness verification of NAND data can be achieved.
[0016] During the test process, the present invention adopts a scheme of first writing data in batches, then selecting some representative PBAs for batch random reading, and finally performing data comparison. This scheme not only simplifies the test process, but also significantly improves the test efficiency. By performing write and read operations on multiple different minimum units, the requirements for full NAND data verification are gradually met, greatly shortening the test time.
[0017] During the test, the present invention adopts a random read operation and a memory comparison table solution to ensure the reliability of data verification. The PBA is selected for reading through a random algorithm to ensure the uniformity and representativeness of data reading. At the same time, the location and correspondence of the data are recorded through the memory comparison table, which realizes the accurate comparison between the reading result and the original data, thereby ensuring the accuracy of data verification. BRIEF DESCRIPTION OF THE DRAWINGS
[0018] The accompanying drawings are used to provide further understanding of the present invention and constitute a part of the specification. They are used to explain the present invention together with the embodiments of the present invention and do not constitute a limitation of the present invention.
[0019] Figure 1It is a schematic diagram of the process structure of the method of the present invention. DETAILED DESCRIPTION
[0020] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.
[0021] Example 1 like Figure 1 As shown, a NAND data correctness verification method includes the following steps: S1: Prepare non-repetitive data with a capacity of at least 1 Block in the CPU memory of the test system.
[0022] S2: Write the data generated in the preparation phase into the Block No. 0 under all CE and LUN units in the NAND memory.
[0023] S3: During the writing process, the correspondence between the data in each PBA (Physical Block Address) in each Block and the memory data location is recorded to form a write information comparison table.
[0024] When the write command type is different, the corresponding relationship between PBA and memory in the comparison table will also be different.
[0025] S4: Generate random read commands in batches, randomly select different PBAs for data reading, store the read data in a non-conflicting position in the memory, and record the position of the data read in the memory, the position of the PBA, and the length of the read data to form a read information comparison table.
[0026] S5: After all read commands are sent, the data corresponding to the memory address pointing to the same PBA are compared according to the read information comparison table and the write information comparison table to confirm the correctness of the data.
[0027] S6: Iterate the above steps until all blocks are verified.
[0028] As a refinement of the above embodiment, the number of random read commands is smaller than the data storage capacity of the Block, the size of the non-repetitive data is the Block capacity of a CE and LUN unit; the multiple CE and LUN units refer to all CE and LUN units in the NAND memory.
[0029] As a refinement of the above embodiment, the read command ensures that the distribution function satisfies the average distribution through a random algorithm, so that all WordLines in the Block have the same probability of being read.
[0030] To ensure test efficiency, the number of read commands can be much smaller than the data storage capacity of the block, but the random algorithm must ensure that the distribution function satisfies the average distribution so that small, medium and large WLs in a block have the probability of being read.
[0031] As a refinement of the above embodiment, the method performs write and read operations on the data to be tested in multiple blocks each time.
[0032] As a refinement of the above embodiment, the random batch generation read command is generated by a pseudo-random number generation module; The pseudo-random number generation module generates a random number, and the remainder obtained by modulo the value obtained by the random number modulus and the total number of PBAs is obtained, and the remainder obtained is the number of the target PBA; the random number and the target PBA number are recorded at the same time to form a mapping table.
[0033] The write information comparison table is formed by the position relationship of the data in each PBA in all blocks to form a mapping table; the read information comparison table is formed by the position relationship of each read data in the memory address to form a mapping table.
[0034] It should be noted that: through the above method, the requirements for CPU memory space can be reduced by tens or even hundreds of times, and due to the introduction of random read operations, the test efficiency is effectively improved while ensuring the reliability of data verification. If there are higher requirements for reliability, the number of random read commands can be increased, or the PBAs can be read directly one by one.
[0035] The method provided by the present invention is simple to operate but has obvious effects. During the test, the structural characteristics of the NAND chip are utilized to find the minimum unit that can be tested. By repeating the write and read operations on multiple different minimum units, the requirements for full NAND data verification are gradually completed. In addition, due to the introduction of the random read scheme and the memory comparison table scheme, the test efficiency is greatly improved while ensuring the reliability of data verification. Compared with the traditional method, the requirements for the test environment are significantly reduced, and it can be deployed in a test environment with a small CPU memory space, which has excellent practicality.
[0036] Example 2 A NAND data correctness verification system, comprising: Memory preparation data module: In the CPU memory of the test system, according to the number of blocks and block capacity of each die, prepare non-repetitive data with a capacity of at least 1 block.
[0037] Write information table construction module: write the data generated in the preparation stage to the Block numbered 0 under all CE and LUN units in the NAND memory; during the writing process, record the correspondence between the data in each PBA in each Block and the memory data position to form a write information comparison table.
[0038] Read information table construction module: randomly generates several read commands in batches, randomly selects different PBAs for data reading, stores the read data in a non-conflicting location in the memory, and records the location in the memory where the data is read, the location of the PBA, and the length of the read data to form a read information comparison table.
[0039] Read information table extraction module: After all read commands are sent, the data corresponding to the memory address pointing to the same PBA is compared according to the read information comparison table and the write information comparison table to confirm the correctness of the data.
[0040] CE (Chip Enable): Chip enable pin, used to select or deselect the NAND chip.
[0041] LUN (Logical Unit Number): refers to the logical unit number.
[0042] Die: A component inside a chip. Each Die contains multiple channels and several storage units.
[0043] The embodiment of the present disclosure provides a NAND data correctness verification device, including a processor and a memory. Optionally, the device may also include a communication interface and a bus. The processor, the communication interface, and the memory may communicate with each other through the bus. The communication interface may be used for information transmission. The processor may call the logic instructions in the memory to execute the NAND data correctness verification method of the above embodiment.
[0044] In addition, the logic instructions in the above-mentioned memory can be implemented in the form of software functional units and can be stored in a computer-readable storage medium when sold or used as an independent product.
[0045] The memory, as a computer-readable storage medium, can be used to store software programs and computer executable programs, such as program instructions / modules corresponding to the method in the embodiment of the present disclosure. The processor 304 executes the functional application and data processing by running the program instructions / modules stored in the memory, that is, the NAND data correctness verification method in the above embodiment is implemented.
[0046] The memory may include a program storage area and a data storage area, wherein the program storage area may store an operating system and an application required for at least one function; the data storage area may store data created according to the use of the terminal device, etc. In addition, the memory may include a high-speed random access memory and may also include a non-volatile memory.
[0047] An embodiment of the present disclosure provides a computer-readable storage medium storing computer-executable instructions, wherein the computer-executable instructions are configured to execute the above-mentioned NAND data correctness verification method.
[0048] The computer-readable storage medium mentioned above may be a transient computer-readable storage medium or a non-transitory computer-readable storage medium.
[0049] The technical solution of the embodiment of the present disclosure can be embodied in the form of a software product, which is stored in a storage medium and includes one or more instructions for enabling a computer device (which may be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in the embodiment of the present disclosure. The aforementioned storage medium may be a non-transient storage medium, including: a USB flash drive, a mobile hard disk, a read-only memory (ROM, Read-Only Memory), a random access memory (RAM, Random Access Memory), a disk or an optical disk, and other media that can store program codes, or a transient storage medium.
[0050] Finally, it should be noted that the above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art can still modify the technical solutions described in the aforementioned embodiments or replace some of the technical features therein by equivalents. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.
Claims
1. A NAND data correctness verification method, characterized in that: The following steps are involved: Prepare non-repetitive data with a capacity of at least 1 Block in the CPU memory of the test system; Writing the data generated in the preparation phase to the Block numbered 0 under all CE and LUN units in the NAND memory; During the writing process, the correspondence between the data in each PBA in each Block and the memory data location is recorded to form a write information comparison table; Generate random read commands in batches, randomly select different PBAs to read data, store the read data in a non-conflicting location in the memory, and record the location of the data read in the memory, the location of the PBA, and the length of the read data to form a read information comparison table; After all read commands are sent, the data corresponding to the memory address pointing to the same PBA is compared according to the read information comparison table and the write information comparison table to confirm the correctness of the data; Iterate the above steps until all blocks are verified.
2. The NAND data correctness verification method according to claim 1, characterized in that: The number of random read commands is smaller than the data storage capacity of the Block, the size of the non-repetitive data is the Block capacity of a CE and LUN unit; the multiple CE and LUN units refer to all CE and LUN units in the NAND memory.
3. The NAND data correctness verification method according to claim 2, characterized in that: The read command uses a random algorithm to ensure that the distribution function satisfies the average distribution, so that all WordLines in the Block have the same probability of being read.
4. The NAND data correctness verification method according to claim 2, characterized in that: The method performs write and read operations on the data to be tested in multiple blocks each time.
5. The NAND data correctness verification method according to claim 2, characterized in that: The random batch generation read command is generated by a pseudo-random number generation module; The pseudo-random number generation module generates a random number, and the remainder obtained by taking the modulus of the value obtained by the random number modulus and the total number of PBAs is the number of the target PBA; and the random number and the target PBA number are recorded at the same time to form a mapping table; The write information comparison table is formed by the position relationship of the data in each PBA in all blocks to form a mapping table; the read information comparison table is formed by the position relationship of each read data in the memory address to form a mapping table.
6. A NAND data correctness verification system using the method according to any one of claims 1 to 5, characterized in that: include: Memory preparation data module: prepares non-repetitive data with a capacity of at least 1 Block in the CPU memory of the test system; Write information table construction module: write the data generated in the preparation stage to the Block numbered 0 under all CE and LUN units in the NAND memory; during the writing process, record the correspondence between the data in each PBA in each Block and the memory data position to form a write information comparison table; Read information table construction module: randomly generates several read commands in batches, randomly selects different PBAs for data reading, stores the read data in a non-conflicting location in the memory, and records the location of the data read in the memory, the location of the PBA, and the length of the read data to form a read information comparison table; Read information table extraction module: After all read commands are sent, the data corresponding to the memory address pointing to the same PBA is compared according to the read information comparison table and the write information comparison table to confirm the correctness of the data.
7. A NAND data correctness check device, comprising a processor and a memory storing program instructions, characterized in that: The processor is configured to execute the NAND data correctness verification method according to any one of claims 1 to 5 when running the program instructions.
8. A computer-readable storage medium, characterized in that: A computer program is stored thereon, and when the program is executed by a processor, the NAND data correctness verification method as described in any one of claims 1 to 5 above is implemented.