Data caching method and device, equipment and medium

Abstract

The invention discloses a data caching method and device, equipment and a medium, and relates to the technical field of storage, and the method comprises the steps: obtaining task operation information sent by a preset processor; wherein the task operation information comprises request information and instruction information corresponding to the to-be-executed task; identifying a function type of the task operation information, and marking the task operation information by using a target label corresponding to the function type to obtain marked task information; sending the marked task information to a preset on-chip bus for transmission, determining a target cache position according to a target label and address information carried in the marked task information, and storing the marked task information to a corresponding target cache block based on the target cache position; and when a preset condition is met, transmitting the marked task information stored in the target cache block to the external equipment through the target bus. According to the invention, the security of data caching can be improved, so that safe and stable operation of equipment is ensured.

Description

Technical Field

[0001] The present invention relates to the field of storage technology, and in particular to a data caching method, device, equipment and medium. Background Art

[0002] In today's technological development, the Internet of Things (IoT) field is booming, and various smart devices are emerging one after another. RISC-V (Reduced Instruction Set Computer V, an open instruction set architecture) architecture has been widely used in the field of IoT chip design due to its many advantages such as open source, simplicity, and customizability. More and more IoT devices choose to build their core chips based on the RISC-V architecture to achieve efficient data processing and flexible function customization.

[0003] However, with the widespread application of RISC-V architecture, data security issues have gradually become prominent. Since the RISC-V architecture design is relatively simple, it is relatively vulnerable to cache packet capture attacks. Cache is an important part of data storage and reading. Once the cache is successfully captured by an attacker, the attacker may be able to control the device's workflow, obtain sensitive information, or even tamper with data, thus posing a serious threat to the security and stability of the device.

[0004] In summary, how to improve the security of data cache to ensure the safe and stable operation of the equipment is a problem that needs to be solved. Summary of the invention

[0005] In view of this, the purpose of the present invention is to provide a data caching method, apparatus, device and medium, which can improve the security of data caching to ensure the safe and stable operation of the device. The specific scheme is as follows:

[0006] In a first aspect, the present application discloses a data caching method, comprising:

[0007] Acquire task operation information sent by a preset processor; wherein the task operation information includes request information and instruction information corresponding to the task to be executed;

[0008] Identifying the function type of the task operation information, and marking the task operation information with a target tag corresponding to the function type to obtain marked task information;

[0009] Sending the marked task information to a preset on-chip bus for transmission, and determining a target cache location according to the target tag and address information carried in the marked task information, so as to store the marked task information in a corresponding target cache block based on the target cache location;

[0010] When a preset condition is met, the marked task information stored in the target cache block is transmitted to an external device through a target bus.

[0011] Optionally, the function type of identifying the task operation information includes:

[0012] If the task operation information is the first type of request information corresponding to the program counter operation, a first function type is obtained;

[0013] If the task operation information is the second type of request information corresponding to the functional logic operation, a second function type is obtained;

[0014] If the task operation information is instruction information, a third function type is obtained;

[0015] If the task operation information is the remaining operation information except the first type of request information, the second type of request information and the instruction information, a fourth function type is obtained.

[0016] Optionally, the bit width of the binary data corresponding to the target tag is 2, wherein the target tag corresponding to the first function type is 01, the target tag corresponding to the second function type is 10, the target tag corresponding to the third function type is 11, and the target tag corresponding to the fourth function type is 00;

[0017] Correspondingly, the step of marking the task operation information with the target tag corresponding to the function type to obtain marked task information includes:

[0018] A target label corresponding to the function type is added to the high bit of the binary data corresponding to the task operation information to obtain labeled task information.

[0019] Optionally, determining the target cache location according to the target tag and address information carried in the marked task information includes:

[0020] Acquire the target tag carried in the marked task information, and determine high-bit information of binary data corresponding to the target tag, so as to determine a target storage group matching the high-bit information from all storage groups;

[0021] Acquire the address information carried in the marked task information, and determine the low-bit information of the binary data corresponding to the address information, so as to determine the target storage path matching the low-bit information from all storage paths;

[0022] A target cache location is determined based on the target storage group and the target storage path.

[0023] Optionally, in the target storage group, each cache position corresponds to a plurality of cache blocks, and the plurality of cache blocks are arranged in ascending order of sequence numbers;

[0024] Correspondingly, storing the marked task information in a corresponding target cache block based on the target cache position includes:

[0025] Determine a plurality of cache blocks corresponding to the target cache location, and obtain a cache block group;

[0026] Determine whether there is a free cache block in the cache block group according to a preset address bit; wherein the preset address bit is used to record the usage of each cache block in the cache block group;

[0027] If there is a free cache block in the cache block group, determining whether the cache space of the free cache block is larger than the data size of the marked task information;

[0028] If it is larger than the data size of the marked task information, a target cache block is determined from the free cache blocks, and the marked task information is stored in the target cache block.

[0029] Optionally, determining a target cache block from the free cache blocks and storing the marked task information in the target cache block includes:

[0030] Determine the number of cache blocks used to store the marked task information according to the data size of the marked task information and the cache size of a single cache block, so as to determine a corresponding number of target cache blocks from the free cache blocks in ascending order of sequence numbers;

[0031] The marked task information is stored in the target cache block in order from high to low.

[0032] Optionally, after determining whether there is a free cache block in the cache block group according to the preset address bit, the method further includes:

[0033] If there is no free cache block in the cache block group, the original task information stored in the cache block group is directly transmitted to the external device through the target bus to obtain a free cache block group, and then jump to the step of determining the target cache block from the free cache blocks and storing the marked task information in the target cache block.

[0034] Optionally, transmitting the marked task information stored in the target cache block to an external device via a target bus includes:

[0035] Determine the data transmission rate and data transmission timing of external devices;

[0036] If the data transmission rate is higher than a preset rate threshold, or if the data transmission timing is higher than a preset transmission timing threshold, the marked task information stored in the target cache block is transmitted to an external device via an advanced high-performance bus, otherwise the marked task information stored in the target cache block is transmitted to an external device via an advanced peripheral bus.

[0037] In a second aspect, the present application discloses a data cache device, comprising:

[0038] An information acquisition module, used to acquire task operation information sent by a preset processor; wherein the task operation information includes request information and instruction information corresponding to the task to be executed;

[0039] a marking module, used for identifying the function type of the task operation information, and marking the task operation information with a target tag corresponding to the function type to obtain marked task information;

[0040] A cache module, used to send the marked task information to a preset on-chip bus for transmission, and determine a target cache location according to the target tag and address information carried in the marked task information, so as to store the marked task information in a corresponding target cache block based on the target cache location;

[0041] The transmission module is used to transmit the marked task information stored in the target cache block to an external device through a target bus when a preset condition is met.

[0042] In a third aspect, the present application discloses an electronic device, comprising:

[0043] Memory, used to store computer programs;

[0044] The processor is used to execute the computer program to implement the steps of the aforementioned disclosed data caching method.

[0045] In a fourth aspect, the present application discloses a computer-readable storage medium for storing a computer program; wherein, when the computer program is executed by a processor, the steps of the aforementioned disclosed data caching method are implemented.

[0046] It can be seen that the present application obtains task operation information sent by a preset processor; wherein the task operation information includes request information and instruction information corresponding to the task to be executed; identifies the functional type of the task operation information, and marks the task operation information with a target tag corresponding to the functional type to obtain marked task information; sends the marked task information to a preset on-chip bus for transmission, and determines a target cache location based on the target tag and address information carried in the marked task information, so as to store the marked task information in a corresponding target cache block based on the target cache location; when a preset condition is met, transmits the marked task information stored in the target cache block to an external device via a target bus.

[0047] Beneficial effect: After obtaining the task operation information sent by the preset processor, the present application needs to identify the functional type of the task operation information, so as to use the target tag corresponding to the functional type to mark the task operation information to obtain the marked task information, wherein the task operation information specifically includes the request information and instruction information corresponding to the task to be executed, that is, the present application will add a new tag on the basis of the original instruction or request, and the tag corresponds to the functional type, and the division of the functional type and the tags corresponding to different functional types can be customized, so as to further protect the request and instruction in the form of a tag. Further, the present application will send the marked task information to the preset on-chip bus for transmission, and determine the target cache location according to the target tag and address information carried in the marked task information, so as to store the marked task information in the corresponding target cache block based on the target cache location. That is, the present application needs to jointly determine the final cache location according to the aforementioned marked target tag and the corresponding address information, not just referring to the address information, and then storing the marked task information in the target cache block corresponding to the target cache location. In this way, data can be cached more scientifically, the security of data cache can be improved, and the safe and stable operation of the device can be guaranteed. Finally, when the preset conditions are met, the marked task information stored in the target cache block is transmitted to the external device through the target bus. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying creative work.

[0049] Figure 1 A flow chart of a data caching method disclosed in this application;

[0050] Figure 2 A schematic diagram of a tag security processing module disclosed in this application;

[0051] Figure 3 This is an architecture diagram applicable to a data caching method disclosed in this application;

[0052] Figure 4 A flow chart of a specific data caching method disclosed in this application;

[0053] Figure 5 A schematic diagram of a cache structure disclosed in this application;

[0054] Figure 6 A schematic diagram of the structure of a data cache device disclosed in this application;

[0055] Figure 7 This is a structural diagram of an electronic device disclosed in this application. DETAILED DESCRIPTION

[0056] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0057] Currently, with the widespread application of RISC-V architecture, data security issues have gradually become prominent. Since the RISC-V architecture design is relatively simple, it is relatively vulnerable to cache packet capture attacks. Cache is an important link in data storage and reading. Once the attacker successfully captures the packet, the attacker may be able to control the workflow of the device, obtain sensitive information, or even tamper with the data, thereby posing a serious threat to the security and stability of the device. To this end, the embodiments of the present application disclose a data caching method, device, equipment and medium, which can improve the security of data caching to ensure the safe and stable operation of the device.

[0058] See also Figure 1 As shown, an embodiment of the present application discloses a data caching method, the method comprising:

[0059] Step S11: Acquire task operation information sent by a preset processor; wherein the task operation information includes request information and instruction information corresponding to the task to be executed.

[0060] In this embodiment, it should be pointed out that the above-mentioned preset processor specifically refers to a core that supports the open source instruction set RISC-V. During the operation of a RISC-V-based system, when various tasks need to be performed, the RISC-V processor will generate corresponding request information or instruction information. For example, when running a data processing program, the processor may issue a request to read data from a specific memory address, or an instruction to perform a certain operation. These requests or instructions carry the operation information required to complete the task.

[0061] Step S12: identifying the function type of the task operation information, and marking the task operation information with a target tag corresponding to the function type to obtain marked task information.

[0062] In this embodiment, a tag security processing module is added to the system. The tag security processing module is mainly used to identify the functional type of task operation information, and mark the task operation information with a target tag corresponding to the functional type to obtain marked task information.

[0063] In a specific implementation, the above-mentioned identification of the function type of the task operation information includes: if the task operation information is the first type of request information corresponding to the program counter operation, then the first function type is obtained; if the task operation information is the second type of request information corresponding to the functional logic operation, then the second function type is obtained; if the task operation information is instruction information, then the third function type is obtained; if the task operation information is the remaining operation information except the first type of request information, the second type of request information and the instruction information, then the fourth function type is obtained. First refer to Figure 2 As shown, Figure 2 This is a schematic diagram of a tag security processing module disclosed in the present application. The tag security processing module may specifically include a Tag label processing module, a PC (Program Counter) counting module, a functional logic module and an instruction module. The Tag label processing module receives requests or instructions from a RISC-V processor, and works in conjunction with the PC counting module, the functional logic module and the instruction module to identify and analyze the input requests or instructions and tag them.

[0064] The specific provisions of this embodiment are: if the task operation information is the first type of request information corresponding to the program counter operation, its function type is the first function type; if the task operation information is the second type of request information corresponding to the functional logic operation, its function type is the second function type; if the task operation information is instruction information, its function type is the third function type; if the task operation information is the remaining operation information except the first type of request information, the second type of request information and the instruction information, its function type is the fourth function type.

[0065] Specifically, the bit width of the binary data corresponding to the above target tag is 2, wherein the target tag corresponding to the first function type is 01, the target tag corresponding to the second function type is 10, the target tag corresponding to the third function type is 11, and the target tag corresponding to the fourth function type is 00. In this embodiment, the bit width currently set for the target tag is 2 bits, specifically represented as: 01 for PC counting, 10 for functional logic, 11 for instructions, 00 for others, and 00 also indicates that the function is not tagged. That is, if it is a counting operation related to the program counter, the target tag is 01; if it belongs to functional logic operations, such as addition, subtraction, multiplication and division, the target tag is 10; for simple instructions, the target tag is 11; and 00 indicates that the function is not tagged or belongs to other undefined classifications. In addition, the bit width of the Tag can also be increased according to the degree of subdivision of the function, such as subdividing the logical function module into addition, subtraction, multiplication and division. This embodiment does not limit the bit width of the target tag.

[0066] Specifically, the above-mentioned use of the target tag corresponding to the function type to mark the task operation information to obtain the marked task information includes: adding the target tag corresponding to the function type to the high bit of the binary data corresponding to the task operation information to obtain the marked task information. That is, after determining the target tag corresponding to the function type, the specific way of marking is to add a 2-bit target tag to the high bit of the original instruction or request. For example, the original instruction code is 10101100. If it is identified as a functional logic operation, it becomes 1010110010 after adding the tag, thereby completing the label adding process and realizing the distinction and marking of different types of requests or instructions.

[0067] Step S13: Send the marked task information to a preset on-chip bus for transmission, and determine a target cache location according to the target tag and address information carried in the marked task information, so as to store the marked task information in a corresponding target cache block based on the target cache location.

[0068] Furthermore, the present application will send the marked task information to the preset on-chip bus for transmission, and determine the target cache location based on the target tag and address information carried in the marked task information, so as to store the marked task information in the corresponding target cache block based on the target cache location. That is, the present application needs to jointly determine the final cache location based on the aforementioned marked target tag and the corresponding address information, rather than just referring to the address information, and then storing the marked task information in the target cache block corresponding to the target cache location. In this way, data can be cached more scientifically, and the security of data caching can be improved to ensure the safe and stable operation of the device.

[0069] Specifically, Figure 3 As shown in the architecture diagram, the tagged task information will be sent through the on-chip bus according to the AXI (Advanced eXtensible Interface) protocol. The AXI protocol is an efficient on-chip bus protocol that ensures reliable and fast transmission of instructions between different modules inside the chip. During the transmission process, the target tag information will be passed along with the instruction or request, so that the subsequent modules can understand the key information such as the type and source of the instruction or request based on the tag, so as to perform corresponding processing and operations.

[0070] Step S14: when a preset condition is met, the marked task information stored in the target cache block is transmitted to an external device via a target bus.

[0071] In this embodiment, when a preset condition is met, the marked task information stored in the target cache block is transmitted to the external device through the target bus.

[0072] Specifically, the above-mentioned transmitting the marked task information stored in the target cache block to the external device through the target bus includes: determining the data transmission rate and data transmission timing of the external device; if the data transmission rate is higher than a preset rate threshold, or if the data transmission timing is higher than a preset transmission timing threshold, then transmitting the marked task information stored in the target cache block to the external device through an advanced high-performance bus, otherwise transmitting the marked task information stored in the target cache block to the external device through an advanced peripheral bus.

[0073] That is, if Figure 3As shown, when it is necessary to interact with external devices, the appropriate bus will be selected for transmission according to the frequency and timing requirements of the peripherals. Specifically, the data transmission rate can be compared with the corresponding preset rate threshold, and the data transmission timing can be compared with the corresponding preset transmission timing threshold. For high-speed peripherals with high timing requirements or high frequency requirements, the Advanced High-performance Bus (AHB) is used to transmit off-chip information; for low-speed peripherals with low frequency requirements and relatively loose timing, the Advanced Peripheral Bus (APB) with lower code complexity is used to transmit off-chip information. Such a design can reduce the load of the entire chip system and ensure that higher-frequency interfaces are allocated to more on-chip resources for information transmission. At the same time, high-speed peripherals and low-speed peripherals can receive and send data, and transmit them to the CPU through the bus. During the transmission process, the data will carry relevant control information and address information to ensure that the peripherals can correctly receive and process the data. For example, when sending image data to a display peripheral, the data will be sent to the display's cache line by line or block by block through the AHB bus in accordance with specific transmission formats and timing requirements for display by the display; while for a simple sensor control signal, it can be transmitted through the APB bus at a lower frequency and simple timing to implement sensor configuration or trigger operations.

[0074] It can be seen that, after obtaining the task operation information sent by the preset processor, the present application needs to identify the functional type of the task operation information, so as to use the target tag corresponding to the functional type to mark the task operation information to obtain the marked task information, wherein the task operation information specifically includes the request information and instruction information corresponding to the task to be executed, that is, the present application will add a new tag on the basis of the original instruction or request, and the tag corresponds to the functional type, and the division of the functional type and the tags corresponding to different functional types can be customized, so as to further protect the request and instruction in the form of a tag. Further, the present application will send the marked task information to the preset on-chip bus for transmission, and determine the target cache position according to the target tag and address information carried in the marked task information, so as to store the marked task information in the corresponding target cache block based on the target cache position. That is, the present application needs to jointly determine the final cache position according to the aforementioned marked target tag and the corresponding address information, not just referring to the address information, and then storing the marked task information in the target cache block corresponding to the target cache position. In this way, data can be cached more scientifically, and the security of data cache can be improved to ensure the safe and stable operation of the device. Finally, when the preset conditions are met, the marked task information stored in the target cache block is transmitted to the external device through the target bus.

[0075] See also Figure 4 As shown, the embodiment of the present application discloses a specific data caching method. Compared with the previous embodiment, this embodiment further explains and optimizes the technical solution. Specifically, it includes:

[0076] Step S21: Acquire task operation information sent by a preset processor; wherein the task operation information includes request information and instruction information corresponding to the task to be executed.

[0077] Step S22: Identify the function type of the task operation information, and use the target tag corresponding to the function type to mark the task operation information to obtain marked task information, and then send the marked task information to a preset on-chip bus for transmission.

[0078] Step S23: Acquire the target tag carried in the marked task information, and determine the high-order information of the binary data corresponding to the target tag, so as to determine the target storage group matching the high-order information from all storage groups.

[0079] In this embodiment, it should be pointed out that when storing data, it will be stored in the corresponding cache location according to the target tag and address information carried by the marked task information. For the entire system, the cache of the entire system is classified into L0 cache (cache) and L1 cache. L0 cache is a common instruction cache and data cache with a high transmission speed and very small capacity. L0 cache is integrated into the Risc-V core and is no different from ordinary ones, so it is not included in the cache. Figure 3 As indicated above, the improved part of this application is L1 cache, which is mainly to integrate Tag Cache as an independent functional module with L1 Cache. Different from the ordinary cache module, the storage of the entire data is more disordered. This embodiment indexes the entire L1 cache by set (i.e. storage group) and way (i.e. storage path), and the storage block is called Bank. Figure 5 As shown, the indexing method of the set is through the target tag. It should be pointed out that, for the sake of ease of explanation, this embodiment only adopts the indexing method of a 2-bit tag width. In fact, as the cache scale increases, the tag width can also be the same as mentioned above, thereby enhancing the index range of the entire cache unit. Figure 5 Specifically, it includes two storage groups, namely set0 and set1.

[0080] Therefore, when storing data, it is necessary to obtain the target tag carried in the task information after marking, and determine the high-bit information of the binary data corresponding to the target tag, so as to determine the target storage group that matches the high-bit information from all storage groups. The specific indexing method is as follows: when the target tag is 00 or 01, the high-bit 0 of the tag is selected, and the data enters the corresponding set0 module; when the tag is 10 or 11, the high-bit 1 of the tag is selected, and the data enters the corresponding set1 module. For the enhanced indexing method, if the tag is 3 bits, the high 2 bits can be used for indexing, and then 4 storage blocks can be designed.

[0081] Step S24: Acquire the address information carried in the marked task information, and determine the low-order information of the binary data corresponding to the address information, so as to determine the target storage path matching the low-order information from all storage paths.

[0082] In this embodiment, for the indexing method of the storage path way, the lower 4 bits of the address information are used for indexing, from 0000 to 1111, corresponding to way0000 to way1111 in the bank respectively, that is, Figure 5 Therefore, it is necessary to obtain the address information carried in the marked task information and determine the low-bit information of the binary data corresponding to the address information, so as to determine the target storage path matching the low-bit information from all storage paths.

[0083] Step S25: determining a target cache location based on the target storage group and the target storage path, so as to store the marked task information into a corresponding target cache block based on the target cache location.

[0084] In this embodiment, after the corresponding target storage group is determined based on the tag information and the corresponding target storage path is determined based on the address information, the target cache location can be determined, that is, which storage path in which storage group should be stored.

[0085] Specifically, in the target storage group, each cache location corresponds to a plurality of cache blocks, and the plurality of cache blocks are arranged in ascending order of sequence numbers. Figure 5 As shown, each cache location corresponds to 8 cache blocks (Bank), and multiple cache blocks are arranged in sequence from 0 to 7. Each storage block has a storage path way0000-way1111.

[0086] Correspondingly, the above-mentioned storing the marked task information to the corresponding target cache block based on the target cache position includes: determining multiple cache blocks corresponding to the target cache position and obtaining a cache block group; judging whether there is a free cache block in the cache block group according to a preset address bit; wherein the preset address bit is used to record the usage of each cache block in the cache block group; if there is a free cache block in the cache block group, judging whether the cache space of the free cache block is larger than the data size of the marked task information; if it is larger than the data size of the marked task information, determining the target cache block from the free cache blocks, and storing the marked task information to the target cache block.

[0087] That is, the present application also needs to determine the corresponding target cache block based on the target cache position. Specifically, first determine the multiple cache blocks corresponding to the target cache position, and obtain a cache block group. For example, the storage path way1111 should be stored in the storage group set0, then find Bank0-Bank7 corresponding to way1111 in set0 to obtain a cache block group. In addition, the present application will use the preset address bits to record the usage of each cache block in the cache block group. For 8 cache blocks, the preset address bits are also 8 bits. For example, when the preset address bits are 00000000, it means that the 8 cache blocks are all idle. If the preset address bits are 11111111, it means that the 8 cache blocks have been used and there are no idle cache blocks. If the preset address bits are 00001111, it means that Bank0-Bank3 are idle and Bank4-Bank7 are in use. Therefore, this application needs to determine whether there is a free cache block in the cache block group based on whether the preset address bit currently has a 0 value. When there is a free cache block, it is also necessary to determine whether the cache space of the free cache block is larger than the data size of the marked task information. It should be pointed out that the storage space of each way in the Bank is 32 bits, and 8 banks can theoretically support the storage of data with a bit width of 32×8. If the cache space of the free cache block is larger than the data size of the marked task information, the target cache block is determined from the free cache blocks, and the marked task information is stored in the target cache block.

[0088] Specifically, the above-mentioned determining the target cache block from the free cache blocks and storing the marked task information in the target cache block includes: determining the number of cache blocks used to store the marked task information according to the data size of the marked task information and the cache size of a single cache block, so as to determine a corresponding number of target cache blocks from the free cache blocks in order from small to large sequence numbers; and storing the marked task information in the target cache block in sequence from high to low sequence numbers.

[0089] That is, the present application needs to determine how many cache blocks are needed to store the marked task information. Specifically, the data size of the marked task information and the cache size of a single cache block can be calculated to obtain quantity information, and then the corresponding number of target cache blocks are determined from the free cache blocks in order of sequence numbers from small to large, and the marked task information is further stored in the target cache blocks in order from high to low. For example, when cache blocks Bank0-Bank7 are all idle, assuming that the data size of the marked task information is 64 bits, the data will first be stored in the corresponding way in bank0 by default, and then the bank pointer will point to the next bank with the same way value, the high 32 bits of data will be placed in bank0, and the low 32 bits of data will be placed in bank1. It should be noted that the process of placing data in different banks occurs at the same clock, that is, bank0 and bank1 are written in parallel.

[0090] In this way, the above scheme allows data to be split by address information and target tags, and stored in different locations of each cache block. Even if the cached data stream is captured, the captured data is completely chaotic and cannot be restored. In this way, it can be used to protect the data security of IoT devices based on Risc-V. And with the help of the definition and classification index of the above tags, the placement and placement of data can be customized, so that while caching data, the data flow can be guaranteed to be stable and the problem of data loss can be prevented. At the same time, the hierarchical storage scheme is more capable of ensuring data security.

[0091] Furthermore, after judging whether there is a free cache block in the cache block group according to the preset address bit, it also includes: if there is no free cache block in the cache block group, the original task information stored in the cache block group is directly transmitted to the external device through the target bus to obtain a free cache block group, and then jump to the step of determining the target cache block from the free cache block and storing the marked task information in the target cache block. That is, if the preset address is 11111111, all 8 cache blocks have been used. In this case, this embodiment adopts the "write-through" strategy, that is, dirty bit data is not used for marking, but directly sent to the corresponding interface or register unit, and the data will replace the previous data, and the previously stored data will be sent out from the cache. That is, at this time, the original task information stored in the cache block group is directly transmitted to the external device through the target bus to obtain a free cache block group. In addition, the cache will initiate the highest level request to the bus, suspend the current transmission, wait for the data replacement to be completed, and send the old data first. After the data replacement is completed, the data transmission will continue, that is, at this time, it will jump to the step of determining the target cache block from the free cache block and storing the marked task information in the target cache block. Although this will cause the bus to pause, considering that the amount of IoT data is not large and the transmission frequency is relatively low, it will not cause much impact on the transmission speed of the L1 cache. The purpose of this is to ensure data security and data loss without losing data, and to ensure the stability of data timing.

[0092] Step S26: When a preset condition is met, the marked task information stored in the target cache block is transmitted to an external device via a target bus.

[0093] For more specific processing procedures of the above steps S21, S22 and S26, reference may be made to the corresponding contents disclosed in the aforementioned embodiments, which will not be described in detail here.

[0094] It can be seen that in this application, the storage of the entire data is more disordered. This embodiment indexes the entire L1 cache by set (i.e. storage group) and way (i.e. storage path). On the one hand, it is necessary to obtain the target tag carried in the task information after marking, and determine the matching target storage group from all storage groups according to the high-bit information of the binary data corresponding to the target tag; on the other hand, it is necessary to obtain the address information carried in the task information after marking, and determine the matching target storage path from all storage paths according to the low-bit information of the binary data corresponding to the address information. After determining the corresponding target storage group based on the tag information and determining the corresponding target storage path based on the address information, the target cache position can be determined, that is, which storage path in which storage group should be stored. In addition, in the target storage group, each cache position also corresponds to multiple cache blocks, and the multiple cache blocks are arranged in a sequence number from small to large. Therefore, this application also needs to determine the target cache block that is ultimately used to store data. When there is no free cache block, a write-through strategy is adopted to first suspend the current transmission, wait for the data replacement to be completed, and send the old data first. After waiting for the data replacement to be completed, the data transmission will continue. In this way, even if the cached data stream is captured, the captured data is completely chaotic and there is no way to restore it. In this way, it can be used to protect the data security of Risc-V-based IoT devices.

[0095] See also Figure 6 As shown, an embodiment of the present application discloses a data cache device, which includes:

[0096] The information acquisition module 11 is used to acquire the task operation information sent by the preset processor; wherein the task operation information includes request information and instruction information corresponding to the task to be executed;

[0097] A marking module 12, used for identifying the function type of the task operation information, and marking the task operation information with a target tag corresponding to the function type to obtain marked task information;

[0098] The cache module 13 is used to send the marked task information to a preset on-chip bus for transmission, and determine a target cache location according to the target tag and address information carried in the marked task information, so as to store the marked task information in a corresponding target cache block based on the target cache location;

[0099] The transmission module 14 is used to transmit the marked task information stored in the target cache block to an external device through a target bus when a preset condition is met.

[0100] It can be seen that, after obtaining the task operation information sent by the preset processor, the present application needs to identify the functional type of the task operation information, so as to use the target tag corresponding to the functional type to mark the task operation information to obtain the marked task information, wherein the task operation information specifically includes the request information and instruction information corresponding to the task to be executed, that is, the present application will add a new tag on the basis of the original instruction or request, and the tag corresponds to the functional type, and the division of the functional type and the tags corresponding to different functional types can be customized, so as to further protect the request and instruction in the form of a tag. Further, the present application will send the marked task information to the preset on-chip bus for transmission, and determine the target cache position according to the target tag and address information carried in the marked task information, so as to store the marked task information in the corresponding target cache block based on the target cache position. That is, the present application needs to jointly determine the final cache position according to the aforementioned marked target tag and the corresponding address information, not just referring to the address information, and then storing the marked task information in the target cache block corresponding to the target cache position. In this way, data can be cached more scientifically, and the security of data cache can be improved to ensure the safe and stable operation of the device. Finally, when the preset conditions are met, the marked task information stored in the target cache block is transmitted to the external device through the target bus.

[0101] Since the embodiments of the device part correspond to the embodiments of the method part, the embodiments of the device part refer to the description of the embodiments of the method part, which will not be described here. In addition, the invention has the same beneficial effects as the above-mentioned data caching method.

[0102] Figure 7 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. Specifically, it may include: at least one processor 21, at least one memory 22, a power supply 23, a communication interface 24, an input / output interface 25, and a communication bus 26. The memory 22 is used to store a computer program, which is loaded and executed by the processor 21 to implement the relevant steps in the data caching method performed by the electronic device disclosed in any of the aforementioned embodiments.

[0103] In this embodiment, the power supply 23 is used to provide working voltage for each hardware device on the electronic device 20; the communication interface 24 can create a data transmission channel between the electronic device 20 and the external device, and the communication protocol it follows is any communication protocol that can be applied to the technical solution of the present application, and is not specifically limited here; the input and output interface 25 is used to obtain external input data or output data to the outside world, and its specific interface type can be selected according to specific application needs and is not specifically limited here.

[0104] Among them, the processor 21 may include one or more processing cores, such as a 4-core processor, an 8-core processor, etc. The processor 21 can be implemented in at least one hardware form of DSP (Digital Signal Processing), FPGA (Field-Programmable Gate Array), and PLA (Programmable Logic Array). The processor 21 may also include a main processor and a coprocessor. The main processor is a processor for processing data in the awake state, also known as a CPU (Central Processing Unit); the coprocessor is a low-power processor for processing data in the standby state. In some embodiments, the processor 21 may be integrated with a GPU (Graphics Processing Unit), which is responsible for rendering and drawing the content to be displayed on the display screen. In some embodiments, the processor 21 may also include an AI (Artificial Intelligence) processor, which is used to process computing operations related to machine learning.

[0105] In addition, the memory 22, as a carrier for storing resources, can be a read-only memory, a random access memory, a disk or an optical disk, etc. The resources stored thereon include an operating system 221, a computer program 222 and data 223, etc. The storage method can be temporary storage or permanent storage.

[0106] Among them, the operating system 221 is used to manage and control the hardware devices and computer programs 222 on the electronic device 20, so as to realize the operation and processing of the processor 21 on the massive data 223 in the memory 22, which can be Windows, Unix, Linux, etc. In addition to including a computer program that can be used to complete the data caching method performed by the electronic device 20 disclosed in any of the aforementioned embodiments, the computer program 222 can further include a computer program that can be used to complete other specific tasks. In addition to data received by the electronic device and transmitted from an external device, the data 223 can also include data collected by its own input and output interface 25, etc.

[0107] Furthermore, an embodiment of the present application also discloses a computer-readable storage medium, in which a computer program is stored. When the computer program is loaded and executed by a processor, the steps of the data caching method disclosed in any of the aforementioned embodiments are implemented.

[0108] In this specification, each embodiment is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part.

[0109] Those skilled in the art may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented with electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in terms of function in the above description. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art may use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0110] The steps of the method or algorithm described in conjunction with the embodiments disclosed herein may be implemented directly using hardware, a software module executed by a processor, or a combination of the two. The software module may be placed in a random access memory (RAM), a memory, a read-only memory (ROM), an electrically programmable ROM, an electrically erasable programmable ROM, a register, a hard disk, a removable disk, a compact disc read-only memory (CD-ROM), or any other form of storage medium known in the art.

[0111] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0112] The above is a detailed introduction to a data caching method, device, equipment and storage medium provided by the present invention. Specific examples are used in this article to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea; at the same time, for general technical personnel in this field, according to the idea of ​​the present invention, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present invention.

Claims

1. A data caching method, characterized in that: include: Acquire task operation information sent by a preset processor; wherein the task operation information includes request information and instruction information corresponding to the task to be executed; Identifying the function type of the task operation information, and marking the task operation information with a target tag corresponding to the function type to obtain marked task information; Sending the marked task information to a preset on-chip bus for transmission, and determining a target cache location according to the target tag and address information carried in the marked task information, so as to store the marked task information in a corresponding target cache block based on the target cache location; When a preset condition is met, the marked task information stored in the target cache block is transmitted to an external device through a target bus.

2. The data caching method according to claim 1, characterized in that: The function type of identifying the task operation information includes: If the task operation information is the first type of request information corresponding to the program counter operation, a first function type is obtained; If the task operation information is the second type of request information corresponding to the functional logic operation, a second function type is obtained; If the task operation information is instruction information, a third function type is obtained; If the task operation information is the remaining operation information except the first type of request information, the second type of request information and the instruction information, a fourth function type is obtained.

3. The data caching method according to claim 2, characterized in that: The bit width of the binary data corresponding to the target tag is 2, wherein the target tag corresponding to the first function type is 01, the target tag corresponding to the second function type is 10, the target tag corresponding to the third function type is 11, and the target tag corresponding to the fourth function type is 00; Correspondingly, the step of marking the task operation information with the target tag corresponding to the function type to obtain marked task information includes: A target label corresponding to the function type is added to the high bit of the binary data corresponding to the task operation information to obtain labeled task information.

4. The data caching method according to claim 1, characterized in that: The determining the target cache location according to the target tag and address information carried in the marked task information includes: Acquire the target tag carried in the marked task information, and determine high-bit information of binary data corresponding to the target tag, so as to determine a target storage group matching the high-bit information from all storage groups; Acquire the address information carried in the marked task information, and determine the low-bit information of the binary data corresponding to the address information, so as to determine the target storage path matching the low-bit information from all storage paths; A target cache location is determined based on the target storage group and the target storage path.

5. The data caching method according to claim 4, characterized in that: In the target storage group, each cache position corresponds to a plurality of cache blocks, and the plurality of cache blocks are arranged in ascending order of sequence numbers; Correspondingly, storing the marked task information in a corresponding target cache block based on the target cache position includes: Determine a plurality of cache blocks corresponding to the target cache location, and obtain a cache block group; Determine whether there is a free cache block in the cache block group according to a preset address bit; wherein the preset address bit is used to record the usage of each cache block in the cache block group; If there is a free cache block in the cache block group, determining whether the cache space of the free cache block is larger than the data size of the marked task information; If it is larger than the data size of the marked task information, a target cache block is determined from the free cache blocks, and the marked task information is stored in the target cache block.

6. The data caching method according to claim 5, characterized in that: The step of determining a target cache block from the free cache blocks and storing the marked task information in the target cache block includes: Determine the number of cache blocks used to store the marked task information according to the data size of the marked task information and the cache size of a single cache block, so as to determine a corresponding number of target cache blocks from the free cache blocks in ascending order of sequence numbers; The marked task information is stored in the target cache block in order from high to low.

7. The data caching method according to claim 5, characterized in that: After determining whether there is a free cache block in the cache block group according to the preset address bit, the method further includes: If there is no free cache block in the cache block group, the original task information stored in the cache block group is directly transmitted to the external device through the target bus to obtain a free cache block group, and then jump to the step of determining the target cache block from the free cache blocks and storing the marked task information in the target cache block.

8. The data caching method according to any one of claims 1 to 7, characterized in that: The step of transmitting the marked task information stored in the target cache block to an external device via a target bus includes: Determine the data transmission rate and data transmission timing of external devices; If the data transmission rate is higher than a preset rate threshold, or if the data transmission timing is higher than a preset transmission timing threshold, the marked task information stored in the target cache block is transmitted to an external device via an advanced high-performance bus, otherwise the marked task information stored in the target cache block is transmitted to an external device via an advanced peripheral bus.

9. A data cache device, characterized in that: include: An information acquisition module, used to acquire task operation information sent by a preset processor; wherein the task operation information includes request information and instruction information corresponding to the task to be executed; a marking module, used for identifying the function type of the task operation information, and marking the task operation information with a target tag corresponding to the function type to obtain marked task information; A cache module, used to send the marked task information to a preset on-chip bus for transmission, and determine a target cache location according to the target tag and address information carried in the marked task information, so as to store the marked task information in a corresponding target cache block based on the target cache location; The transmission module is used to transmit the marked task information stored in the target cache block to an external device through a target bus when a preset condition is met.

10. An electronic device, characterized in that: include: Memory, used to store computer programs; A processor, configured to execute the computer program to implement the steps of the data caching method according to any one of claims 1 to 8.

11. A computer-readable storage medium, characterized in that: Used to store computer programs; wherein, when the computer program is executed by a processor, the steps of the data caching method according to any one of claims 1 to 8 are implemented.

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