A Cross-Clock Domain Data Latching System and Method

Abstract

The present application relates to a cross-clock-domain data latching system, which includes a first clock domain module configured to generate a first signal representing the data update of the first clock domain that conforms to the clock frequency of the first clock domain; a latching module coupled to the first clock domain module, which includes one or more latches and is configured to receive data from the first clock domain module and latch it; a second clock domain module coupled to the latching module and configured to generate a second signal representing that the data in the latching module is about to be read, which conforms to the clock frequency of the second clock domain, wherein the clock frequency of the second clock domain is higher than that of the first clock domain. The present application also relates to an electronic device. The present application also relates to a cross-clock-domain data latching method. The present application is directed to the scenario of cross-clock domains and reduces the probability and negative impact of metastability.

Description

Technical Field

[0001] This application relates to the field of semiconductors, and particularly to a cross-clock domain data latch system and method. Background Art

[0002] In modern integrated circuit (IC) design, especially in the design of high-integration system-on-chip (SoC), cross-clock domain data processing (Clock Domain Crossing, CDC) is a crucial and complex issue. With the increasing complexity of chip functions and the diversification of clock networks, the number of cross-clock domain interfaces is constantly increasing. How to effectively process these asynchronous signals has become the key to ensuring the stability and reliability of the system.

[0003] When a signal crosses from one clock domain to another, if not properly processed, metastability is very likely to occur. Metastability refers to a state where the output of a circuit element is in an uncertain state. This uncertain state may be between the high level and the low level, manifested as the output signal level fluctuating around an intermediate value. This uncertain output will cause subsequent logic circuits to receive incorrect signals and may also lead to serious system failures. Therefore, avoiding the occurrence of metastability is very important in cross-clock domain data processing.

[0004] Although the occurrence of metastability cannot be completely avoided, its occurrence probability and negative impact can be reduced through reasonable design means.

[0005] According to the prior art, a multi-stage synchronizer can be used to reduce the impact of metastability. By setting multiple cascaded flip-flops in the user clock domain to receive data from the master clock domain. However, in the case where the user clock is much faster than the master clock, for example, in an application scenario where the user clock frequency is greater than twice the master clock frequency, this method has certain defects. Using strategies such as synchronizers, handshakes, or first-in-first-out (FIFO) cannot meet the requirements because when the user issues a read command, due to the slower master clock and the large synchronization logic delay, the data read by the user is incomplete or incorrect.

[0006] Therefore, a reliable way is needed to achieve data latching from the master clock domain to the user clock domain. Summary of the Invention

[0007] In view of the technical problems existing in the prior art, the present application proposes a cross-clock-domain data latching system, including: a first clock domain module configured to generate a first signal representing the update of data in the first clock domain that conforms to the clock frequency of the first clock domain; a latching module coupled to the first clock domain module, which includes one or more latches and is configured to receive and latch data from the first clock domain module; a second clock domain module coupled to the latching module and configured to generate a second signal representing the upcoming reading of the data in the latching module that conforms to the clock frequency of the second clock domain, wherein the clock frequency of the second clock domain is higher than that of the first clock domain; wherein, the first clock domain module at least includes a first latching signal generating unit coupled to the second clock domain module and configured to receive the first signal and the second signal and generate a first latching signal based on the first signal and the second signal; a buffer unit coupled to the first latching signal generating unit, and when the first latching signal is valid, configured to widen the first latching signal to generate a second latching signal and provide it to the latching module, and the latching module is configured to update its latched data to the current data in the first clock domain, wherein the pulse width of the second latching signal is greater than or equal to the minimum latching pulse width of the latching module.

[0008] Specifically, in the cross-clock-domain data latching system proposed by the present application, when the first latching signal is invalid, the output of the buffer unit is invalid, and the latching module is configured not to update the data it latches.

[0009] Specifically, in the cross-clock-domain data latching system proposed by the present application, the first latching signal generating unit at least includes a NOT gate, the input end of which is configured to receive the second signal; an AND gate, the first input end of which is coupled to the output end of the NOT gate, the second input end of which is configured to receive the first signal, and the output end of which is coupled to the buffer unit.

[0010] Specifically, in the cross-clock-domain data latching system proposed by the present application, the buffer unit includes at least one buffer sub-unit; wherein the buffer sub-unit includes: a first buffer, the input end of which is coupled to the first latching signal generating unit and is configured to receive the first latching signal; an OR gate, the first input end of which is coupled to the output end of the first buffer, the second input end of which is coupled to the input end of the first buffer, and the output end of which is coupled to the output end of the buffer unit.

[0011] Specifically, in the cross-clock-domain data latching system proposed by the present application, the buffer unit further includes a filtering sub-unit, which is coupled between the first latching signal generating unit and the first buffer sub-unit and is configured to filter out the first latching signals with a pulse width less than a preset pulse width.

[0012] Specifically, for the cross-clock-domain data latch system proposed in this application, the preset pulse width adopted by the filtering subunit is at least related to the maximum latch pulse width of each latch in the latch module.

[0013] Specifically, for the cross-clock-domain data latch system proposed in this application, the preset pulse width is also related to the driving pulse width and the number of the first buffers.

[0014] Specifically, for the cross-clock-domain data latch system proposed in this application, the filtering subunit is a second buffer, and its driving pulse width is greater than that of the first buffer.

[0015] This application also proposes an electronic device, including the above-mentioned cross-clock-domain data latch system.

[0016] This application also proposes a cross-clock-domain data latching method, including: when a first signal representing the update of the first clock domain data is valid and a second signal representing the upcoming reading of the latched data is invalid, generating a first latch signal based on the first signal and the second signal, broadening the first latch signal to generate a second latch signal that meets the latch pulse width, and using the current first clock domain data to update the latched data.

[0017] Specifically, for the cross-clock-domain data latching method proposed in this application, it also includes that when the first signal is valid and the second signal is also valid, the latched data is not updated.

[0018] Specifically, for the cross-clock-domain data latching method proposed in this application, it also includes filtering the first latch signal first and then broadening the filtered signal to obtain the second latch signal.

[0019] For the cross-clock-domain scenario, this application ensures that the data remains stable when the user reads it, and at the same time reduces the probability and negative impact of metastability. Especially in the application scenario where the user clock frequency is more than twice the main clock frequency, this application can quickly complete the latching of the latest data after the signal representing the update of the main clock domain data is generated. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Next, the preferred embodiments of this application will be further described in detail with reference to the drawings, where:

[0021] Figure 1 is a schematic diagram of a cross-clock-domain data latch system according to an embodiment of this application;

[0022] Figure 2 is a timing schematic diagram of the working signals of a cross-clock-domain data latch system according to an embodiment of this application;

[0023] Figure 3 It is a timing diagram of the working signals of a cross-clock-domain data latch system according to an embodiment of the present application;

[0024] Figure 4 It is a timing diagram of the working signals of a cross-clock-domain data latch system according to an embodiment of the present application;

[0025] Figure 5 It is a flowchart of a cross-clock-domain data latching method according to an embodiment of the present application. Detailed implementation manners

[0026] To make the objectives, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Apparently, the described embodiments are some but not all of the embodiments of the present application. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present application without creative efforts shall fall within the protection scope of the present application.

[0027] In the following detailed description, reference may be made to the various specification drawings that form a part of the present application and illustrate specific embodiments of the present application. In the drawings, like reference numerals generally describe substantially similar components in different figures. The various specific embodiments of the present application are described in sufficient detail below to enable those of ordinary skill in the relevant art to implement the technical solutions of the present application. It should be understood that other embodiments may also be utilized or structural, logical or electrical changes may be made to the embodiments of the present application.

[0028] For technologies, methods and devices known to those of ordinary skill in the relevant art, they may not be discussed in detail, but where appropriate, the said technologies, methods and devices should be regarded as part of the description. Regarding the connections between the units in the drawings, it is only for the convenience of description, which indicates that at least the units at both ends of the connection communicate with each other, and it is not intended to limit that the units not connected cannot communicate. In addition, the number of lines between two units is intended to represent at least the number of signals involved in the communication between the two units or at least the number of output terminals, and it is not used to limit that the two units can only communicate with the signals shown in the figure.

[0029] In the following detailed description, high level is defined as valid and low level is defined as invalid for introduction. Based on the solution of the present application, the transformation of defining the valid or invalid state of the signal in the opposite way also belongs to the protection scope of the present application.

[0030] Figure 1 It is a schematic diagram of a cross-clock-domain data latch system according to an embodiment of the present application.

[0031] According to one embodiment, a cross-clock domain data latching system may include a master clock domain module 10, a user clock domain module 11, and a latching module 12 coupled therebetween.

[0032] According to one embodiment, the master clock domain module 10 may include a first latching signal generation unit 101.

[0033] According to one embodiment, the first latching signal generation unit 101 may be configured to receive update_main. update_main is a signal representing data update in the master clock domain module 10. According to one embodiment, the signal width of update_main may be at least one master clock cycle.

[0034] According to one embodiment, the first latching signal generation unit 101 may also be configured to receive read_user. read_user is a signal representing that data in the latching module is about to be read, indicating that the user will read the data in the latching module 12 in the next user clock cycle. read_user may remain high during the user's data reading process.

[0035] According to one embodiment, the first latching signal generation unit 101 may include at least one NOT gate 1011 and one AND gate 1012. The NOT gate 1011 is configured to receive read_user, and its output terminal is electrically connected to the first input terminal of the AND gate 1012. The second input terminal of the AND gate 1012 is configured to receive update_main. The output terminal of the AND gate 1012 is configured to output latch_en_temp. According to one embodiment, when update_main is valid and read_user is invalid, latch_en_temp is valid. When the user is reading, read_user is valid, and at this time, regardless of whether update_main is valid, the output signal latch_en_temp is invalid, and the data is not updated, ensuring data stability during user reading.

[0036] According to one embodiment, the master clock domain module 10 may further include a buffer unit 102. According to one embodiment, the buffer unit 102 may be configured to widen latch_en_temp to obtain latch_en. The reason for widening latch_en_temp is to ensure that latch_en meets the minimum pulse width requirement of the latching module 12. If the minimum pulse width requirement of the latching module 12 is not met, it may cause the data to not be properly latched.

[0037] According to one embodiment, the buffer unit 102 may include a plurality of buffer subunits 1021. Each of the buffer subunits 1021 is capable of delaying the signal it receives by a certain amount of time. Therefore, latch_en_temp is successively delayed by the plurality of buffer subunits 1021, and the resulting latch_en is equivalent to latch_en_temp being widened, and the total width of the widening is the sum of the delay times of the respective buffer subunits.

[0038] According to one embodiment, each buffer subunit 1021 may include at least one buffer 10211, whose input terminal is configured to receive latch_en_temp or buffered latch_en_temp, and whose output terminal is coupled to the first input terminal of the OR gate 10212. The other input terminal of the OR gate 10212 is configured to receive latch_en_temp or buffered latch_en_temp.

[0039] According to another embodiment, latch_en_temp with too small a pulse width still cannot meet the minimum pulse width requirement of the latch module after being widened. To avoid this situation, the buffer unit 102 may also be configured to filter latch_en_temp that still does not meet the minimum pulse width requirement of the latch module 12 after being widened. Since there are some slight differences between the minimum latch pulse widths of different latches in the latch module 12, the input signal latch_en_temp is filtered to ensure that the pulse width of the widened latch_en must be greater than a certain length to ensure that all latches work simultaneously, otherwise it will cause some latches to work and some latches not to work, resulting in latch data errors. Therefore, optionally, according to one embodiment, the buffer unit 102 may further include a filtering subunit 1022, whose input terminal is configured to receive the first latch signal latch_en_temp, and whose output terminal is coupled to the input terminal of the first buffer subunit 1021. According to one embodiment, the filtering subunit 1022 may include a buffer, which has a larger specification than the buffers in the buffer subunits, so that signals with too small a pulse width cannot enter the buffer subunit 1021.

[0040] According to one embodiment, the OR gate 10231 in the last buffer subunit has a stronger driving ability than the OR gates in other buffer subunits and is capable of driving the latch module 12.

[0041] According to one embodiment, the number of buffer subunits in the buffer unit 102 is determined according to the delay parameter of the buffer subunit and the minimum latch signal pulse width of the latch module 12.

[0042] Assume that the minimum pulse width requirement of the latch module 12 is t lThe minimum driving pulse width of the filtering subunit 1022 is t f , that is, the pulse width of latch_en_temp should reach at least t f to pass through the filtering subunit 1022. The pulse delay of each buffering subunit is t b , and the number of buffering subunits is n. To make the second latch signal latch_en meet the minimum pulse width requirement of the latch module 12, it should satisfy:

[0043] t f + nt b ≥t l , that is, n≥(t l -t f ) / t b .

[0044] Optionally, according to an embodiment, to avoid deviation, an additional broadening amount of 20% is usually reserved. Therefore, the number n of the actually used buffering subunits should satisfy n≥1.2(t l -t f ) / t b .

[0045] Optionally, the above formula can also be used to calculate the range of t f , that is, t f ≥t l -nt b / 1.2.

[0046] According to an embodiment, the period of the driving signal in the user clock domain can be 30 ns. After the first latch signal latch_en_temp with a pulse width of 0.3 ns is broadened by 24 buffering subunits 1021, the generated second latch signal latch_en has a pulse width of 1.5 ns (0.3 + 0.05×24 = 1.5). After read_user is generated at a certain rising edge or falling edge of the driving signal in the user clock domain module, because the pulse width of the second latch signal latch_en is less than half of the period of the driving signal in the user clock domain module, it can be ensured that the latest data can be latched before the next rising edge or falling edge of the driving signal in the user clock domain module arrives.

[0047] Optionally, according to an embodiment, the number of buffering subunits can be greater than the minimum number limit. In subsequent operations, the number of actually used buffering subunits can be adjusted by adding switches or the like.

[0048] Figures 2 to 4 is a timing diagram of the working signals of the cross-clock domain data latching system according to an embodiment of the present application.

[0049] According to one embodiment, a cross-clock domain data latching system may involve a signal main_clk. main_clk is the driving signal of the main clock domain module.

[0050] According to one embodiment, a cross-clock domain data latching system may also involve a signal update_main. update_main is a signal representing the update of the main clock domain data.

[0051] According to one embodiment, a cross-clock domain data latching system may also involve a signal user_clk. user_clk is the driving signal of the user clock domain module.

[0052] According to one embodiment, a cross-clock domain data latching system may also involve a signal read_user. read_user is a signal representing that data in the latching module is about to be read.

[0053] According to one embodiment, a cross-clock domain data latching system may also involve a first latching signal latch_en_temp. latch_en_temp is the first latching signal generated by the first latching signal generation unit.

[0054] According to one embodiment, a cross-clock domain data latching system may also involve a second latching signal latch_en. latch_en is the second latching signal after the first latching signal latch_en_temp is widened by the buffer unit.

[0055] According to one embodiment, a cross-clock domain data latching system may also involve data main_data. main_data is the data in the main clock domain module.

[0056] According to one embodiment, a cross-clock domain data latching system may also involve data user_data. user_data is the data read by the user clock domain module.

[0057] According to one embodiment, as Figure 2As shown, at time t1, update_main transitions to valid. After t1, at time t2, read_user transitions to valid. After read_user transitions to valid, the next rising edge t3 of user_clk will trigger the user to read the data. That is, when the data in the main clock domain is updated and the user has not started reading the data in the latch module, this period of time can be fully utilized to make the latch module latch the data that has been updated in the main clock domain. For example, in the time period from t1 to t2, update_main is valid and read_user is invalid. Through the operation of the first latch signal generation unit, latch_en_temp becomes valid. latch_en_temp passes through the filtering and widening of the buffer unit to generate latch_en. The pulse width of this signal is greater than or equal to the minimum pulse width for the latch module to operate normally, enabling the latest data DATA_B to be latched into the latch module before the user reads the data.

[0058] Optionally, according to an embodiment, when the filtering subunit is not used, the rising edge of latch_en is aligned with the rising edge of latch_en_temp.

[0059] According to an embodiment, the number of buffer subunits in the buffer unit is determined according to the delay parameter of the buffer subunit and the minimum latch signal pulse width of the latch module.

[0060] Assume that the minimum pulse width requirement of the latch module is t l . The minimum driving pulse width of the filtering subunit is t f , that is, the pulse width of latch_en_temp must reach at least t f to pass through the filtering subunit. The pulse delay of each buffer subunit is t b , and the number of buffer subunits is n. To make the second latch signal latch_en meet the minimum pulse width requirement of the latch module, the following should be satisfied:

[0061] t f + nt b ≥ t l , that is, n ≥ (t l - t f ) / t b .

[0062] Optionally, according to an embodiment, to avoid deviation, usually an additional widening amount of 20% is reserved. Therefore, the number n of buffer subunits finally used should satisfy n ≥ 1.2(t l - t f ) / t b .

[0063] Optionally, the above formula can also be used to calculate tf in the range, i.e., t f ≥t l -nt b / 1.2.

[0064] According to an embodiment, as Figure 3 shown, at time t4, update_main transitions to valid. At time t5 before t4, read_user transitions to valid, and at time t4, read_user is still valid. It can be considered that the user is reading data at this time or will soon read data. Therefore, it is necessary to keep the data stable to avoid the user reading incorrect data. Specifically, through the operation of the first latch signal generation unit, it is obtained that latch_en_temp is invalid and cannot be widened, and latch_en is invalid. Although the data in the main clock domain has been updated to DATA_B, the data in the latch will not be updated, ensuring that the data remains stable when the user reads it.

[0065] According to an embodiment, as Figure 4 shown, at time t6, update_main transitions to valid. At time t7 after t6, read_user transitions to valid. In the time period from t6 to t7, update_main is valid and read_user is invalid. Through the operation of the first latch signal generation unit, it is obtained that latch_en_temp is valid. However, at this time, the pulse width of latch_en_temp does not meet the minimum pulse width requirement of the filtering subunit in the buffer unit, so it fails to pass through the filtering subunit, and latch_en is still invalid, and the data is not updated.

[0066] The reasons for filtering latch_en_temp are as follows: First, latch_en_temp with too small a pulse width still cannot meet the minimum pulse width requirement of the latch module after being widened. Second, there are some slight differences in the minimum latch pulse widths of different latches in the latch module. It is necessary to filter the input signal latch_en_temp to ensure that the pulse width of latch_en after being widened must be greater than a certain length to ensure that all latches work simultaneously. Otherwise, it will cause some latches to work and some latches not to work, resulting in latch data errors.

[0067] Figure 5 is a flowchart of a cross-clock domain data latching method according to an embodiment of the present application.

[0068] Step 501: Receive update_main and read_user, and generate latch_en_temp. update_main is a signal representing the update of data in the main clock domain, and its width can be at least one main clock cycle. read_user is a signal representing the upcoming reading of data in the latch module.

[0069] Step 502: Determine whether latch_en_temp is valid.

[0070] Step 503: When latch_en_temp is invalid, the data is not updated.

[0071] Step 504: When latch_en_temp is valid, determine whether the pulse width of latch_en_temp meets the minimum pulse width requirement.

[0072] Step 505: When the pulse width of latch_en_temp does not meet the minimum pulse width requirement, latch_en_temp is ignored.

[0073] Step 506: The data is not updated.

[0074] Step 507: When the pulse width of latch_en_temp meets the minimum pulse width requirement, widen latch_en_temp to generate latch_en.

[0075] Step 508: Latch the data in the main clock domain based on latch_en and wait for the user to read.

[0076] The cross-clock-domain data latching system and method proposed in this application can reliably implement cross-clock-domain data latching, ensuring that the data will not change when the user reads at any time, thus avoiding the occurrence of metastable states.

[0077] In view of the cross-clock-domain scenario, this application ensures that the data remains stable when the user reads, while reducing the probability and negative impact of metastable states. Especially in the application scenario where the user clock frequency is more than twice the main clock frequency, this application can quickly complete the latching of the latest data after the signal representing the update of data in the main clock domain is generated.

[0078] The above embodiments are only for illustrating this application, rather than limiting this application. Those of ordinary skill in the relevant technical fields can still make various changes and modifications without departing from the scope of this application. Therefore, all equivalent technical solutions should also fall within the scope of the disclosure of this application.

Claims

1. A cross-clock domain data latch system, characterized in that: include: A first clock domain module configured to generate a first signal representing a first clock domain data update that complies with a first clock domain clock frequency; A latch module, coupled to the first clock domain module, comprising one or more latches, configured to receive data from the first clock domain module and latch the data; A second clock domain module, coupled to the latch module, configured to generate a second signal that corresponds to a second clock domain clock frequency and represents that data in the latch module is to be read, wherein the second clock domain clock frequency is higher than the first clock domain clock frequency; Wherein, the first clock domain module at least includes: a first latch signal generating unit, coupled to the second clock domain module, configured to receive the first signal and the second signal and generate a first latch signal based on the first signal and the second signal; A buffer unit is coupled to the first latch signal generating unit. When the first latch signal is valid, the buffer unit is configured to widen the first latch signal to generate a second latch signal and provide it to the latch module. The latch module is configured to update its latched data to the current first clock domain data, wherein the pulse width of the second latch signal is greater than or equal to the minimum latch pulse width of the latch module.

2. The cross-clock domain data latch system according to claim 1, characterized in that: When the first latch signal is invalid, the buffer unit output is invalid, and the latch module is configured not to update the latched data.

3. The cross-clock domain data latch system according to claim 1, characterized in that: The first latch signal generating unit at least includes: a NOT gate, whose input terminal is configured to receive the second signal; An AND gate has a first input terminal coupled to the output terminal of the NOT gate, a second input terminal configured to receive the first signal, and an output terminal coupled to the buffer unit.

4. The cross-clock domain data latch system according to claim 1, characterized in that: The buffer unit includes at least one buffer subunit; The buffer subunit comprises: a first buffer, an input terminal of which is coupled to the first latch signal generating unit and configured to receive the first latch signal; An OR gate has a first input terminal coupled to the output terminal of the first buffer, a second input terminal coupled to the input terminal of the first buffer, and an output terminal coupled to the output terminal of the buffer unit.

5. The cross-clock domain data latching system according to claim 4 is characterized in that: The buffer unit further includes a filtering subunit coupled between the first latch signal generating unit and the first buffer subunit and configured to filter out the first latch signal having a pulse width smaller than a preset pulse width.

6. The cross-clock domain data latching system according to claim 5, characterized in that: The preset pulse width used by the filtering subunit is at least related to the maximum latch pulse width of each latch in the latch module.

7. The cross-clock domain data latching system according to claim 6 is characterized in that: The preset pulse width is also related to the driving pulse width and number of the first buffer.

8. The cross-clock domain data latching system according to claim 6, characterized in that: The filtering subunit is a second buffer, and a driving pulse width thereof is greater than a driving pulse width of the first buffer.

9. An electronic device, characterized in that: The invention comprises a cross-clock domain data latching system as described in any one of claims 1-8.

10. A method for latching data across clock domains, characterized in that: include: When the first signal representing the update of the first clock domain data is valid and the second signal representing the latched data to be read is invalid, a first latch signal is generated based on the first signal and the second signal, and the first latch signal is widened to generate a second latch signal that meets the latch pulse width, and the latched data is updated using the current first clock domain data.

11. The cross-clock domain data latching method according to claim 10, characterized in that: The method further includes not updating latched data when the first signal is valid and the second signal is also valid.

12. The cross-clock domain data latching method according to claim 10, characterized in that: The method further includes filtering the first latch signal and then stretching the filtered signal to obtain the second latch signal.

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