Security chip for securing physical integrity of integrated circuit

Abstract

The invention relates to a security chip for ensuring the physical integrity of an integrated circuit. A secure electronic component assembly for ensuring the physical integrity of an integrated circuit (IC) is described herein. The secure electronic component assembly may include a printed circuit board (PCB), an integrated circuit (IC) mounted on the PCB, and a secure chip operably coupled to the IC. The IC may include a plurality of solder balls operably coupled thereto and configured for physical and electrical connection between the IC and the PCB. The security chip is configured to detect potential tampering of the IC.

Description

Technical Field

[0001] Example embodiments of the present disclosure relate to a security chip, and more particularly, to a security chip for ensuring the physical integrity of an integrated circuit (IC). Background Art

[0002] As technology steadily and continuously advances, the functionality and complexity of integrated circuits (ICs) have grown exponentially. As the fundamental building blocks of most technologies, ICs have become a prime target for malicious tampering activities aimed at changing, stealing, or destroying the functions they control. Tampering with ICs poses serious security risks, such as unauthorized access to sensitive data, disruption of critical services, manipulation of device functions, etc. Given these challenges, there is a pressing need for a secure chip that can detect tampering activities in ICs.

[0003] Applicants have identified many deficiencies and problems associated with current designs to ensure the physical integrity of ICs. Many of these identified problems have been addressed by developing solutions included in the embodiments of the present disclosure, many examples of which are described in detail herein. Summary of the invention

[0004] Systems and methods for a secure chip for ensuring the physical integrity of an integrated circuit (IC) are provided.

[0005] In one aspect, a security chip for ensuring the physical integrity of an integrated circuit (IC) is provided. The security chip includes: a plurality of physical interfaces operably coupled to the IC; a tamper detection circuit configured to monitor the state of the security chip in response to an interaction initiated by the IC, wherein the tamper detection circuit is configured to detect potential tampering of the IC based at least on the interaction initiated by the IC; and a tamper response circuit configured to execute one or more countermeasures when potential tampering is detected.

[0006] In some embodiments, the plurality of physical interfaces are operably coupled to a plurality of solder balls operably coupled to the IC, wherein the plurality of solder balls are configured for physical and electrical connection between the IC and a printed circuit board (PCB).

[0007] In some embodiments, a security chip is embedded in the IC.

[0008] In some embodiments, the tamper detection circuit further comprises: one or more sensors configured to detect changes in one or more physical parameters of the IC that indicate potential tampering, wherein the one or more physical parameters include at least one of voltage, current, impedance, light, and onboard temperature.

[0009] In some embodiments, the one or more countermeasures include at least one of sending a signal to a user input device indicating potential tampering, disabling one or more functions of the security chip, disabling one or more functions of the IC, or engaging a physical lock associated with the IC.

[0010] In some embodiments, the security chip operates in a passive mode of operation.

[0011] In some embodiments, the security chip operates in an active operating mode.

[0012] In another aspect, a secure electronic component assembly is provided. The assembly includes: a printed circuit board (PCB); an integrated circuit (IC) mounted on the PCB, wherein the IC includes a plurality of solder balls operably coupled thereto and configured for physical and electrical connection between the IC and the PCB; and a security chip operably coupled to the IC, wherein the security chip is configured to detect potential tampering with the IC.

[0013] In some embodiments, the security chip is operably coupled to the plurality of solder balls.

[0014] In another aspect, a method for ensuring the physical integrity of an integrated circuit (IC) is provided. The method includes: monitoring a state of a security chip via a tamper detection circuit, wherein the security chip is operably coupled to the IC; detecting potential tampering of the IC via the tamper detection circuit based at least on a change in the state of the security chip; and executing one or more countermeasures via the tamper response circuit when potential tampering is detected.

[0015] The above content of the invention is provided only to summarize some example embodiments to provide a basic understanding of some aspects of the present disclosure. Therefore, it should be understood that the above embodiments are only examples and should not be interpreted as narrowing the scope or spirit of the present disclosure in any way. It should be understood that the scope of the present disclosure covers many potential embodiments in addition to the embodiments summarized here, some of which will be further described below. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The above generally describes the embodiments of the present disclosure, and now reference will be made to the drawings. The components shown in the drawings may or may not be present in certain embodiments described herein. Some embodiments may include fewer (or more) components than those shown in the drawings.

[0017] Figure 1 An example block diagram of a security chip according to an embodiment of the present invention is shown;

[0018] Figure 2A A secure electronic component assembly according to an embodiment of the present invention is shown in which a secure chip is embedded in an integrated circuit (IC);

[0019] Figure 2B shows a secure electronic component assembly externally coupled to an IC by a secure chip according to an embodiment of the present invention;

[0020] Figure 2C shows a secure electronic component assembly externally coupled to an IC by a secure chip 100 according to an embodiment of the present invention; and

[0021] Figure 3 A method of ensuring the physical integrity of an IC using a security chip according to an embodiment of the present invention is shown. DETAILED DESCRIPTION

[0022] Overview

[0023] The unauthorized removal and reuse of integrated circuits (ICs) from printed circuit boards (PCBs) by unauthorized parties is a pressing issue in the electronics industry. The issue involves the risk of intellectual property theft, as these ICs, once removed, can be analyzed and reverse engineered, leading to unfair competition and potential loss of profitability for the original manufacturer. In addition, these components can be used to produce counterfeit electronic products, which often perform poorly, fail prematurely, and can pose safety issues. This can lead to a negative customer experience and can damage the reputation of the original manufacturer. Further challenges arise in terms of quality control and data security. The removed ICs may not have undergone the necessary quality checks and may have been damaged during the extraction process, resulting in an unreliable product. In addition, these ICs often contain data storage components, so there is a significant risk of data leakage and potential disclosure of sensitive information. From an economic perspective, these issues can cause significant losses to companies that have invested heavily in the research, development, and production of electronic products when their components are reused without authorization.

[0024] The process of mounting an IC on a PCB typically includes positioning the IC on the PCB so that the solder balls on the bottom surface of the IC are aligned with the connection pad pattern on the PCB. After positioning, heat is applied to melt the solder balls so that they form a strong electrical and mechanical connection with the corresponding pads on the PCB. Subsequently, an underfill material is applied in the space between the IC and the PCB. This underfill material can be a specific type of epoxy resin, which is selected for its fluidity and curing characteristics. The underfill material penetrates into the gap and encapsulates the now solidified solder balls and the lower part of the IC. After curing, the underfill material provides additional support and mechanical strength for the bond between the IC and the PCB. The underfill material also reduces the thermal stress of the solder joints and acts as a protective barrier to protect the IC and the precision solder joints from environmental factors such as thermal stress, oxygen, moisture, dust and corrosive agents. The underfill material used in this application is generally resistant to any heat or chemical. Unauthorized persons typically remove the IC from the PCB by stripping off the underfill material (e.g., by chiseling off the underfill material).

[0025] The above problems can be solved in many ways. One such solution, as detailed in the related patent application incorporated herein by reference at the end of this section, involves the use of a bottom filling material in which a detection agent is embedded. When an unauthorized user peels off the bottom filling material to remove the IC, the detection agent may be subject to specific stimulation, thereby triggering certain reactions, thereby changing the state of the IC from its operation, functional state to a dormant state, a non-functional state, a limited functional state, and / or the like. In another solution described herein, a security chip is provided for ensuring the physical integrity of an IC (e.g., a graphics processing unit (GPU)). If an unauthorized individual attempts to extract the IC from a PCB, the security chip can be programmed to identify such tampering and subsequently initiate corrective measures that may cause the IC to fail. As described in more detail below with reference to the accompanying drawings, the security chip may include a physical interface operably coupled to the IC itself and / or the solder balls on the bottom surface of the IC, a tamper detection circuit for monitoring the state of the security chip to detect potential tampering of the IC, and a tamper response circuit configured to execute countermeasures when potential tampering is detected. In some embodiments, the tamper detection circuit may include a sensor configured to detect changes in physical parameters of the IC that may indicate potential tampering. These physical parameters may include voltage, current, impedance, illumination, and / or onboard temperature. In some other embodiments, the tamper detection circuit may include an active shielding layer that can generate an electric field around the embedded security chip so that any disturbance in the electric field may indicate potential tampering with the IC. When potential tampering is detected, the tamper response circuit may execute countermeasures, such as by sending a signal indicating potential tampering to a user input device, disabling one or more functions of the security chip, disabling one or more functions of the IC, engaging a physical lock associated with the IC, etc. In this way, embodiments of the present invention implement hardware-level security measures to ensure that the IC is tamper-resistant.

[0026] Although the present invention has been described with reference to specific embodiments thereof, it will be apparent that various modifications and variations may be made thereto without departing from the broader spirit and scope of the invention. Specifically, although the present invention has been described in the context of a single security chip, those skilled in the art will recognize that the present invention may be used with multiple security chips, either in coordination or in parallel, as appropriate for a given application or as required by a given application. Accordingly, the description and drawings should be regarded as illustrative rather than restrictive.

[0027] Sample Security Chip

[0028] Figure 1 FIG. 1 shows an example block diagram of a security chip 100 according to an embodiment of the present invention. Figure 1As shown, the security chip 100 may include a processor 112 , a memory 114 , an input / output circuit 116 , a communication circuit 118 , a tamper detection circuit 120 , and a tamper response circuit 122 .

[0029] Although the term "circuitry" used herein with respect to elements 112-122 is described using functional language in some cases, it should be understood that a particular implementation necessarily includes the use of specific hardware configured to perform the functions associated with the respective circuits described herein. It should also be understood that certain of these elements 112-122 may include similar or common hardware. For example, both sets of circuits may utilize the same processor, network interface, storage medium, etc. to perform their associated functions, so that each set of circuits does not require duplicate hardware.

[0030] Although the term "circuit" should be broadly understood to include hardware, in some embodiments, the term "circuit" may also include software for configuring hardware. For example, in some embodiments, a "circuit" may include processing circuits, storage media, network interfaces, input / output devices, etc. In some embodiments, other elements of the security chip 100 may provide or supplement the functionality of a particular circuit. For example, the processor 112 may provide processing functionality, the memory 114 may provide storage functionality, the communication circuit 118 may provide network interface functionality, and so on.

[0031] In some embodiments, the processor 112 (and / or a coprocessor or any auxiliary processor or other processing circuitry otherwise associated with the processor) may communicate with the memory 114 via a bus to transfer information between elements of, for example, the security chip 100. The memory 114 may be non-temporary and may include, for example, one or more volatile and / or non-volatile memories, or some combination thereof. In other words, for example, the memory 114 may be an electronic storage device (e.g., a non-temporary computer-readable storage medium). The memory 114 may be configured to store information, data, content, applications, instructions, etc., so that the device (e.g., the security chip 100) can perform various functions according to the example embodiments of the present disclosure.

[0032] Despite Figure 1114 is shown as a single memory, but the memory 114 may include multiple memory components. Multiple memory components may be embodied on a single computing device or distributed on multiple computing devices. In various embodiments, the memory 114 may include, for example, flash memory, static random access memory (SRAM), dynamic random access memory (DRAM), electrically erasable programmable read-only memory (EEPROM), read-only memory (ROM), non-volatile random access memory (NVRAM), or some combination thereof. The memory 114 may be configured to store information, data, applications, instructions (e.g., firmware, operating parameters, tamper detection thresholds, data logs, etc.) to enable the security chip 100 to perform various functions according to the example embodiments discussed herein. For example, in at least some embodiments, the memory 114 is configured to buffer data for processing by the processor 112. In addition, or alternatively, in at least some embodiments, the memory 114 is configured to store program instructions for execution by the processor 112. The memory 114 may store information in the form of static and / or dynamic information. In the process of performing its functions, the security chip 100 may store and / or use the stored information.

[0033] The processor 112 may be embodied in a variety of different ways, for example, may include one or more processing devices configured for independent execution. In addition, or alternatively, the processor 112 may include one or more processors configured in series via a bus to enable independent execution of instructions, pipelining, and / or multithreading. The processor 112 may, for example, be embodied as a variety of devices, including one or more microprocessors with an attached digital signal processor, one or more processors without an attached digital signal processor, one or more coprocessors, one or more multi-core processors, one or more controllers, processing circuits, one or more computers, various other processing elements (including integrated circuits, such as ASICs (application-specific integrated circuits) or FPGAs (field programmable gate arrays)), or some combination thereof. The use of the term "processing circuit" may be understood to include a single-core processor, a multi-core processor, multiple processors within a device, and / or a remote or "cloud" processor. Therefore, although Figure 1 100 is shown as a single processor, but in some embodiments, processor 112 may include multiple processors. The multiple processors may be embodied on a single computing device, or may be distributed across multiple such devices that are collectively configured to function as a security chip 100. The multiple processors may be in operative communication with each other and may be collectively configured to perform one or more functions of the security chip 100 described herein.

[0034] In an example embodiment, the processor 112 is configured to execute instructions stored in the memory 114 or accessible to the processor 112. Alternatively or additionally, the processor 112 may be configured to perform hard-coded functions. Therefore, whether configured by hardware or software methods, or by a combination thereof, the processor 112 may represent an entity (e.g., physically embodied in a circuit) that can perform operations according to an embodiment of the present disclosure when configured accordingly. Alternatively, as another example, when the processor 112 is embodied as an executor of software instructions, the instructions may specifically configure the processor 112 to perform one or more algorithms and / or operations described herein when the instructions are executed. For example, when the processor 112 executes these instructions, they may cause the security chip 100 to perform one or more of its functions described herein.

[0035] In some embodiments, the security chip 100 also includes an input / output circuit 116, which can communicate with the processor 112 in turn to provide audible, visual, mechanical or other outputs and / or receive input instructions from a user or other source in some embodiments. In this sense, the input / output circuit 116 may include a device for performing analog-to-digital and / or digital-to-analog data conversion. The input / output circuit 116 may include support for, for example, digital input / output pins, analog input / output pins, serial interfaces (e.g., universal asynchronous receiver / transmitter (UART), integrated circuit (I2C), serial peripheral interface (SPI), etc.), general input / output pins and / or other input / output mechanisms. The input / output circuit 116 may include a user interface, and may include a network interface, a mobile application, etc.

[0036] The processor 112 can be configured to control one or more functions of a display, alarm, notification, etc., or one or more interface elements via computer program instructions (e.g., software and / or firmware) stored on a memory accessible to the processor 112 (e.g., memory 114, etc.). In some embodiments, aspects of the input / output circuit 116 can be reduced compared to embodiments in which the security chip 100 can be implemented as an end-user chip or other type of device designed for complex customer interactions. In some embodiments (and as is the case with other components discussed herein), the input / output circuit 116 can be eliminated from the security chip 100. The input / output circuit 116 can communicate with the memory 114, the communication circuit 118, and / or any other components, for example via a bus. Although more than one input / output circuit and / or other components may be included in the security chip 100, for ease of explanation, Figure 1 Only one is shown in order to avoid overcomplicating the disclosure (eg, as with other components discussed herein).

[0037] In some embodiments, the communication circuit 118 includes any device, such as a device or circuit embodied in hardware, software, firmware, or a combination of hardware, software, and / or firmware, which is configured to receive and / or send data from / to a network and / or any other device, circuit, or module that communicates with the device. In this regard, the communication circuit 118 may include, for example, a network interface for implementing communication with a wired or wireless communication network. For example, in some embodiments, the communication circuit 118 may be configured to receive and / or send data that may be stored by the memory 114 using any protocol that can be used for communication between computing devices. For example, the communication circuit 118 may include one or more network interface cards, antennas, transmitters, receivers, buses, switches, routers, modems, and supporting hardware and / or software, and / or firmware / software, or any other device suitable for implementing communication via a network. In addition, or alternatively, in some embodiments, the communication circuit 118 may include circuits for interacting with an antenna to transmit signals via the antenna or handle the reception of signals received via the antenna. These signals may be transmitted by the security chip 100 using any of a variety of wireless personal area network (PAN) technologies, such as v1.0 to v5.0, low-power Bluetooth (BLE), infrared wireless (e.g., IrDA), ultra-wideband (UWB), inductive wireless transmission, etc. In addition, it should be understood that these signals can be transmitted using Wi-Fi, near-field communication (NFC), global interoperability for microwave access (WiMAX), or other proximity-based communication protocols. The communication circuit 118 can additionally or alternatively communicate with the memory 114, the input / output circuit 116, and / or any other component of the security chip 100, for example, via a bus. The communication circuit 118 of the security chip 100 can also be configured to receive and transmit information with the various network ports discussed herein.

[0038] The tamper detection circuit 120 may include hardware, software, firmware, and / or a combination of these components for monitoring and anomaly detection, intended to identify potential tampering activities that may endanger the IC. To this end, the tamper detection circuit 120 may be configured to monitor the state of the IC in real time, primarily through interactions initiated by the IC. In an example embodiment, the tamper detection circuit 120 may include one or more sensors designed to detect changes in one or more physical parameters of the IC that may indicate potential tampering. In various embodiments, the physical parameters may include voltage, current and impedance, illumination, onboard temperature, and the like. In one aspect, voltage, current, and impedance measurements can provide insight into the electrical function of the IC and can help identify abnormal electrical behavior that indicates tampering. For example, unexpected changes in voltage levels or current flow may indicate an unauthorized attempt to bypass or manipulate the operation of the IC. On the other hand, any sudden or abnormal illumination detection may indicate an attempt to directly and physically access or change the IC, such as removing the IC from its housing or disassembling the IC package. On the other hand, any sudden increase or decrease in onboard temperature may mean that someone is trying to exploit the vulnerability of the IC through temperature changes.

[0039] Upon detecting such changes, the tamper detection circuit 120 may trigger the tamper response circuit 122. The tamper response circuit 122 may include hardware, software, firmware, and / or a combination of these components for executing one or more predefined countermeasures to mitigate the effects of tampering and protect the integrity of the IC. In some embodiments, the tamper response circuit 122 may be configured to execute various countermeasures based on the nature and severity of the detected threat. In one aspect, the countermeasures may include alarm generation. After detecting potential tampering, the tamper response circuit 122 may generate an alarm signal to trigger an onboard alarm, or transmit it to an external device (e.g., a console). In another aspect, for more serious threats, the countermeasures may include system lockout, whereby the tamper response circuit 122 may disable some or all functions of the IC and / or the security chip 100 to prevent further IC damage until other measures can be taken. On the other hand, in an IC storing sensitive data, the countermeasures may include encrypting or erasing onboard data when potential tampering is detected to prevent unauthorized access to the data. In other aspects, the countermeasures may include activating a physical lock or changing the physical state of the IC to prevent tampering attempts. In an example embodiment, a physical lock can be a micromechanical device integrated into the IC or its housing. When triggered, the physical lock can mechanically lock or block specific portions of the IC, making further intrusion attempts more challenging. The physical lock can be configured to block access to certain critical areas of the IC or to securely seal the entire IC, preventing any physical access without causing noticeable damage.

[0040] In some embodiments, the security chip 100 includes hardware, software, firmware, and / or a combination of these components, configured to support various aspects of tamper detection and response execution. It should be understood that in some embodiments, the tamper detection circuit 120 and / or the tamper response circuit 122 can be combined with other circuits of the security chip 100 (e.g., memory 114, processor 112, input / output circuit 116, and / or communication circuit 118) to perform one or more such example actions. For example, in some embodiments, the tamper detection circuit 120 and / or the tamper response circuit 122 utilizes a processing circuit (e.g., processor 112, etc.) to form an independent subsystem to perform one or more operations thereof. In another example, and in some embodiments, some or all of the functions of the tamper detection circuit 120 and / or the tamper response circuit 122 can be performed by the processor 112. Therefore, in some embodiments, the processor 112 may include the tamper detection circuit 120 and / or the tamper response circuit 122. In this regard, some or all of the example processes and algorithms discussed herein may be performed by at least one of the processor 112, the tamper detection circuit 120, and / or the tamper response circuit 122. It should also be understood that in some embodiments, the tamper detection circuit 120 and / or the tamper response circuit 122 may include a separate processor, a specially configured field programmable gate array (FPGA), or an application specific interface circuit (ASIC) to perform their respective functions.

[0041] Example Safety Electronics Assembly

[0042] Figure 2A FIG. 2 shows a secure electronic component assembly 200 according to an embodiment of the present invention, wherein the secure chip 100 is embedded in an integrated circuit (IC). Figure 2AAs shown, the secure electronic component assembly 200 may include a printed circuit board (PCB) 206, an IC 202 mounted on the PCB 206, and a secure chip 100 embedded in the IC 202 and configured to detect and subsequently respond to potential tampering events. The IC 202 may be mounted on the PCB 206 to establish physical and electrical connections thereto through a plurality of solder balls 204. The solder balls 204 may serve as the primary contact points between the IC 202 and the PCB 206. The solder balls 204 may be arranged in a grid-like pattern and strategically positioned on the underside of the IC 202. The solder balls 204 may be made of a lead-tin alloy or a lead-free alternative, which are selected because they have good properties, such as high electrical conductivity and melting point, suitable for establishing a strong, reliable and conductive connection. In an example embodiment, solder balls 204 may be placed on specific points on the bottom side of IC 202 (these points are generally referred to as pads 205) in a uniform and predetermined pattern that generally corresponds to a layout of contact points on PCB 206, thereby ensuring accurate alignment and connection. When IC 202 is placed on PCB 206, solder balls 204 are aligned with corresponding contact points on PCB 206. After alignment, IC 202 and PCB 206 are subjected to a soldering process (e.g., a reflow process), in which solder balls 204 are heated to a temperature exceeding the melting point of the solder, causing solder balls 204 to melt, and subsequently solidify after cooling to form a strong mechanical and electrical connection between IC 202 and PCB 206. In some embodiments, when IC 202 is mounted on PCB 206 , underfill material 207 may be applied in the space between IC 202 and PCB 206 to distribute thermal and mechanical stress between IC 202 and PCB 206 and add an additional adhesive protection layer between IC 202 and PCB 206 .

[0043] like Figure 2AAs shown, in some embodiments, the security chip 100 can be integrated with the IC 202 at the silicon level during the manufacturing process, where the security chip 100 and the IC 202 are manufactured as a single unit, albeit with different functions. The security chip may include a plurality of physical interfaces 130, which can be used to operably couple the security chip to the IC 202. In some embodiments, the physical interface 130 can be a tangible contact point or connection point that enables the chip to communicate with, monitor, and affect the functions of the IC 202. For example, the physical interface 130 can continuously relay real-time temperature readings from the IC 202 to the security chip 100. In turn, when an anomaly or value outside a specified threshold is detected, the security chip 100 can send corrective instructions through the physical interface 130 to adjust the operation of the IC 202 to maintain the desired temperature level. In an example embodiment, the physical interface 130 can be configured in the form of pins, pads, connectors, wire bonds, etc. When integrated with IC 202, during the manufacturing process, the physical interface 130 of the security chip 100 can be positioned to connect directly to the solder balls 204 or the pads 205 where the solder balls 204 are located. In an alternative embodiment, when integrated with IC 202, the security chip 100 can be positioned below the die shadow area without the pads 205 or solder balls 204. In one aspect, the physical interface 130 can be manufactured on the same layer as the solder balls 204 to ensure direct connectivity. In another aspect, the physical interface can be placed on a different layer, where vias—small conductive holes that connect different layers of the IC—ensure electrical connection. In an embodiment where the physical interface 130 of the security chip 100 is connected to the pads 205, the physical interface 130 is also substantially connected to the solder balls 204. This is because once the IC 202 is heated during the soldering process, the solder balls 204 will melt and fuse with the pads 205, thereby forming a strong conductive connection that also includes the physical interface 130 of the security chip 100. In some embodiments, when IC 202 (with security chip 100 embedded thereon) is mounted on PCB 206, bottom fill material 207 can be applied in the space between IC 202 and PCB 206 so that bottom fill material 207 encapsulates all conductive connections between security chip 100, IC 202 and / or solder balls 204.

[0044] Figure 2B FIG. 2 shows a secure electronic component assembly 250 according to an embodiment of the present invention, wherein the secure chip 100 is embedded in the PCB 20. Figure 2BAs shown, in some embodiments, the security chip can be externally connected to the IC to form a secure electronic component assembly 250. In this configuration, the security chip 100 may not be integrally formed as part of the IC 202 manufacturing process, but can be externally coupled to the IC 202 after the IC 202 is manufactured. In one aspect, the security chip 100 can be positioned in the die shadow area below the IC 202 so that the physical interface 130 of the security chip is aligned with the corresponding contact points 203 on the IC 202 and / or the corresponding solder balls 204 of the IC 202. Once aligned, the security chip 100 can be externally coupled to the IC 202 using the physical interface 130 of the security chip 100 and additional conductive elements (e.g., wire bonds, flip chip bumps, and / or the like) to establish a conductive connection between the security chip 100 and the IC 202. In some embodiments, after the security chip 100 is externally coupled to the IC 202 , an underfill material 207 may be applied in the space between the IC 202 and the PCB 206 encapsulating the security chip 100 and ensure that the security chip 100 will not move or be disassembled without being damaged.

[0045] Figure 2C FIG. 2 shows a secure electronic component assembly 280 according to an embodiment of the present invention, wherein the secure chip 100 is externally coupled to the IC 250. Figure 2C As shown, in some embodiments, the security chip 100 can be integrated with the PCB 206 at the silicon level during the manufacturing process, wherein the security chip 100 and the PCB 206 are manufactured as a single unit, although with different functions. The security chip may include a plurality of physical interfaces 130, which can be used to operatively couple the security chip to the IC 202. When integrated with the PCB 206, during the manufacturing process, the physical interface 130 of the security chip 100 can be positioned to be directly connected to the solder ball 204. In an alternative embodiment, when integrated with the IC 202, the security chip 100 can be positioned below the die shadow area without the pad 205 or the solder ball 204. In some embodiments, when the IC 202 (with the security chip 100 embedded thereon) is mounted on the PCB 206, the bottom fill material 207 can be applied in the space between the IC 202 and the PCB 206, so that the bottom fill material 207 encapsulates all conductive connections between the security chip 100, the PCB 206 and / or the solder ball 204.

[0046] In some embodiments, the security chip 100 may be a passive chip or operate in a passive mode of operation. In this case, the security chip 100 may operate primarily in a sleep or low-power mode, with a primary focus on saving energy and resources. Despite its low activity, the security chip 100 may continuously monitor specific triggers or criteria, and when these triggers or criteria are met, it may switch from its passive mode of operation to an active mode of operation. For example, while high-frequency processing tasks are minimized, the security chip 100 may still be adapted to detect specific signals or anomalies, ensuring that the chip can switch to an active mode of operation when needed, especially during critical security-related events. In its passive mode of operation, the security chip 100 may also be used to protect stored data, ensuring that data integrity and encryption standards are not compromised. In some embodiments, the security chip 100 may have a predetermined communication interval, during which the security chip 100 briefly switches from its passive state to communicate or relay data at a predetermined time, and then reverts to its energy-saving mode. In a further embodiment, the security chip 100 in its passive state may also employ a buffering system in which incoming data or alarms may be temporarily stored and then processed at predetermined intervals or when the chip switches back to its active operating mode.

[0047] In some other embodiments, the security chip 100 can be an active chip or work in an active operation mode. In this case, the security chip 100 can be configured to provide real-time response, high-frequency processing, and strong security measures. In the active operation mode, the security chip 100 is fully put into use, consuming more power to meet the needs of continuous monitoring, data processing, and instant communication. Compared with the passive operation in which the security chip 100 communicates at predetermined intervals, during active operation, the security chip 100 maintains continuous communication with related systems or components, and can instantly relay alarms, receive updates, or coordinate with other chips or systems for synchronous operation.

[0048] Example method of ensuring the physical integrity of an IC using a security chip

[0049] Figure 3A method 300 for ensuring the physical integrity of an IC using a security chip according to an embodiment of the present invention is shown. As shown in block 302, the method may include monitoring the state of a security chip via a tamper detection circuit, wherein the security chip is operably coupled to the IC. As described herein, an unauthorized person may remove the IC from a PCB by stripping off the bottom fill material (e.g., by chiseling off the bottom fill material or using an appropriate solvent to completely dissolve the bottom fill material). If successful, any of these actions may affect the state of the security chip encapsulated in the bottom fill material. In some embodiments, the state of the security chip may refer to various characteristics, including its operating mode, its electrical characteristics, its thermal state, and the state of its various subsystems, such as the voltage level, current flow, power consumption, temperature, illumination, and / or any other quantifiable aspects that can be monitored of the security chip. In some embodiments, the state of the security chip may also refer to the software state of the security chip, including the state of certain processes or the presence of certain signals. In some embodiments, the tamper detection circuit may include an active shielding layer that can generate an electric field around the security chip so that any disturbance in the electric field may indicate potential tampering with the IC. In an example embodiment, the tamper detection circuit may include multiple sensors and transmitters embedded in or around the shielding layer, which may be calibrated to produce an electric field with a specific strength and pattern. Any external interaction or intrusion, such as an attempt to probe, access, or otherwise tamper with the security chip, may cause a disruption in the established electric field. The change may be a change in the field strength, a shift in its pattern, or any other anomaly that is inconsistent with its normal state.

[0050] As shown in block 304, the method may include: detecting potential tampering of the IC via a tamper detection circuit based at least on a change in the state of the security chip. As described herein, the tamper detection circuit may be designed to identify a normal state and flag any deviation from normality. Monitoring the state of the security chip allows for real-time detection of any abnormal events or potential security threats to the IC. If the tamper detection circuit identifies a parameter outside a predetermined range, it may interpret it as a sign of potential tampering.

[0051] Under normal circumstances, the characteristics that define the state of the security chip may follow a predictable pattern or remain within a predefined range. However, if the IC is tampered with, some changes to these characteristics may occur. For example, if an unauthorized person attempts to physically remove or change the IC, it may cause changes in electrical connections, which in turn affect the voltage levels or current flow in the security chip. Similarly, using a solvent to dissolve the bottom fill material may increase the temperature around the security chip, and this change can be detected by the circuit. According to an embodiment of the present invention, when the tamper detection circuit records a change in the state of the security chip that exceeds normal parameters, it interprets this change as indicating a potential tampering event.

[0052] As shown in block 306, the method may include: executing one or more countermeasures via the tamper response circuit after detecting potential tampering. In some embodiments, after identifying a possible tampering attempt (as indicated by a change in the state of the security chip), the tamper detection circuit may send a signal to the tamper response circuit to execute one or more countermeasures specifically designed to respond to the tampering attempt. As described herein, the countermeasures may include alarm generation, functional shutdown of the security chip, IC and / or PCB, data protection measures, physical countermeasures, chip reset, and / or the like.

[0053] Many modifications and other embodiments of the disclosure described herein will occur to those skilled in the art having the benefit of the above description and the teachings presented in the associated drawings. Although the drawings show only certain components of the methods and systems described herein, it should be understood that various other components may also be part of the disclosure herein. In addition, in some cases, the above method may include fewer steps, while in other cases, additional steps may be included. In some cases, the steps of the above method may be modified in any order and in any combination.

[0054] Therefore, it is to be understood that the disclosure is not to be limited to the specific embodiments disclosed and that modifications and other embodiments are intended to be included within the scope of the appended claims.Although specific terms are employed herein, they are used in a generic and descriptive sense only and not for purposes of limitation.

[0055] Incorporation by Reference

[0056] To supplement the present disclosure, this application also incorporates by reference the following commonly assigned patent applications in their entirety:

[0057]

Claims

1. A security chip for ensuring the physical integrity of an integrated circuit IC, the security chip comprising: a plurality of physical interfaces operably coupled to the IC; a tamper detection circuit configured to monitor a state of the security chip in response to an interaction initiated by the IC, wherein the tamper detection circuit is configured to detect potential tampering with the IC based at least on the interaction initiated by the IC; as well as A tamper response circuit is configured to execute one or more countermeasures upon detection of the potential tampering.

2. The security chip according to claim 1, wherein: The plurality of physical interfaces are operably coupled to a plurality of solder balls operably coupled to the IC, wherein the plurality of solder balls are configured for physical and electrical connection between the IC and a printed circuit board (PCB).

3. The security chip according to claim 1, wherein: The security chip is embedded in the IC.

4. The security chip according to claim 1, wherein: The tamper detection circuit also includes: One or more sensors configured to detect changes in one or more physical parameters of the IC that are indicative of the potential tampering, wherein the one or more physical parameters include at least one of voltage, current, impedance, light, and onboard temperature.

5. The security chip according to claim 1, wherein: The one or more countermeasures include at least one of sending a signal to a user input device indicating the potential tampering, disabling one or more functions of the security chip, disabling one or more functions of the IC, or engaging a physical lock associated with the IC.

6. The security chip according to claim 1, wherein: The security chip works in a passive operation mode.

7. The security chip according to claim 1, wherein: The security chip works in an active operation mode.

8. A safety electronic component assembly comprising: Printed circuit board PCB; an integrated circuit (IC) mounted on the PCB, wherein the IC includes a plurality of solder balls operably coupled to the IC and configured for physical and electrical connection between the IC and the PCB; as well as A security chip is operably coupled to the IC, wherein the security chip is configured to detect potential tampering with the IC.

9. The assembly according to claim 8, wherein: The security chip is operably coupled to the plurality of solder balls.

10. The assembly according to claim 8, wherein: The security chip is embedded in the IC.

11. The assembly according to claim 8, wherein The security chip comprises: a plurality of physical interfaces operably coupled to the IC; a tamper detection circuit configured to monitor a state of the security chip in response to an interaction initiated by the IC, wherein the tamper detection circuit is configured to detect potential tampering with the IC based at least on the interaction initiated by the IC; and A tamper response circuit is configured to execute one or more countermeasures upon detection of the potential tampering.

12. The assembly according to claim 11, wherein The tamper detection circuit also includes: One or more sensors configured to detect changes in one or more physical parameters of the IC that are indicative of the potential tampering, wherein the one or more physical parameters include at least one of voltage, current, impedance, light, and onboard temperature.

13. The assembly of claim 11, wherein: The one or more countermeasures include at least one of sending a signal to a user input device indicating potential tampering, disabling one or more functions of the security chip, disabling one or more functions of the IC, or engaging a physical lock associated with the IC.

14. A method for ensuring the physical integrity of an integrated circuit IC, the method comprising: monitoring a status of a security chip via a tamper detection circuit, wherein the security chip is operably coupled to the IC; detecting, via the tamper detection circuit, potential tampering with the IC based at least on a change in a state of the security chip; as well as Via the tamper response circuitry, one or more countermeasures are executed upon detection of the potential tampering.

15. The method of claim 14, wherein the tamper detection circuit further comprises: One or more sensors configured to detect changes in one or more physical parameters of the IC, wherein the changes in the one or more physical parameters result in changes in a state of the security chip that indicate the potential tampering, wherein the one or more physical parameters include at least one of voltage, current, impedance, light, and onboard temperature.

16. The method according to claim 14, wherein: The one or more countermeasures include at least one of sending a signal to a user input device indicating the potential tampering, disabling one or more functions of the security chip, disabling one or more functions of the IC, or engaging a physical lock associated with the IC.

17. The method according to claim 14, wherein: The security chip is operably coupled to a plurality of solder balls operably coupled to the IC, wherein the plurality of solder balls are configured for physical and electrical connection between the IC and a printed circuit board (PCB).

18. The method according to claim 14, wherein: The security chip works in a passive operation mode.

19. The method according to claim 14, wherein: The security chip works in an active operation mode.

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