Behavior model construction method for power additional efficiency of solid-state power amplifier chip

Abstract

The invention discloses a behavior model construction method for the power additional efficiency of a solid-state power amplifier chip, and belongs to the technical field of simulation modeling, and the method comprises the steps: scanning excitation power, and obtaining modeling parameters of a tested solid-state power amplifier chip; a first parameter file and a second parameter file are extracted from the modeling parameters, the first parameter file is used for simulating electric heating nonlinear characteristics, and the second parameter file is used for simulating dynamic efficiency; packaging the first parameter file and the second parameter file into an initial behavior model, and calculating input and output voltage and current wave characteristics of the initial behavior model; obtaining a calculation formula of the power additional efficiency according to the input and output voltage and current wave characteristics and the second parameter file; and adding a calculation formula of the power additional efficiency into the initial behavior model to obtain a complete behavior model. The invention provides a behavior-level model modeling method capable of representing power additional efficiency.

Description

Technical Field

[0001] The present application belongs to the technical field of simulation modeling, and in particular relates to a method for constructing a behavioral model of power added efficiency of a solid-state power amplifier chip. Background Art

[0002] RF solid-state power amplifier chips are important components of radar, navigation, communication and other systems, and play a decisive role in the performance of their RF front-end transceiver systems. Therefore, how to accurately establish a solid-state power amplifier chip model is crucial for the design simulation and verification of high-performance front-end systems. Compared with equivalent circuit models and physical models, behavioral models focus on the description of the mapping relationship between chip input and output signals. There is no need to understand the working mechanism of devices or circuits and their interactions. The model has low model complexity and is flexible to use. At the same time, the behavioral model is directly associated with test data, and has significant advantages in characterization accuracy and convergence.

[0003] For the behavioral modeling of RF solid-state power amplifier chips, accurate characterization of nonlinearity is a major difficulty. At the same time, since the thermal effect of solid-state power amplifiers has a significant impact on their own electrical characteristics, accurate characterization of the impact of heat on electrical performance is also a hot spot and difficulty in modeling. For nonlinear modeling, traditional modeling methods mainly include polynomial models, Volterra series models, polyharmonic distortion models (Poly Harmonic Distortion, PHD), etc. In addition, Keysight Technologies proposed the X-parameter model based on the PHD model, which has become the industry standard for large-signal nonlinear behavioral models in engineering applications. However, this model only considers the mapping relationship between the input and output RF components of the chip, and does not have the ability to predict the DC signal at the static bias power supply of the chip, resulting in the inability of the model to simulate the power added efficiency index. In order to accurately characterize the impact of heat on electrical performance, the industry has used test data lookup table methods (DWLU), polynomial fitting methods under load traction, and artificial neural network fitting modeling and simulation methods. However, the above methods require a large data sample size, which makes the test difficult. In addition, the data processing is relatively complex, the parameter extraction is complex and the calculation is large. It is impossible to combine nonlinearity with power added efficiency calculation, and it is difficult to adapt to the modeling and simulation needs of multi-level RF systems. Summary of the invention

[0004] The purpose of this application is to provide a method for constructing a behavioral model of the power added efficiency of a solid-state power amplifier chip in order to overcome the defects of the prior art, aiming to solve the problem that traditional solid-state power amplifier chip modeling methods are difficult to simultaneously characterize the fundamental amplitude phase, odd harmonics, third-order intermodulation, S parameter compression characteristics, noise, efficiency and other characteristics of the chip, and are not adaptable to multi-level RF system simulation.

[0005] The purpose of this application is achieved through the following technical solutions:

[0006] A method for constructing a behavioral model of power added efficiency of a solid-state power amplifier chip, the method comprising:

[0007] Scan the excitation power to obtain the modeling parameters of the solid-state power amplifier chip under test;

[0008] Extracting a first parameter file and a second parameter file respectively from the modeling parameters, wherein the first parameter file is used to simulate electrothermal nonlinear characteristics, and the second parameter file is used to simulate dynamic efficiency;

[0009] Encapsulating the first parameter file and the second parameter file into an initial behavior model, and calculating input and output voltage and current wave characteristics of the initial behavior model;

[0010] Obtaining a calculation formula for power added efficiency according to the input and output voltage and current wave characteristics and the second parameter file;

[0011] The calculation formula of the power added efficiency is added to the initial behavior model to obtain a complete behavior model.

[0012] Furthermore, the scanning excitation power to obtain the modeling parameters of the solid-state power amplifier chip under test specifically includes:

[0013] The solid-state power amplifier chip under test is tested by scanning the excitation power using a vector network analyzer under multiple temperature environments, and various modeling parameters on the DC source are recorded in sequence according to the test frequency points.

[0014] Furthermore, the first parameter file is extracted in the following manner:

[0015] The relevant parameters extracted from the S parameters obtained by the sweep excitation power test at each temperature are converted into an S2D model file. The S2D file is divided into multiple temperature data blocks according to the temperature points. In each temperature data block, the S parameters at the minimum excitation power measured at each temperature are selected as small signal parameter modules and placed in the first half of the temperature data block.

[0016] The S parameters measured under non-minimum excitation power are normalized and divided into multiple power point data blocks according to frequency points, which are placed in the second half of the temperature data block as gain compression modules.

[0017] Furthermore, the method further comprises:

[0018] The measured S21 is normalized in each frequency block, specifically including:

[0019] A′ n =A n -A0

[0020]

[0021] Where A′ n Normalized S21 amplitude, A n is the S21 amplitude at the input power, A0 is the S21 amplitude at the minimum input power, is the normalized S21 phase, is the S21 phase at this input power, is the S21 phase at minimum input power. The unit of S21 amplitude is dB, and the unit of S21 phase is angle.

[0022] Furthermore, the method for extracting the second parameter file includes:

[0023] The relevant parameters of the current data corresponding to the frequency points obtained by the scanning excitation power test at each temperature are extracted and converted into an mdf model file. The mdf file is divided into multiple temperature data blocks according to the temperature points, and the temperature data blocks are divided into multiple power data blocks according to the power points. In each power data block, the current values ​​measured at the scanned frequency points are recorded in sequence.

[0024] Furthermore, the method further comprises:

[0025] When calculating the input and output voltage and current wave characteristics of the initial behavior model, a cubic spline interpolation method is used to interpolate between data points read from the test data file.

[0026] Furthermore, the calculation formula for obtaining the power added efficiency according to the input and output voltage and current wave characteristics and the second parameter file includes:

[0027] According to the input and output voltage and current wave characteristics, combined with the bias voltage and bias current corresponding to the excitation power obtained by querying the mdf file, a calculation formula for power added efficiency is obtained.

[0028] On the other hand, the present invention also provides a device for constructing a behavior model of a solid-state power amplifier chip, the device comprising:

[0029] A test data acquisition module, wherein the test data acquisition module scans the excitation power to obtain modeling parameters of the solid-state power amplifier chip under test;

[0030] A model parameter extraction module, wherein the model parameter extraction module extracts a first parameter file and a second parameter file from the modeling parameters, wherein the first parameter file is used to simulate electrothermal nonlinear characteristics, and the second parameter file is used to simulate dynamic efficiency;

[0031] A characteristic calculation module, wherein the characteristic calculation module encapsulates the first parameter file and the second parameter file into an initial behavior model, and calculates input and output voltage and current wave characteristics of the initial behavior model;

[0032] A power added efficiency calculation module, wherein the power added efficiency calculation module obtains a calculation formula for the power added efficiency according to the input and output voltage and current wave characteristics and the second parameter file;

[0033] A behavior model building module is used to add the calculation formula of the power added efficiency to the initial behavior model to obtain a complete behavior model.

[0034] On the other hand, the present invention further provides a computer device, comprising a processor and a memory, wherein a computer program is stored in the memory, and the computer program is loaded and executed by the processor to implement any one of the above-mentioned pulse stream deinterleaving methods.

[0035] On the other hand, the present invention further provides a computer-readable storage medium, in which a computer program is stored. The computer program is loaded and executed by a processor to implement any of the above-mentioned pulse stream deinterleaving methods.

[0036] The beneficial effects of this application are:

[0037] (1) Based on a simplified polynomial (S2D) chip behavioral level model, this application proposes a behavioral level modeling method that can characterize power added efficiency. By combining the actual measured data of the dynamic drain current in the chip and the simulation results of the chip output power, the problem of the difficulty in dynamically calculating the power added efficiency is solved, and the simulation prediction of the chip power added efficiency based on the simplified polynomial model is realized. It supports system-level modeling and simulation of multi-level RF system links cascaded with other devices.

[0038] (2) The behavioral model constructed in this application can not only accurately characterize the nonlinear characteristics of the solid-state power amplifier chip, but also support the dynamic calculation of the rate added efficiency. It has the characteristics of low model complexity and high computational efficiency. It supports cascading with other devices to form a multi-level RF system link for system-level modeling and simulation, thus meeting the needs of multi-level RF system modeling and simulation. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 It is a flowchart of a method for constructing a behavioral model of power added efficiency of a solid-state power amplifier chip according to an embodiment of the present application;

[0040] Figure 2 This is a schematic diagram of the data test principle of the embodiment of the present application;

[0041] Figure 3 This is a schematic diagram of the data structure of the S2D file of the solid-state power amplifier chip in the embodiment of the present application;

[0042] Figure 4 This is a schematic diagram of the data structure of the mdf file of current data in an embodiment of the present application;

[0043] Figure 5 This is a schematic diagram of the output power results of the embodiment of the present application;

[0044] Figure 6 is a schematic diagram of gain simulation results of an embodiment of the present application;

[0045] Figure 7 It is a schematic diagram of the simulation results of power added efficiency of the embodiment of the present application;

[0046] Figure 8 It is a structural block diagram of a device for constructing a behavior model of a solid-state power amplifier chip according to an embodiment of the present application. DETAILED DESCRIPTION

[0047] The following describes the embodiments of the present application through specific examples, and those skilled in the art can easily understand other advantages and effects of the present application from the contents disclosed in this specification. The present application can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present application. It should be noted that the following embodiments and features in the embodiments can be combined with each other without conflict.

[0048] Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making any creative work shall fall within the scope of protection of this application.

[0049] The existing behavioral modeling methods require a large amount of data samples, which makes testing difficult. The data processing is relatively complex, the parameter extraction is complex and the calculation is large. It cannot combine nonlinearity with power added efficiency calculation, and it is difficult to adapt to the modeling and simulation needs of multi-level RF systems.

[0050] In order to solve the above technical problems, the following embodiments of a method for constructing a behavioral model of power added efficiency of a solid-state power amplifier chip are proposed in the present application.

[0051] Example 1

[0052] This embodiment takes a radio frequency solid-state power amplifier chip with an operating frequency of 38 to 43 GHz as an example, and performs data testing, parameter extraction, behavioral model construction and other operation steps under ambient temperatures of -40°C, 25°C, and 85°C, respectively. Finally, a simulation schematic diagram is built in a commercial simulation software, and indicators such as power, gain, and power added efficiency of the chip model are simulated. The PAE, output power, and gain obtained by simulation are compared with the measured data, and the average error of each dimension is calculated to judge the accuracy and effectiveness of the model.

[0053] Reference Figure 1 ,like Figure 1The figure is a flowchart of a method for constructing a behavior model of power added efficiency of a solid-state power amplifier chip according to the present embodiment. The method comprises the following steps:

[0054] Step 1: Sweep the excitation power to obtain the modeling parameters of the solid-state power amplifier chip under test.

[0055] Specifically, this embodiment uses a vector network analyzer to test the solid-state power amplifier chip under test by scanning the excitation power Pin under multiple temperature environments, and records the DC voltage, current data and S parameter data on the DC source in sequence according to the test frequency. Before the test, the vector network analyzer needs to be calibrated vector and power to ensure the accuracy of the excitation power Pin on the test reference plane of the vector network analyzer. At the same time, the power range of the excitation power Pin should cover the linear region of the device under test and the input power corresponding to the 3dB compression point to ensure the integrity of the modeling data.

[0056] Reference Figure 2 ,like Figure 2 The following is a schematic diagram of the data test principle of this embodiment. Figure 2 Build a test bench, mount the chip on a special fixture and place it in a temperature chamber; before data testing, the vector network analyzer needs to be calibrated for vector and power, and saved in the calibration file in sequence according to the excitation power scanning points. When actually testing each power point, the vector network analyzer obtains the test reference benchmark of the corresponding power from the calibration file to ensure the accuracy of the data at each test point.

[0057] In this embodiment, the ambient temperature is set to -40℃, 25℃, and 85℃ through a temperature box; the excitation power Pin range is set to -15dBm~19dBm through a scanning vector network analyzer, and the excitation power Pin covers the input power corresponding to the linear region and 3dB compression point of the chip; the frequency setting covers the frequency range of 38GHz~43GHz with a step of 0.1GHz. The excitation power points are scanned at various ambient temperatures to record the S parameters of each point, and the DC voltage and current data on the DC source are recorded at the same time (check the readings of the DC source).

[0058] Step 2: Extract the first parameter file and the second parameter file from the modeling parameters, wherein the first parameter file is used to simulate the electrothermal nonlinear characteristics, and the second parameter file is used to simulate the dynamic efficiency.

[0059] In this embodiment, the measured temperature, power, frequency, S parameters, current and other data information are written into a standard file to adapt to the call of commercial SPICE simulation software.

[0060] Among them, the parameters of temperature, power, frequency, S parameters and other dimensions are extracted and written into the S2D format file for simulating the electrothermal nonlinear characteristics of the solid-state power amplifier chip; the parameters of temperature, power, frequency, and current dimensions are extracted and written into the mdf format file for simulating the dynamic efficiency of the solid-state power amplifier chip;

[0061] The S parameters obtained by the sweep excitation power test at each temperature are extracted and converted into S2D model files. The S2D file is divided into multiple temperature data blocks according to the temperature points. In each temperature data block, the S parameters at the minimum excitation power measured at the temperature are selected as small signal parameter modules and placed in the first half of the temperature data block; the S parameters measured at other power points are normalized and divided into multiple power point data blocks according to the frequency points as gain compression modules, which are used to characterize the nonlinear characteristics of the power amplifier gain and are placed in the second half of the temperature data block; the method for normalizing the measured S21 in each frequency block is as follows:

[0062] A′ n =A n -A0

[0063]

[0064] Where A′ n Normalized S21 amplitude, A n is the S21 amplitude at the input power, A0 is the S21 amplitude at the minimum input power, is the normalized S21 phase, is the S21 phase at this input power, is the S21 phase at minimum input power. The unit of S21 amplitude is dB, and the unit of S21 phase is angle.

[0065] The relevant parameters of the current data corresponding to the frequency points obtained by the scanning excitation power test at each temperature are extracted and converted into an mdf model file. The mdf file is divided into multiple temperature data blocks according to the temperature points, and the temperature data blocks are divided into multiple power data blocks according to the power points. In each power data block, the current values ​​measured at the scanned frequency points are recorded in sequence.

[0066] In this embodiment, at three ambient temperature points, the S parameter with an excitation power Pin of -15dBm is selected as the low-power S parameter and written into the first half of the S2D format file. After the S21 of the S parameters at other powers is normalized, they are written into the second half of the S2D file in blocks according to the frequency, forming an overall S2D ​​file of three data blocks divided by three temperature values. Figure 3 ,like Figure 3 The figure is a schematic diagram of the data structure of the S2D file of the solid-state power amplifier chip according to an embodiment of the present application.

[0067] Extract parameters such as temperature, power, frequency, current, etc. and write them into mdf format files. Figure 4 ,like Figure 4 The figure is a schematic diagram of the data structure of the mdf file of the current data in the embodiment of the present application.

[0068] Step three: Encapsulate the first parameter file and the second parameter file into an initial behavior model, and calculate input and output voltage and current wave characteristics of the initial behavior model.

[0069] Specifically, the S2D model file and the mdf file containing efficiency information are respectively imported into the commercial SPICE simulation software, encapsulated into a behavioral model, and a simulation schematic diagram is built to use the harmonic balance simulator to calculate the model input and output voltage and current wave characteristics; since S2D stores discrete points and the test data points are limited, in order to support the characterization of the electrothermal nonlinear characteristics of the power amplifier chip between the test point data, the cubic spline interpolation method is used to interpolate between the data points of the test data file. The cubic spline interpolation calculation process is as follows:

[0070] The cubic spline interpolation function is represented by S(x), and its basic expression is:

[0071] S(x)=d*x 3 +c*x 2 +b*x+a

[0072] Its coefficients (a, b, c, d) can be determined as follows, assuming that there are n+1 data nodes, namely (x0, y0), (x1, y1), (x2, y2), …, (x n ,y n );

[0073] ① Set the calculation step length h i =x i+1 -x i ;

[0074] ②Let m i =S”(x i ), substitute the data nodes and the specified first endpoint condition into the equation:

[0075]

[0076] ③ Use Gaussian elimination method to solve the equation and obtain the quadratic differential value m i ;

[0077] ④Calculate the coefficients of the spline curve

[0078]

[0079] ⑤In each subinterval x i ≤x≤xi+1 , create the equation:

[0080] g i (x) = a i +b i (xx i )+c i (xx i ) 2 +d i (xx i ) 3 .

[0081] In this embodiment, the S2D model simulation schematic diagram is constructed in the commercial SPICE simulation software, and the model input and output voltage and current wave characteristic calculation is performed based on the harmonic balance simulator in the software. Since discrete points (with a step of 0.1 GHz) are stored in S2D, the simulation calculation in this embodiment interpolates between the data points of the test data file read, and the interpolation step is 0.02 GHz, thereby obtaining a denser input and output voltage and current wave characteristic curve.

[0082] Step 4: Obtain a calculation formula for power added efficiency based on input and output voltage and current wave characteristics and the second parameter file.

[0083] Specifically, the output power Pout, gain Gain, and output voltage V corresponding to the chip are obtained through the calculation in step 3. load [1] Output current wave I load [1] and other data, combined with the bias voltage U corresponding to the Pin obtained by querying the mdf file d and bias current I d , the calculation method of power added efficiency PAE is as follows:

[0084] Pout=0.5*real(V load [1]*conj(I load [1]);

[0085] Gain = Pout - Pin;

[0086]

[0087] The calculation formula of the power added efficiency PAE is compiled into the behavioral model of the chip. The chip model is called during the schematic simulation. After completing the input and output voltage and current wave characteristic calculations, the power added efficiency calculation is automatically performed and the simulation result data is output.

[0088] Step 5: Add the calculation formula of power added efficiency to the initial behavioral model to obtain a complete behavioral model.

[0089] The calculation formula of the power added efficiency PAE is compiled into the behavioral model of the chip. The chip model is called during the schematic simulation. After completing the input and output voltage and current wave characteristic calculations, the power added efficiency calculation is automatically performed and the simulation result data is output.

[0090] Finally, in order to verify the accuracy of the model, the model was substituted into the commercial simulation software, a simulation schematic was built, and the power, gain, and power added efficiency of the chip model were simulated. Figure 5-Figure 7 ,like Figure 5 The figure is a schematic diagram of the output power results of the embodiment of the present application. Figure 6 FIG. 1 is a schematic diagram of the gain simulation results of an embodiment of the present application. Figure 7 Shown is a schematic diagram of the power added efficiency simulation results of an embodiment of the present application.

[0091] After data statistics and analysis, the mean absolute error of the power added efficiency PAE within the frequency band is calculated. The average errors of the simulated and measured PAE, output power and gain at each temperature are shown in Table 1.

[0092] Table 1. Average error of simulation and measurement

[0093] Test environment temperature -40℃ 25℃ 85℃ PAE error (%) 1.138 0.559 0.379 Power Error(dBm) 0.325 0.290 0.272 Gain Error(dB) 0.099 0.073 0.048

[0094] The results show that the average errors of PAE simulation and measurement at different temperatures are within 1.2%, the average error of output power is within 0.35dBm, and the average error of gain is within 0.1dB, indicating that the method proposed in this patent has high accuracy.

[0095] This embodiment is based on a chip behavioral level model of a simplified polynomial (S2D), and proposes a behavioral level modeling method that can characterize power added efficiency. By combining the measured data of the dynamic drain current in the chip and the simulation results of the chip output power, the problem of the difficulty in dynamically calculating the power added efficiency is solved, and the simulation prediction of the chip power added efficiency based on the simplified polynomial model is realized, and it supports system-level modeling and simulation of multi-level RF system links cascaded with other devices. The behavioral model constructed based on this embodiment can not only accurately characterize the nonlinear characteristics of the solid-state power amplifier chip, but also support the dynamic calculation of the power added efficiency. It has the characteristics of low model complexity and high computational efficiency, and supports system-level modeling and simulation of multi-level RF system links cascaded with other devices, meeting the needs of multi-level RF system modeling and simulation.

[0096] Example 2

[0097] parameter Figure 8 ,like Figure 8 The figure is a structural block diagram of a device for constructing a behavior model of a solid-state power amplifier chip according to this embodiment, and the device includes the following structures:

[0098] A test data acquisition module, the test data acquisition module scans the excitation power to obtain modeling parameters of the solid-state power amplifier chip under test;

[0099] A model parameter extraction module, wherein the model parameter extraction module extracts a first parameter file and a second parameter file from the modeling parameters, wherein the first parameter file is used to simulate the electrothermal nonlinear characteristics, and the second parameter file is used to simulate the dynamic efficiency;

[0100] A characteristic calculation module, which encapsulates the first parameter file and the second parameter file into an initial behavior model, and calculates input and output voltage and current wave characteristics of the initial behavior model;

[0101] A power added efficiency calculation module, which obtains a calculation formula for the power added efficiency according to input and output voltage and current wave characteristics and a second parameter file;

[0102] The behavior model building module adds the calculation formula of the power added efficiency to the initial behavior model to obtain a complete behavior model.

[0103] Example 3

[0104] This preferred embodiment provides a computer device, which can implement the steps in any embodiment of the pulse stream deinterleaving method provided in the embodiments of the present application. Therefore, the beneficial effects of the pulse stream deinterleaving method provided in the embodiments of the present application can be achieved. Please refer to the previous embodiments for details and will not be repeated here.

[0105] Example 4

[0106] Those skilled in the art can understand that all or part of the steps in the various methods of the above embodiments can be completed by instructions, or by controlling related hardware through instructions, and the instructions can be stored in a computer-readable storage medium and loaded and executed by a processor. To this end, an embodiment of the present invention provides a storage medium, which stores multiple instructions, and the instructions can be loaded by a processor to execute the steps of any embodiment of the pulse stream deinterleaving method provided by the embodiment of the present invention.

[0107] The storage medium may include: a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, etc.

[0108] Since the instructions stored in the storage medium can execute the steps in any pulse stream deinterleaving method embodiment provided in the embodiments of the present invention, the beneficial effects that can be achieved by any pulse stream deinterleaving method provided in the embodiments of the present invention can be achieved. Please refer to the previous embodiments for details and will not be repeated here.

[0109] The above description is only a preferred embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present application should be included in the protection scope of the present application.

Claims

1. A method for constructing a behavioral model of power added efficiency of a solid-state power amplifier chip, characterized in that: The method comprises: Scan the excitation power to obtain the modeling parameters of the solid-state power amplifier chip under test; Extracting a first parameter file and a second parameter file respectively from the modeling parameters, wherein the first parameter file is used to simulate electrothermal nonlinear characteristics, and the second parameter file is used to simulate dynamic efficiency; Encapsulating the first parameter file and the second parameter file into an initial behavior model, and calculating input and output voltage and current wave characteristics of the initial behavior model; Obtaining a calculation formula for power added efficiency according to the input and output voltage and current wave characteristics and the second parameter file; The calculation formula of the power added efficiency is added to the initial behavior model to obtain a complete behavior model.

2. The method for constructing a behavioral model of power added efficiency of a solid-state power amplifier chip according to claim 1, characterized in that: The scanning excitation power to obtain the modeling parameters of the solid-state power amplifier chip under test specifically includes: The solid-state power amplifier chip under test is tested by scanning the excitation power using a vector network analyzer under multiple temperature environments, and various modeling parameters on the DC source are recorded in sequence according to the test frequency points.

3. The method for constructing a behavioral model of power added efficiency of a solid-state power amplifier chip according to claim 1, characterized in that: The method for extracting the first parameter file includes: The relevant parameters extracted from the S parameters obtained by the sweep excitation power test at each temperature are converted into an S2D model file. The S2D file is divided into multiple temperature data blocks according to the temperature points. In each temperature data block, the S parameters at the minimum excitation power measured at each temperature are selected as small signal parameter modules and placed in the first half of the temperature data block. The S parameters measured under non-minimum excitation power are normalized and divided into multiple power point data blocks according to frequency points, which are placed in the second half of the temperature data block as gain compression modules.

4. The method for constructing a behavioral model of power added efficiency of a solid-state power amplifier chip according to claim 3, characterized in that: The method further comprises: The measured S21 is normalized in each frequency block, specifically including: TO ′ n =A n -A0 Among them A ′ n Normalized S21 amplitude, A n is the S21 amplitude at the input power, A0 is the S21 amplitude at the minimum input power, is the normalized S21 phase, is the S21 phase at this input power, is the S21 phase at minimum input power. The unit of S21 amplitude is dB, and the unit of S21 phase is angle.

5. The method for constructing a behavioral model of power added efficiency of a solid-state power amplifier chip according to claim 1, characterized in that: The method for extracting the second parameter file includes: The relevant parameters of the current data corresponding to the frequency points obtained by the scanning excitation power test at each temperature are extracted and converted into an mdf model file. The mdf file is divided into multiple temperature data blocks according to the temperature points, and the temperature data blocks are divided into multiple power data blocks according to the power points. In each power data block, the current values ​​measured at the scanned frequency points are recorded in sequence.

6. The method for constructing a behavioral model of power added efficiency of a solid-state power amplifier chip according to claim 3, characterized in that: The method further comprises: When calculating the input and output voltage and current wave characteristics of the initial behavior model, a cubic spline interpolation method is used to interpolate between data points read from the test data file.

7. The method for constructing a behavioral model of power added efficiency of a solid-state power amplifier chip according to claim 5, characterized in that: The calculation formula for obtaining the power added efficiency according to the input and output voltage and current wave characteristics and the second parameter file includes: According to the input and output voltage and current wave characteristics, combined with the bias voltage and bias current corresponding to the excitation power obtained by querying the mdf file, a calculation formula for power added efficiency is obtained.

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