Method and system for predicting dynamic bending fatigue life of circuit board and medium

Abstract

The invention relates to the technical field of electronic engineering, in particular to a method and system for predicting the dynamic bending fatigue life of a circuit board and a medium. The method comprises the following steps: obtaining dynamic bending condition data of the circuit board, and carrying out a dynamic bending test on the circuit board according to the dynamic bending condition data of the circuit board, so as to obtain dynamic bending test data of the circuit board; performing circuit board test material feature extraction according to the circuit board dynamic bending test data so as to obtain circuit board test material data; performing circuit board dynamic bending analysis according to the circuit board test material data so as to obtain circuit board material dynamic bending data; and circuit board thickness feature extraction and circuit board layer number feature extraction are carried out according to the circuit board dynamic bending test data, so that circuit board thickness data and circuit board layer number data are obtained. Based on the electronic engineering technology, the accuracy of predicting the dynamic bending fatigue life of the circuit board is improved.

Description

Technical Field

[0001] The present invention relates to the field of electronic engineering technology, and in particular to a prediction method, system and medium for dynamic bending fatigue life of a circuit board. Background Art

[0002] The traditional prediction method of the dynamic bending fatigue life of circuit boards is usually based on static mechanical analysis for fatigue life prediction, and fails to fully consider the impact of dynamic loading conditions on the fatigue behavior of materials. Since circuit boards are often subjected to complex loads such as dynamic bending and impact during actual use, static analysis cannot accurately reflect the true response of the material under dynamic conditions, resulting in a significant reduction in the accuracy of the prediction results. During the dynamic bending process, the thermal expansion effect of the circuit board material is often ignored, and the behavior of the material under different temperature conditions is not considered, resulting in insufficient analysis of thermal stress and strain. This defect is particularly obvious in high-frequency and high-temperature environments, and it is easy to cause material peeling and fatigue failure. Traditional fatigue life prediction methods usually focus on macroscopic characteristics and fail to deeply analyze the changes in the internal microstructure of the material, such as the accumulation of dislocations, the formation and expansion of microcracks, etc. Summary of the invention

[0003] Based on this, it is necessary for the present invention to provide a method for predicting the dynamic bending fatigue life of a circuit board to solve at least one of the above technical problems.

[0004] To achieve the above object, a method for predicting the dynamic bending fatigue life of a circuit board comprises the following steps: Step S1: obtaining circuit board dynamic bending condition data, and performing a circuit board dynamic bending test according to the circuit board dynamic bending condition data, thereby obtaining circuit board dynamic bending test data; Step S2: extracting circuit board test material features according to the circuit board dynamic bending test data, thereby obtaining circuit board test material data; performing circuit board dynamic bending analysis according to the circuit board test material data, thereby obtaining circuit board material dynamic bending data; Step S3: performing circuit board thickness feature extraction and circuit board layer feature extraction according to the circuit board dynamic bending test data, thereby obtaining circuit board thickness data and circuit board layer data; performing circuit board interlayer peeling analysis according to the circuit board thickness data and circuit board layer data, thereby obtaining circuit board interlayer peeling data; Step S4: constructing a circuit board dynamic bending fatigue life prediction model according to the circuit board material dynamic bending data and the circuit board interlayer peeling data, thereby obtaining a circuit board dynamic bending fatigue life prediction model; performing crack propagation analysis according to the circuit board dynamic bending test data, thereby obtaining circuit board crack propagation data; Step S5: Perform dynamic bending fatigue life prediction on the circuit board crack extension data according to the line board dynamic bending fatigue life prediction model, so as to obtain the line board dynamic bending fatigue life prediction data, and upload it to the circuit board management cloud platform to execute the circuit board dynamic bending fatigue life prediction task.

[0005] The present invention provides a real experimental basis by obtaining the dynamic bending condition data of the circuit board and conducting actual tests, which provides accurate data support for subsequent analysis. The dynamic bending test can simulate the performance of the circuit board in the actual working environment and identify the performance changes under complex loads. Extracting the characteristics of the circuit board test material can effectively identify the mechanical properties of the material under dynamic bending conditions, provide important parameters for model construction, and perform material analysis based on the dynamic bending test data, so as to more comprehensively understand the response of the material under dynamic conditions, help optimize the design and improve reliability. By analyzing the thickness and number of layers of the circuit board, the structural integrity of the circuit board can be effectively evaluated, and the weak links can be identified. The interlayer peeling analysis can help identify areas with a higher risk of peeling, so as to take measures in advance to avoid failures in actual applications. By combining the dynamic bending data of the material with the interlayer peeling data, a fatigue life prediction model can be constructed, which can provide a more accurate life prediction, which is of great significance for optimizing product design and extending service life. The crack extension analysis enables timely monitoring of the microcracks inside the material, providing data basis for preventive maintenance of the product. Uploading dynamic bending fatigue life prediction data to the cloud platform can achieve real-time monitoring and data update, providing intelligent support for product management and maintenance. The use of the cloud platform enables multiple departments and personnel to access the latest data and analysis results in real time, which helps cross-departmental collaboration and improves decision-making efficiency.

[0006] Optionally, step S2 specifically includes: Step S21: extracting circuit board test material features according to the circuit board dynamic bending test data, thereby obtaining circuit board test material data; Step S22: performing dynamic bending stress analysis according to the circuit board test material data, thereby obtaining dynamic bending stress data of the circuit board; Step S23: performing dynamic bending strain analysis according to the circuit board test material data, thereby obtaining dynamic bending strain data of the circuit board; Step S24: merging data according to the circuit board dynamic bending stress data and the circuit board dynamic bending strain data to obtain the circuit board material dynamic bending data.

[0007] The present invention can obtain the physical and mechanical properties of the material by extracting the material characteristics of the dynamic bending test data of the circuit board, which provides an important basis for subsequent analysis, ensures the reliability and accuracy of the data, and pays special attention to the material behavior under dynamic bending conditions compared to static analysis, providing support for understanding the performance of the material in actual use. Dynamic bending stress analysis can identify the stress distribution of the material under different dynamic load conditions, help analyze the bearing capacity of the circuit board in actual application, and through stress data, stress concentration areas can be identified. These areas are often the starting point of fatigue failure, which helps to take preventive measures in design and use. Strain analysis can provide information on the degree of deformation of the material during dynamic bending, which helps to evaluate the elastic and plastic behavior of the material under specific conditions, understand the strain characteristics of the material under different bending conditions, and help reveal the dynamic response mechanism of the material, providing a theoretical basis for subsequent design optimization. By merging stress and strain data, a comprehensive dynamic bending data set of circuit board materials can be obtained, which makes subsequent analysis more comprehensive, and can understand the dynamic behavior of the material from multiple dimensions. The merged data helps to build a more accurate fatigue life prediction model, enhance the understanding of the behavior of the material under dynamic conditions, and thus improve the accuracy of the prediction.

[0008] Optionally, step S22 is specifically: Step S221: extracting circuit board via material features according to circuit board test material data, thereby obtaining circuit board via material data; Step S222: Acquire dynamic bending angle data and dynamic bending frequency data of the circuit board; Step S223: performing via bending thermal stress analysis on the via material data of the circuit board according to the dynamic bending frequency data of the circuit board, thereby obtaining the via bending thermal stress data of the circuit board; Step S224: performing via bending angle statistics on the via material data of the circuit board according to the dynamic bending angle data of the circuit board, thereby obtaining via bending angle data; Step S225: performing stress concentration analysis on the circuit board via bending thermal stress data according to the via bending angle data, thereby obtaining via stress concentration data; Step S226: identifying the circuit board via dynamic bending stress concentration area based on the circuit board test material data according to the via stress concentration data, thereby obtaining the circuit board dynamic bending stress data.

[0009] By acquiring dynamic bending angle and frequency data, the present invention can accurately capture the dynamic loading conditions experienced by the circuit board during actual use, so that the analysis is closer to the real application environment. These data provide necessary parameters for subsequent thermal stress analysis and angle statistics, ensuring the relevance and effectiveness of subsequent analysis. Analysis of thermal stress can reveal the thermal load borne by the via material during dynamic bending. This analysis helps to understand the impact of thermal expansion on the via area, especially under high temperature and high frequency conditions. Identifying the thermal stress of the via helps predict the area that causes material peeling or failure, and provides guidance for subsequent design improvements and material selection. Statistics on the response of the via material at different bending angles can help understand the relationship between stress and angle, which is crucial for fatigue analysis under dynamic loading conditions. By analyzing the bending angle data, the via area that causes fatigue failure at a specific angle can be found, providing data support for fatigue life prediction. Through stress concentration analysis, it is possible to identify which via areas are subject to greater stress concentration under specific bending conditions, which helps to assess the risk of peeling and fatigue failure. Understanding the stress concentration area can guide optimization in the subsequent design and manufacturing process, thereby improving the overall performance and reliability of the circuit board. Through comprehensive analysis of stress concentration data, the global identification of the dynamic bending stress distribution of the entire circuit board can be achieved, thereby providing a more comprehensive understanding of material behavior, which can be directly used in the construction of dynamic bending fatigue life prediction models, and provide a basis for predicting the durability and reliability of circuit boards during actual use.

[0010] Optionally, step S23 is specifically: Step S231: extracting solder joint material features according to the circuit board test material data, thereby obtaining solder joint material data; Step S232: performing dynamic bending plastic deformation analysis according to the welding point material data, thereby obtaining dynamic bending plastic deformation data; Step S233: performing welding spot bending frequency area statistics on welding spot material data according to dynamic bending plastic deformation data, thereby obtaining high-frequency welding spot bending area data; Step S234: Calculating the probability of microcracks in dynamic bending of the weld spot according to the high-frequency weld spot bending area data, thereby obtaining the probability data of microcracks in dynamic bending of the weld spot; Step S235: identifying the dynamic bending strain concentration area of ​​the circuit board test material data according to the point dynamic bending microcrack probability data, thereby obtaining the circuit board dynamic bending strain data.

[0011] By extracting the characteristics of solder joint materials, the present invention can deeply understand the mechanical properties and thermal properties of solder joints, which provides basic data for subsequent plastic deformation analysis and ensures the accuracy of data. As a key connecting part in the circuit board, the characteristics of solder joints directly affect the reliability of the entire circuit board, and feature extraction helps to achieve more accurate performance evaluation. Dynamic bending plastic deformation analysis can monitor the deformation behavior of solder joint materials under dynamic loads in real time, identify permanent deformations generated under high load conditions, and by analyzing plastic deformation data, identify the failure mechanism of solder joints under dynamic bending conditions, providing a basis for optimizing welding processes and selecting suitable materials. Statistics on the bending behavior of solder joints at different frequencies help to identify the frequency range that has the greatest impact on solder joint reliability, especially the behavior under high frequency conditions. Identifying the data of high-frequency solder joint bending areas can provide a basis for monitoring and management of solder joints, especially in the actual use environment of the product. By calculating the probability of microcracks, the risk of microcracks occurring in solder joints during dynamic bending can be evaluated, which helps to identify potential failure areas in advance, thereby reducing the probability of failures, and can provide data support for the selection and design of solder joint materials, making decisions more scientific and targeted. Based on the microcrack probability data, identifying the strain concentration areas in dynamic bending can effectively help engineers understand the performance of materials under load, especially those areas that are prone to microcracks. By understanding the strain concentration areas, the design and material selection of the circuit board can be optimized, and the fatigue life and reliability of the entire circuit board can be improved.

[0012] Optionally, step S223 is specifically: The via temperature data of the circuit board via material is statistically analyzed based on the dynamic bending frequency data of the circuit board, thereby obtaining high-temperature via temperature data; Obtain circuit board heat dissipation path data and circuit board electronic component data; A thermal coupling model of the circuit board is constructed according to the heat dissipation path data of the circuit board and the electronic component data of the circuit board, thereby obtaining a thermal coupling model of the circuit board; Extracting high-temperature via position features according to high-temperature via temperature data, thereby obtaining high-temperature via position data; Perform via heat dissipation simulation on the high-temperature via position data according to the circuit board thermal coupling model to obtain via heat dissipation data; The dynamic bending stress of the via is calculated based on the via heat dissipation data, so as to obtain the bending thermal stress data of the via of the circuit board.

[0013] The present invention can identify the temperature change of the via under different dynamic bending frequencies by counting the via temperature, help understand the influence of temperature on the performance of the via material, provide basic data for the evaluation of material performance under high temperature environment, and provide important information for subsequent analysis. Acquiring the heat dissipation path and electronic component data helps to fully understand the heat conduction path inside the circuit board, helps to identify potential heat accumulation areas, and by understanding the heat distribution of electronic components, it can provide a reference basis for the heat dissipation design and optimization of the circuit board, thereby improving the thermal management efficiency of the circuit board. Constructing a thermal coupling model can help analyze the thermal interaction between each electronic component, identify which components will affect the temperature state of the via under high load conditions, and through the establishment of a thermal coupling model, the thermal management of the entire circuit board can be optimized at the system level to reduce the risk of material failure caused by high temperature. Extracting the high-temperature via position characteristics can accurately identify which via positions will be affected by higher temperatures under dynamic bending conditions, thereby providing a more accurate risk assessment. Through the extraction of this data, it can provide a basis for subsequent monitoring and maintenance, ensuring that problems can be discovered in time in practical applications. Through heat dissipation simulation, the heat dissipation performance of vias under high temperature conditions can be accurately evaluated, and their thermal response under dynamic bending conditions can be understood. Based on the simulation results, more effective heat dissipation management strategies can be formulated to prevent material fatigue and failure caused by excessive temperature. By combining heat dissipation data with dynamic bending stress, the stress state of vias under dynamic load and high temperature conditions can be more accurately calculated to help identify high-risk areas. The final calculated via bending thermal stress data can provide important input parameters for the fatigue life prediction of circuit boards, helping to optimize the design and improve the reliability of circuit boards.

[0014] Optionally, step S3 specifically includes: Step S31: extracting circuit board thickness features and circuit board layer number features according to the circuit board dynamic bending test data, thereby obtaining circuit board thickness data and circuit board layer number data; Step S32: performing layer classification according to the circuit board layer number data, thereby obtaining conductive layer data and insulating layer data; Step S33: performing a dynamic bending thermal expansion test on the circuit board thickness data according to the circuit board dynamic bending frequency data, thereby obtaining the circuit board thickness dynamic bending thermal expansion data; Step S34: performing a conductive layer peeling analysis on the conductive layer data according to the dynamic bending thermal expansion data of the circuit board thickness, thereby obtaining the conductive layer peeling data; Step S35: performing insulation stripping analysis on the insulation layer data according to the dynamic bending thermal expansion data of the circuit board thickness, thereby obtaining insulation stripping data; Step S36: merging the circuit board interlayer stripping data according to the conductive layer stripping data and the insulating layer stripping data, thereby obtaining the circuit board interlayer stripping data.

[0015] The present invention can obtain basic geometric parameters by extracting the thickness and number of layers of the circuit board, and provide necessary input data for subsequent analysis. Obtaining thickness and number of layers data helps to better understand the structural characteristics of the circuit board, and facilitates the subsequent analysis of the impact of different layers on the overall performance. Through hierarchical classification, the conductive layer and the insulating layer can be clearly distinguished, laying the foundation for the analysis of different materials. The classified data helps to conduct more accurate analysis of the material characteristics of different layers in the subsequent process, and improves the accuracy of the stripping analysis. Through the dynamic bending thermal expansion test, the thermal expansion behavior of the circuit board at different frequencies can be identified, and the impact of temperature changes on material properties can be deeply understood, which helps to simulate the dynamic response of the material under actual working conditions and provide necessary thermal expansion data for subsequent stripping analysis. Through the thermal expansion data, the stripping analysis of the conductive layer can evaluate the stripping risk of the conductive layer under dynamic bending conditions, timely discover potential failure modes, and help judge the adaptability of the conductive layer under dynamic bending environments, providing guidance for material selection and design optimization. Analyzing the stripping of the insulating layer can effectively evaluate its performance under dynamic loads, help identify the weaknesses of the insulating material, and through the stripping risk assessment of the insulating layer, corresponding improvement measures can be formulated to reduce the risk of failure of the insulating layer. By combining the peeling data of the conductive layer and the insulating layer, a comprehensive understanding of the overall interlayer peeling of the circuit board can be formed, which helps predict the reliability of the entire circuit board. The comprehensive analysis results can provide important decision-making basis for design improvement and material selection, thereby improving the durability and reliability of the circuit board under dynamic bending conditions.

[0016] Optionally, step S34 is specifically: Step S341: simulating the thermal expansion stress of the conductive layer according to the dynamic bending thermal expansion data of the circuit board thickness, thereby obtaining the thermal expansion stress data of the conductive layer; Step S342: drawing a stress distribution area map according to the thermal expansion stress data of the conductive layer, thereby obtaining a thermal expansion stress distribution area map of the conductive layer; Step S343: identifying the stress concentration distribution area according to the conductive layer thermal expansion stress distribution area diagram, thereby obtaining the conductive layer thermal expansion stress concentration distribution area data; Step S344: obtaining yield strength data of the conductive layer material; Step S345: performing stress intensity comparison on the data of the concentrated distribution area of ​​thermal expansion stress of the conductive layer according to the yield strength data of the conductive layer material, so as to obtain high-risk stress intensity data; Step S346: Conducting a conductive layer peeling risk assessment based on the high-risk stress intensity data, thereby obtaining conductive layer peeling data.

[0017] The present invention can clarify the stress state of the conductive layer under dynamic bending conditions through thermal expansion stress simulation, provide basic data for subsequent analysis, help predict the behavior of the conductive layer under dynamic loads and temperature changes, and provide a reference for design optimization. By drawing a stress distribution area map, the stress distribution in the conductive layer can be intuitively displayed, helping engineers to quickly identify potential problem areas, helping to identify areas of stress concentration, and providing important information for subsequent peeling risk assessment. Identifying stress concentration distribution areas can accurately locate the most vulnerable areas in the conductive layer, providing a basis for targeted improvement measures. By analyzing the stress concentration areas, the design of the conductive layer can be optimized to enhance its durability under dynamic bending conditions. Obtaining yield strength data is the basis for understanding the performance of the conductive layer material, which helps to judge the performance of the material under stress conditions and provides necessary material parameter support for subsequent stress intensity comparison and risk assessment. Through stress intensity comparison, the load-bearing capacity of the conductive layer under dynamic bending conditions can be evaluated, and high-risk stress areas can be identified, which can provide a basis for design improvements and ensure the reliability of the conductive layer under dynamic conditions. By analyzing high-risk stress intensity data, the risk of debonding of the conductive layer can be comprehensively assessed, helping to identify potential modes of material failure. This can provide early warning for subsequent material selection and circuit board design, and reduce the risk of failure in actual applications.

[0018] Optionally, step S35 is specifically: Step S351: simulating the thermal expansion stress of the insulation layer according to the dynamic bending thermal expansion data of the circuit board thickness, thereby obtaining the thermal expansion stress data of the insulation layer; Step S352: performing dynamic bending thermal cycle statistics according to the dynamic bending thermal expansion data of the circuit board thickness, thereby obtaining dynamic bending thermal cycle data; Step S353: performing thermal expansion stress accumulation calculation on the thermal expansion stress data of the insulation layer according to the dynamic bending thermal cycle data, thereby obtaining the thermal expansion stress accumulation data of the insulation layer; Step S354: performing microcrack formation analysis on the insulation layer data according to the insulation layer thermal expansion stress accumulation data, thereby obtaining insulation layer microcrack formation data; Step S355: Perform insulation layer peeling risk assessment based on the insulation layer microcrack formation data to obtain insulation layer peeling data.

[0019] The present invention can clearly identify the stress state of the insulating layer under dynamic bending conditions by simulating the thermal expansion stress of the insulating layer, provide basic data for subsequent analysis, help predict the performance of the insulating layer under different load and temperature conditions, and provide a reference for design optimization. Statistical dynamic bending thermal cycle cycles help understand the behavior of the insulating layer under repeated loads, provide data support for material fatigue property analysis, and through thermal cycle data, the durability of the insulating layer under actual working conditions can be evaluated. Through stress accumulation calculation, the total stress borne by the insulating layer during the thermal cycle can be identified, which helps understand the fatigue performance of the material. This calculation helps identify the reliability problems of the insulating layer under multiple thermal cycles, thereby providing a basis for optimized design. Analysis of the formation of microcracks helps to identify the risk of material failure early. Through microcrack formation analysis, the performance of the insulating layer material under dynamic conditions can be more deeply understood, providing data support for subsequent improvement measures. Through the analysis of microcrack formation data, the risk of peeling of the insulating layer can be comprehensively evaluated and the failure mode can be identified. This risk assessment can provide a scientific basis for design optimization and ensure the reliability of the insulating layer under dynamic working conditions.

[0020] Optionally, the present specification also provides a computer-readable storage medium storing a computer program, wherein when the computer program is executed by a processor, the method for predicting the dynamic bending fatigue life of a circuit board described in any one of the above is implemented.

[0021] Optionally, the present specification also provides a circuit board dynamic bending fatigue life prediction system, which is used to execute the circuit board dynamic bending fatigue life prediction method as described above, and the circuit board dynamic bending fatigue life prediction system includes: Circuit board dynamic bending test module: used to obtain circuit board dynamic bending condition data, and perform circuit board dynamic bending test according to the circuit board dynamic bending condition data, so as to obtain circuit board dynamic bending test data; Circuit board dynamic bending analysis module: used to extract circuit board test material features according to circuit board dynamic bending test data, so as to obtain circuit board test material data; perform circuit board dynamic bending analysis according to circuit board test material data, so as to obtain circuit board material dynamic bending data; Circuit board interlayer peeling analysis module: used to extract circuit board thickness features and circuit board layer number features according to circuit board dynamic bending test data, so as to obtain circuit board thickness data and circuit board layer number data; perform circuit board interlayer peeling analysis according to circuit board thickness data and circuit board layer number data, so as to obtain circuit board interlayer peeling data; Circuit board crack propagation analysis module: used to construct a circuit board dynamic bending fatigue life prediction model based on the circuit board material dynamic bending data and the circuit board interlayer peeling data, thereby obtaining a circuit board dynamic bending fatigue life prediction model; perform crack propagation analysis based on the circuit board dynamic bending test data, thereby obtaining circuit board crack propagation data; Wire board dynamic bending fatigue life prediction module: used to perform dynamic bending fatigue life prediction on circuit board crack extension data according to the wire board dynamic bending fatigue life prediction model, so as to obtain the wire board dynamic bending fatigue life prediction data, and upload it to the circuit board management cloud platform to perform the circuit board dynamic bending fatigue life prediction task.

[0022] The circuit board dynamic bending fatigue life prediction system of the present invention can implement any circuit board dynamic bending fatigue life prediction method of the present invention, and is used to combine the operation and signal transmission medium between various modules to complete the circuit board dynamic bending fatigue life prediction method. The internal modules of the system cooperate with each other to improve the accuracy of the circuit board dynamic bending fatigue life prediction. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Other features, objects and advantages of the present invention will become more apparent from the detailed description of non-limiting embodiments thereof made with reference to the following drawings: Figure 1 It is a schematic flow chart of the steps of the method for predicting the dynamic bending fatigue life of a circuit board of the present invention; Figure 2 Detailed step flow diagram of step S2 in the present invention; Figure 3 Detailed step flow diagram of step S23 in the present invention; The realization of the purpose, functional features and advantages of the present invention will be further explained in conjunction with embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0024] The following is a clear and complete description of the technical method of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by technicians in this field without creative work are within the scope of protection of the present invention.

[0025] In addition, the accompanying drawings are only schematic illustrations of the present invention and are not necessarily drawn to scale. The same reference numerals in the figures represent the same or similar parts, and their repeated description will be omitted. Some of the block diagrams shown in the accompanying drawings are functional entities and do not necessarily correspond to physically or logically independent entities. The functional entities can be implemented in software form, or implemented in one or more hardware modules or integrated circuits, or implemented in different networks and / or processor methods and / or microcontroller methods.

[0026] It should be understood that, although the terms "first", "second", etc. may be used herein to describe various units, these units should not be limited by these terms. These terms are used only to distinguish one unit from another unit. For example, without departing from the scope of the exemplary embodiments, the first unit may be referred to as the second unit, and similarly the second unit may be referred to as the first unit. The term "and / or" used herein includes any and all combinations of one or more of the listed associated items.

[0027] To achieve this, please refer to Figures 1 to 3 The present invention provides a method for predicting the dynamic bending fatigue life of a circuit board, the method comprising the following steps: Step S1: obtaining circuit board dynamic bending condition data, and performing a circuit board dynamic bending test according to the circuit board dynamic bending condition data, thereby obtaining circuit board dynamic bending test data; In this embodiment, the dynamic bending condition data of the circuit board is collected in real time through sensors in an industrial environment, including important parameters such as bending angle, bending frequency, number of loading times and loading force. The collection of these condition data is completed by stress strain sensors and dynamic monitoring devices installed on the test device. The monitored bending angle is between 0 and 45 degrees, the frequency range is set to 10Hz to 100Hz, and the loading force is set between 5N and 50N according to the different circuit board material properties. In order to ensure the accuracy of the data, each set of tests is repeated at least 5000 times to simulate actual working conditions. The dynamic bending test is completed using an automated robotic arm, which has high-precision motion control capabilities and can ensure a stable and repeatable test process under the set bending conditions. The dynamic stress change data of the circuit board is obtained in real time through high-precision stress strain sensors, and bending test data is generated for subsequent analysis.

[0028] Step S2: extracting circuit board test material features according to the circuit board dynamic bending test data, thereby obtaining circuit board test material data; performing circuit board dynamic bending analysis according to the circuit board test material data, thereby obtaining circuit board material dynamic bending data; In this embodiment, the material characteristic data of the circuit board is extracted from the bending test data. The material structure of the circuit board is analyzed by X-ray diffraction (XRD) technology to extract the crystal structure and main components of the material, and the microstructure data is obtained in combination with a scanning electron microscope (SEM) to determine the particle size and surface defects of the material. The test data should also include mechanical properties such as elastic modulus and yield strength of the material, which are measured under specific bending load conditions using a universal material testing machine. After obtaining the above material characteristic data, the finite element analysis (FEA) software is used to input the bending frequency, stress-strain data and material characteristic data obtained during the bending test, and dynamic bending stress and strain distribution analysis is performed to determine the stress concentration point, stress distribution and fatigue behavior of the material under dynamic bending conditions. Through these analyses, the mechanical behavior data of the circuit board material under dynamic bending state is generated, providing a basis for fatigue life prediction.

[0029] Step S3: performing circuit board thickness feature extraction and circuit board layer feature extraction according to the circuit board dynamic bending test data, thereby obtaining circuit board thickness data and circuit board layer data; performing circuit board interlayer peeling analysis according to the circuit board thickness data and circuit board layer data, thereby obtaining circuit board interlayer peeling data; In this embodiment, the thickness and number of layers of the circuit board are measured non-contactly using a laser thickness gauge, with an accuracy of ±0.01 mm to ensure the accuracy of the thickness data. After the thickness data is measured, X-ray tomography (X-ray CT) is used to obtain the layer structure information inside the circuit board, including the number, thickness and material distribution of the conductive layer and the insulating layer. These layer and thickness data are processed by automated analysis software, and the position and thickness difference of each layer are marked. Next, the circuit board is subjected to interlayer debonding analysis by finite element analysis. The parameters input for the analysis include the thermal expansion coefficient, interlayer bonding strength and stress distribution of each layer of material. To ensure accuracy, the thermal expansion coefficient is measured by a thermomechanical analyzer (TMA), and the stress of interlayer debonding is calculated by the stress distribution data obtained by the dynamic bending test. Interlayer debonding analysis can identify areas with higher debonding risks and generate detailed debonding risk maps, providing a basis for further fatigue life prediction.

[0030] Step S4: constructing a circuit board dynamic bending fatigue life prediction model according to the circuit board material dynamic bending data and the circuit board interlayer peeling data, thereby obtaining a circuit board dynamic bending fatigue life prediction model; performing crack propagation analysis according to the circuit board dynamic bending test data, thereby obtaining circuit board crack propagation data; In this embodiment, the dynamic bending data of the material and the interlayer peeling data are used to construct a dynamic bending fatigue life prediction model for the circuit board. The model is constructed based on the multivariate regression analysis method, taking multiple factors such as bending frequency, stress level, material properties, etc. as independent variables, and fatigue life as the dependent variable to fit the fatigue life prediction formula. The least squares method is used to reduce the error in the prediction model construction process, and the historical test data is used for correction to ensure the accuracy of the model. The crack propagation analysis uses a digital microscope to observe and record the expansion process of the cracks in the circuit board. The input parameters include the initial length of the crack, the crack growth rate, and the crack propagation direction. These data are collected by combining successive loading with microscopic observation to generate crack propagation rate data. The crack propagation path and stress concentration area are analyzed by finite element simulation to determine the critical value and failure point of crack propagation, providing a reference for the failure prediction of the circuit board.

[0031] Step S5: Perform dynamic bending fatigue life prediction on the circuit board crack extension data according to the line board dynamic bending fatigue life prediction model, so as to obtain the line board dynamic bending fatigue life prediction data, and upload it to the circuit board management cloud platform to execute the circuit board dynamic bending fatigue life prediction task.

[0032] In this embodiment, a fatigue life prediction model is used to comprehensively analyze the crack extension data of the circuit board to predict the fatigue life of the circuit board. The fatigue life prediction data includes the expected life of the circuit board under different bending frequencies and stress levels, and combined with the data in the crack extension analysis, clearly indicates the time node and location of the failure of the circuit board. The predicted data is uploaded to the circuit board management cloud platform, and a management system based on big data analysis is used to perform statistical analysis on the fatigue life of different circuit boards. The cloud platform integrates the operating data of multiple circuit boards to generate dynamic maintenance and inspection plans to optimize the service life and maintenance cycle of the circuit board. The platform monitors the fatigue state of the circuit board in real time and automatically generates maintenance alarms to ensure that maintenance measures are taken in time before failure. At the same time, the prediction model is dynamically optimized according to the new data received by the cloud platform to improve the accuracy of future predictions.

[0033] Optionally, step S2 specifically includes: Step S21: extracting circuit board test material features according to the circuit board dynamic bending test data, thereby obtaining circuit board test material data; In this embodiment, an X-ray diffractometer (XRD) and a scanning electron microscope (SEM) are used to extract the characteristics of the material composition and microstructure of the circuit board. The XRD instrument is used to analyze the crystal structure of the circuit board material and determine the types and proportions of the main components therein, while the SEM is used to obtain the surface microscopic morphology image of the material, accurate to the nanometer level, to observe the defects and particle structure on the surface of the material. In terms of the mechanical properties of the test material, a universal material testing machine is used to obtain the elastic modulus, yield strength and tensile strength data of the material by performing tensile, compression and bending tests on the circuit board. To ensure the accuracy of the test, during the feature extraction process, the test environment must be kept at a constant temperature and humidity, and controlled under standard laboratory conditions of room temperature 25°C and humidity 50%. Through a comprehensive analysis of the above test data, the dynamic bending test characteristic data of the circuit board material is obtained for input into subsequent stress and strain analysis.

[0034] Step S22: performing dynamic bending stress analysis according to the circuit board test material data, thereby obtaining dynamic bending stress data of the circuit board; In this embodiment, the dynamic bending stress analysis is performed based on the finite element analysis (FEA) software, and the material characteristic data is input into the finite element model, including the elastic modulus, yield strength and stress-strain curve of the material. Next, the stress distribution data in the dynamic bending test of the circuit board is imported as the initial condition. In the finite element analysis process, by simulating the actual bending conditions, a nonlinear stress analysis model based on Lagrangian coordinates is adopted to obtain the stress distribution of the circuit board in the dynamic bending state. In order to obtain accurate stress data, the bending angle, bending frequency and applied load are used as input parameters, which are set to 30 degrees, 50Hz and 25N respectively, and the stress concentration areas under these conditions are analyzed in detail to generate a stress distribution diagram. The key goal of stress analysis is to determine the high stress areas on the circuit board that are most prone to fatigue failure, providing a basis for subsequent strain analysis and fatigue life prediction.

[0035] Step S23: performing dynamic bending strain analysis according to the circuit board test material data, thereby obtaining dynamic bending strain data of the circuit board; In this embodiment, strain analysis relies on digital image correlation (DIC) technology and high-precision strain gauge technology. During the dynamic bending process, high-sensitivity strain gauges are attached to key parts of the circuit board to collect strain data during the bending process in real time. The strain gauge adopts a sensitivity of 1.0mV / V to ensure measurement accuracy. At the same time, DIC technology records the tiny deformations on the surface of the circuit board through a high-resolution camera and converts them into displacement fields and strain fields. The strain gauge data and DIC data are combined for multiple calibrations to ensure the accuracy of strain analysis. Through these technologies, the strain distribution of the circuit board under different bending cycles and different angles can be obtained, and the strain evolution of the circuit board material during dynamic bending can be obtained. Strain analysis needs to pay special attention to the fatigue strain concentration area, and analyze the strain accumulation in the area in combination with the yield strength and fatigue limit of the material, and finally obtain complete dynamic bending strain data.

[0036] Step S24: merging data according to the circuit board dynamic bending stress data and the circuit board dynamic bending strain data to obtain the circuit board material dynamic bending data.

[0037] In this embodiment, comprehensive dynamic bending data is generated by merging stress data and strain data. The data merging process uses an adaptive interpolation algorithm to spatially align stress and strain data to ensure accurate integration of data from different sources. The key to merging stress and strain data is to ensure that the stress and strain changes at the same position are consistent. Therefore, a multi-scale analysis method is used to calibrate the data, and multi-level matching is performed from macroscopic (millimeter level) to microscopic (micrometer level). At the same time, the merged data is subjected to statistical regression analysis to determine the fatigue response behavior of the material under different stress and strain conditions. This process requires noise reduction processing of the data to ensure that the systematic error of the test equipment is eliminated. The dynamic bending data finally generated can accurately reflect the fatigue characteristics of the circuit board during the dynamic bending process, and serve as important input data for the subsequent construction of the life prediction model.

[0038] Optionally, step S22 is specifically: Step S221: extracting circuit board via material features according to circuit board test material data, thereby obtaining circuit board via material data; In this embodiment, the material of the circuit board via is characterized by scanning electron microscope (SEM) and energy dispersive spectroscopy (EDS). First, the circuit board via is micro-cut to ensure that a clear cross-sectional image can be obtained during the scanning process. SEM is used to analyze the microstructure of the via material, including grain size, material density, and internal defects. EDS is used to analyze the chemical composition of the via material, including the content ratio and distribution of metal elements such as copper, nickel, and tin. When the fatigue properties of the material in the via are tested, a nanoindenter is required to measure the nanohardness and elastic modulus of the material, and the data results are used for the subsequent accurate analysis of dynamic bending stress. All test data need to be compared and analyzed in conjunction with the process records of the circuit board to determine the accuracy of the characteristic data, and generate via material data, including the yield strength, fatigue limit, and thermal expansion coefficient of the material, to provide a reference for stress and angle analysis in subsequent steps.

[0039] Step S222: Acquire dynamic bending angle data and dynamic bending frequency data of the circuit board; In this embodiment, the dynamic bending angle and frequency data are monitored in real time by using high-precision sensors. The bending angle of the circuit board is collected by a displacement sensor. The sensor is installed on the bending axis of the test device and can accurately measure each change from the initial state to the maximum bending angle. The bending angle range is usually set at 0° to 60°, and the specific value is determined according to the actual working conditions of the circuit board application. The dynamic bending frequency is obtained by an acceleration sensor, and the acquisition frequency range is 1Hz to 100Hz. In actual testing, data in the range of 10Hz to 50Hz is usually selected. All data are stored and analyzed by a real-time data acquisition system to ensure that no dynamic features are missed during the measurement process. This data is used for subsequent thermal stress and bending angle analysis of via materials, and is a key input condition in dynamic bending stress concentration analysis.

[0040] Step S223: performing via bending thermal stress analysis on the via material data of the circuit board according to the dynamic bending frequency data of the circuit board, thereby obtaining the via bending thermal stress data of the circuit board; In this embodiment, the thermal stress of the circuit board via material during the dynamic bending process is analyzed by finite element analysis (FEA). The via material data and the dynamic bending angle and frequency data are input into the finite element analysis software. The analysis model takes into account the thermal expansion effect of the via under different temperature conditions in the multi-layer circuit board, and uses a multi-scale analysis method from the micro grain level to the macro stress distribution. The key to thermal stress analysis is to simulate the expansion effect of different bending frequencies and temperature changes (for example, 20°C to 80°C) on the material. The load conditions applied in the finite element analysis are set according to the actual use conditions of the circuit board, focusing on the thermal stress concentration area in the via, especially the deformation of the material during thermal cycle loading. The finally obtained via bending thermal stress data includes stress change diagrams at different frequencies and temperatures, which provide a basis for the identification of stress concentration areas.

[0041] Step S224: performing via bending angle statistics on the via material data of the circuit board according to the dynamic bending angle data of the circuit board, thereby obtaining via bending angle data; In this embodiment, the bending angle data is processed to count the angle change range experienced by each via during the dynamic bending process. This step uses data analysis software to associate the bending angle data with the via position to generate a detailed angle change curve. According to the test results, each time point in the bending process is marked, with special attention paid to the deformation when the via reaches the maximum angle, and the maximum angle value and the average angle value are counted to generate the via bending angle data. In this process, irregular angle changes need to be calibrated to eliminate noise or abnormal data to ensure that all angle statistics are accurate. The statistical results of the bending angle are compared with the yield angle of the via material, which can be used to analyze whether the material has undergone irreversible deformation during the bending process, providing a reference for subsequent stress concentration analysis.

[0042] Step S225: performing stress concentration analysis on the circuit board via bending thermal stress data according to the via bending angle data, thereby obtaining via stress concentration data; In this embodiment, stress concentration analysis is performed using thermal stress and bending angle data. This analysis uses a stress field smoothing technique based on the Laplace operator, which can accurately identify stress concentration areas at the vias. When performing stress concentration analysis, focus on areas that exceed the yield strength of the material, which are prone to become the starting point of fatigue failure. First, the effect of the bending angle on stress at different positions is displayed through a thermal map, focusing on the distribution of stress peaks at the maximum bending angle. By comparing point-by-point stress values, the stress concentration area is located, and stress concentration data is generated. This data determines the fatigue limit and failure risk area of ​​the via material through sophisticated numerical analysis, providing an important basis for the subsequent identification of dynamic bending stress concentration areas.

[0043] Step S226: identifying the circuit board via dynamic bending stress concentration area based on the circuit board test material data according to the via stress concentration data, thereby obtaining the circuit board dynamic bending stress data.

[0044] In this embodiment, the dynamic bending stress concentration area of ​​the circuit board via is identified using a multivariate regression analysis method based on the stress concentration data. The data of all stress concentration points are input into the analysis model, and combined with the microstructural characteristics of the circuit board material, the area where the stress concentration is most obvious during the dynamic bending process is identified. The stress field topology analysis technology is used to further refine the scope of the identified area and generate a detailed stress concentration area map. The analysis results can intuitively show the via locations where stress concentration is most likely to occur during the dynamic bending process. The identified stress concentration areas will be used as key input data in the next step of the fatigue life prediction model to accurately predict the service life of the circuit board.

[0045] Optionally, step S23 is specifically: Step S231: extracting solder joint material features according to the circuit board test material data, thereby obtaining solder joint material data; In this embodiment, the feature extraction of the solder material is based on scanning electron microscopy (SEM) and X-ray diffraction analysis (XRD) technology. The solder material mainly contains a mixture of solder and flux, and its physical properties such as grain size, hardness, tensile strength and yield strength will affect its performance during dynamic bending. First, the microstructure of the solder joint is observed using SEM to identify the grain boundaries and microscopic defects in the solder joint. Next, the crystal structure and phase composition of the solder material are measured by XRD to confirm its microscopic phase change behavior. In the hardness test of the solder material, a Vickers hardness tester is used to measure the hardness change under different temperature and stress conditions. In addition, the shear strength of the solder material is evaluated by using material mechanics testing equipment to simulate the destructive strength of the solder joint under dynamic bending stress. After testing and analyzing these feature data, solder material data is generated, including key indicators such as fatigue strength, grain boundary stability and fatigue resistance of the solder material, which are used for subsequent plastic deformation analysis.

[0046] Step S232: performing dynamic bending plastic deformation analysis according to the welding point material data, thereby obtaining dynamic bending plastic deformation data; In this embodiment, finite element analysis (FEA) is used to analyze the plastic deformation of the weld during dynamic bending. The weld material data is used as the initial input, and the mechanical loading conditions of the dynamic bending are set (such as a bending frequency of 10 Hz to 50 Hz and a loading stress of 100 MPa to 300 MPa) to perform simulation analysis. The focus of the plastic deformation analysis is on the cumulative deformation of the weld material under multiple cycles of bending. By establishing a three-dimensional finite element model, the geometry of the weld and the stress distribution of the surrounding welding area are taken into account, and the deformation characteristics of the weld at different bending angles and stress amplitudes are analyzed. The key output data include the permanent deformation of the weld material in the high stress area, the offset of the material yield point, and the cumulative effect of deformation after multiple bending. The analysis also includes the hardening behavior of the weld material after yielding, ensuring that the plastic deformation data can be used for subsequent high-frequency weld area analysis and microcrack probability calculation.

[0047] Step S233: performing welding spot bending frequency area statistics on welding spot material data according to dynamic bending plastic deformation data, thereby obtaining high-frequency welding spot bending area data; In this embodiment, a statistical analysis of the bending frequency area of ​​the weld is performed based on the dynamic bending plastic deformation data. The plastic deformation amount in each frequency interval is analyzed by segmenting the bending frequency of the weld. The frequency is divided into multiple intervals, such as a low frequency band of 1Hz to 10Hz, a medium frequency band of 10Hz to 30Hz, and a high frequency band of 30Hz to 50Hz. The stress distribution of the weld at different frequencies is classified and statistically analyzed by frequency analysis software, and the high-frequency bending area is highlighted. These areas are usually subject to frequent stress cycles and are therefore more susceptible to fatigue damage. For each frequency interval, the deformation amplitude and stress concentration points of the weld are statistically analyzed. The welds with strain concentration in the high-frequency area will be further analyzed so that the probability of microcracks can be calculated in the next step. The high-frequency weld bending area data output by this step provides a key reference for the next step of microcrack probability calculation.

[0048] Step S234: Calculating the probability of microcracks in dynamic bending of the weld spot according to the high-frequency weld spot bending area data, thereby obtaining the probability data of microcracks in dynamic bending of the weld spot; In this embodiment, the probability of microcracks in the weld is calculated by the high-frequency bending area data of the weld. Using a crack initiation model based on fatigue damage, the stress distribution and frequency data of the weld are input into the model to simulate the probability of microcracks initiating in the weld material. The model calculates the probability of microcracks based on the fatigue limit, plastic deformation accumulation and stress concentration of the weld material. The critical stress for crack initiation is usually set to 80% to 90% of the yield strength of the weld material. During the calculation process, the stress concentration point of the weld under high-frequency dynamic bending and its plastic deformation accumulation effect are focused on. The results of the crack probability calculation are verified by Monte Carlo simulation to ensure the accuracy of the calculation results. Finally, the dynamic bending microcrack probability data of the weld is generated, laying the foundation for the subsequent identification of strain concentration areas.

[0049] Step S235: identifying the dynamic bending strain concentration area of ​​the circuit board test material data according to the point dynamic bending microcrack probability data, thereby obtaining the circuit board dynamic bending strain data.

[0050] In this embodiment, the dynamic bending strain concentration area of ​​the solder material is identified based on the microcrack probability data of the solder joint. The high-probability microcrack area is used as the initial position of the strain concentration area, and the area range is further refined by strain field analysis software. This step uses the strain energy density method to evaluate the strain concentration of the solder material during the dynamic bending process. For each identified area, its cumulative plastic strain is calculated. In the process of identifying the strain concentration area, the coupling effect of the microstructure and macroscopic geometry of the material is considered to ensure the accurate positioning of the strain concentration area. The final output dynamic bending strain data of the circuit board includes the strain distribution diagram and strain energy density value of the strain concentration area, which is used for further optimization of the fatigue life prediction model.

[0051] Optionally, step S223 is specifically: The via temperature data of the circuit board via material is statistically analyzed based on the dynamic bending frequency data of the circuit board, thereby obtaining high-temperature via temperature data; In this embodiment, based on the dynamic bending frequency data of the circuit board, a temperature statistical analysis of the via is performed to obtain high-temperature via temperature data. First, thermal imaging technology is used to perform real-time temperature detection on the circuit board, especially focusing on the thermal changes in the via area. Combined with the frequency data of dynamic bending, the temperature changes in the via area at different frequencies are analyzed. For areas with higher frequencies, a larger temperature rise phenomenon usually occurs, so special attention needs to be paid to the temperature fluctuations in these areas. In the temperature statistics process, it is necessary to set temperature thresholds under different frequencies and load conditions. Usually, when the temperature reaches 90 degrees Celsius or above, it is regarded as a high-temperature via. Through thermal imaging data acquisition and processing, high-temperature via temperature data is finally generated. The data includes the via position, temperature peak, temperature fluctuation range and corresponding bending frequency.

[0052] Obtain circuit board heat dissipation path data and circuit board electronic component data; In this embodiment, the circuit board heat dissipation path data and electronic component data are obtained through the design drawings of the circuit board and the thermal simulation analysis software. During the analysis process, the layout of the circuit board is parsed to extract the power consumption information of each electronic component. Generally, components with high power consumption, such as processors, chipsets, and power circuits, will cause high temperatures in local areas, so the heat dissipation paths in these areas are particularly important. The CFD (computational fluid dynamics) tool is used to simulate the air flow and heat dissipation to determine the main heat dissipation path of the circuit board. In this step, multiple parameters need to be considered, such as the thermal conductivity of the heat dissipation path, the air flow velocity, the thermal power consumption of the electronic components, etc. For electronic components with high power, it is particularly important to confirm whether the heat dissipation method is forced heat dissipation or natural heat dissipation, and combine its heat dissipation characteristic data with the heat dissipation path information to generate a complete heat dissipation path and electronic component data.

[0053] A thermal coupling model of the circuit board is constructed according to the heat dissipation path data of the circuit board and the electronic component data of the circuit board, thereby obtaining a thermal coupling model of the circuit board; In this embodiment, a thermal coupling model of the circuit board is constructed using finite element analysis (FEA) and thermal fluid analysis tools based on the acquired heat dissipation path data and electronic component data. The model takes into account the heat source characteristics, thermal conductivity, heat diffusion path and heat dissipation conditions of the surrounding environment of each electronic component on the circuit board. For the heat source of the electronic component, the power dissipation parameter of each component is defined. Then, according to the thermal conductivity characteristics of the circuit board material (such as the thermal conductivity of copper is about 385 W / m·K), the thermal conduction path and heat dissipation path of each material are set in the model. By simulating the actual working environment, such as air convection, heat sink and fan, the heat diffusion of each via under different temperature and stress conditions is dynamically calculated. The model can provide real-time feedback on the temperature distribution at different locations on the circuit board, and finally generate a thermal coupling model of the circuit board, and output the temperature distribution curves of the main heat dissipation area and the high temperature area.

[0054] Extracting high-temperature via position features according to high-temperature via temperature data, thereby obtaining high-temperature via position data; In this embodiment, the spatial position characteristics of the high-temperature vias are extracted based on the temperature data of the high-temperature vias through the results of thermal imaging analysis and thermal coupling models. Using the via temperature threshold method, the via areas with temperatures higher than a preset value (such as 90 degrees Celsius) are marked as high-temperature vias. Next, based on the geometric model of the circuit board, the distribution positions of the high-temperature vias are analyzed, especially focusing on vias close to high-power components, dense wiring areas, or vias with poor heat dissipation. The extracted via position information is coordinate-located for subsequent heat dissipation simulation. The high-temperature via position characteristics include the X and Y coordinates of the via, the via size (such as diameter), the type of electronic components around the via, and the corresponding heat source and heat dissipation path.

[0055] Perform via heat dissipation simulation on the high-temperature via position data according to the circuit board thermal coupling model to obtain via heat dissipation data; In this embodiment, based on the high-temperature via position data, the thermal coupling model of the circuit board is used to perform via heat dissipation simulation. The heat flow path of the via area is defined in the model, and the high-temperature via is used as a local heat source to simulate the heat exchange process with the surrounding area. Thermal conductivity, ambient temperature, air flow velocity, and heat dissipation performance of materials near the via need to be considered during the heat dissipation simulation. The calculation of the heat dissipation path is based on the heat transfer equation, in which the key parameters involved include the thermal conductivity of the via material and the heat dissipation coefficient of the local heat sink. In the simulation, the temperature change of the via is evaluated by adjusting the heat dissipation conditions (such as adding a heat sink or optimizing the air flow path). Finally, the heat dissipation data of the via is output, and the data content includes the temperature change curve of the via, the heat flux density distribution, and the temperature balance around the via.

[0056] The dynamic bending stress of the via is calculated based on the via heat dissipation data, so as to obtain the bending thermal stress data of the via of the circuit board.

[0057] In this embodiment, the dynamic bending stress of the via area is calculated based on the via heat dissipation data. The via thermal stress analysis method is used to combine the heat dissipation data with the bending frequency and stress distribution. The calculation of the via bending stress focuses on analyzing the coupling effect of thermal stress and mechanical stress, especially the influence of temperature fluctuations in the via area on the mechanical properties of the material. Through the finite element method, a stress calculation model is established to simulate the stress concentration of the via under high temperature and bending conditions. The input parameters for stress calculation include temperature gradient, material yield strength, dynamic bending frequency, strain rate, etc. During the calculation process, the dynamic bending frequency is combined with the thermal expansion coefficient of the via to evaluate the stress accumulation of the via under different bending cycles. Finally, the via bending thermal stress data is generated, including the stress concentration area, the maximum stress value and the stress-temperature relationship curve, which is used for subsequent fatigue life analysis.

[0058] Optionally, step S3 specifically includes: Step S31: extracting circuit board thickness features and circuit board layer number features according to the circuit board dynamic bending test data, thereby obtaining circuit board thickness data and circuit board layer number data; In this embodiment, according to the dynamic bending test data of the circuit board, a three-dimensional scanner or X-ray tomography technology is used to extract features of the thickness and number of layers of the circuit board. The surface and internal structure of the circuit board are scanned with high precision to extract the thickness data of each layer of material. The thickness data is usually in microns, and the thickness of common circuit boards is between 0.2mm and 3.2mm. Through scanning and analysis, the precise thickness of each conductive layer and insulating layer can be obtained. At the same time, X-ray tomography technology can clearly display the number of layers and structural layout of the circuit board, thereby extracting the number of layers of the circuit board. For multi-layer circuit boards, the extraction results of the number of layers include the number of conductive layers and insulating layers and their arrangement order. These data can be recorded in a spreadsheet as the basis for subsequent analysis. Finally, the thickness data and number of layers of the circuit board are calibrated to ensure that the error is less than 0.01 mm.

[0059] Step S32: performing layer classification according to the circuit board layer number data, thereby obtaining conductive layer data and insulating layer data; In this embodiment, the classification of the conductive layer and the insulating layer is based on the material composition and electrical properties, and the conductive and insulating materials are usually distinguished by using material scanning electron microscopy (SEM) and energy spectrum analysis (EDS) technology. The conductive layer is usually composed of copper or other metal materials, and its main function is circuit conduction. The insulating layer is mostly composed of insulating materials such as glass fiber and polyimide to avoid short circuits between layers. By analyzing the chemical composition and conductivity characteristics of each layer of material, the number, position and thickness distribution data of the conductive layer and the insulating layer are extracted. The focus of this step is to distinguish the boundary position between the conductive layer and the insulating layer to ensure the accuracy of the hierarchical classification results, so as to provide accurate material property data for subsequent dynamic bending analysis.

[0060] Step S33: performing a dynamic bending thermal expansion test on the circuit board thickness data according to the circuit board dynamic bending frequency data, thereby obtaining the circuit board thickness dynamic bending thermal expansion data; In this embodiment, a dynamic bending thermal expansion test is performed on the thickness data of the circuit board based on the dynamic bending frequency data of the circuit board. This test simulates the bending frequency and amplitude in actual work by placing the circuit board in a controllable dynamic bending environment, and combines thermal imaging technology to monitor the thermal expansion of the circuit board at different temperatures. Set the bending frequency range, such as 10 Hz to 1000 Hz, and then use temperature control equipment to gradually increase the ambient temperature of the circuit board, and record the effects of temperature and bending frequency on thickness changes. Use a laser interferometer or a contact thickness gauge to monitor in real time the changes in thickness of each layer of the circuit board under different temperatures and stress states. After the test, the dynamic bending thermal expansion data of the thickness of the circuit board is generated. The data includes temperature changes, thickness change curves under stress, and the thermal expansion coefficients of different material layers are marked. Step S34: performing a conductive layer peeling analysis on the conductive layer data according to the dynamic bending thermal expansion data of the circuit board thickness, thereby obtaining the conductive layer peeling data; In this embodiment, the peeling analysis of the conductive layer is performed based on the dynamic bending thermal expansion data of the thickness of the circuit board. The focus of the peeling analysis is to study the separation trend of the conductive layer under heat and stress conditions. Based on the thermal expansion data, the stress concentration area of ​​the conductive layer under high temperature and high frequency dynamic bending conditions is determined. Stress analysis software is used to simulate the peeling process of the conductive layer, especially the conditions for the generation of the initial point of peeling. Factors considered in the peeling analysis include the interface bonding strength between the conductive layer and the insulating layer, the difference in thermal expansion coefficient of the conductive layer, and the effect of the bending frequency on the interface stress. The conductive layer of the circuit board after the experiment was observed under an electron microscope, and its micro cracks and peeling phenomena were analyzed. Finally, the conductive layer peeling data is generated, covering the temperature at which the peeling occurs, the bending frequency, and the crack propagation path.

[0061] Step S35: performing insulation stripping analysis on the insulation layer data according to the dynamic bending thermal expansion data of the circuit board thickness, thereby obtaining insulation stripping data; In this embodiment, the insulation layer peeling analysis is carried out according to the dynamic bending thermal expansion data of the circuit board thickness. The peeling of the insulation layer is often related to temperature gradient and stress concentration. The thermal-mechanical coupling analysis tool is used to simulate the stress distribution and thermal expansion of the insulation layer at different bending frequencies. During the test, the circuit board is placed in a constant temperature and humidity environment, and a dynamic bending load is applied to record the stress concentration area of ​​the insulation layer. Next, a non-destructive detection method (such as an ultrasonic scanner) is used to monitor the internal defects and interlayer separation of the insulation layer. When the bending frequency is high, microcracks are easily generated in the insulation layer, resulting in interface peeling. The results of the peeling analysis include the threshold temperature and bending stress at which the insulation layer peels off, and finally form the insulation layer peeling data, which is used to evaluate the bending resistance of the insulation layer.

[0062] Step S36: merging the circuit board interlayer stripping data according to the conductive layer stripping data and the insulating layer stripping data, thereby obtaining the circuit board interlayer stripping data.

[0063] In this embodiment, the interlayer peeling data of the circuit board are merged based on the conductive layer peeling data and the insulating layer peeling data. In the process of merging data, the peeling positions of the conductive layer and the insulating layer are matched to determine the key areas where peeling occurs in the multilayer structure. Through the interlayer peeling analysis software, combined with the peeling characteristics and temperature and stress data of different material layers, the peeling conditions between layers are merged into an overall peeling data set. This data set covers the degree of interlayer separation of the circuit board under dynamic bending and thermal expansion conditions, the initial point of peeling, the crack propagation rate and the final peeling area. Finally, complete interlayer peeling data of the circuit board is generated to provide basic data on peeling behavior for subsequent fatigue life prediction.

[0064] Optionally, step S34 is specifically: Step S341: simulating the thermal expansion stress of the conductive layer according to the dynamic bending thermal expansion data of the circuit board thickness, thereby obtaining the thermal expansion stress data of the conductive layer; In this embodiment, the thermal expansion stress simulation of the conductive layer is carried out according to the dynamic bending thermal expansion data of the thickness of the circuit board. The stress state of the conductive layer of the circuit board under thermal expansion and bending loads is simulated using a finite element analysis (FEA) tool. The simulation process first inputs the physical parameters of the conductive layer of the circuit board, such as thickness, thermal expansion coefficient of the material, Young's modulus, etc. According to the dynamic bending thermal expansion data measured in the early stage, the temperature change range is set, usually ranging from 25°C to 150°C, and the bending frequency is set to 10 Hz to 1000 Hz. Through the stress analysis module, the stress changes of the conductive layer under these conditions are calculated to generate a stress distribution curve. The simulation focuses on detecting the stress concentration area near the bending point and at the interface of the conductive layer. Finally, the thermal expansion stress data of the conductive layer is output, including the stress value of each stress concentration point.

[0065] Step S342: drawing a stress distribution area map according to the thermal expansion stress data of the conductive layer, thereby obtaining a thermal expansion stress distribution area map of the conductive layer; In this embodiment, a stress distribution area map is drawn based on the obtained thermal expansion stress data of the conductive layer. Stress analysis software is used to visualize the stress distribution of the conductive layer at different bending frequencies and temperatures. During the drawing process, the geometric model of the conductive layer is fused with the stress simulation data to generate a stress contour map, showing stress concentration areas and areas with relatively small stress. The stress distribution area map uses a color gradient to represent the stress intensity of each area, with red representing high stress areas and blue representing low stress areas. During the drawing process, by comparing the stress distribution area with the structure of the circuit board, the parts where stress concentration and failure occur are identified. After image processing, a thermal expansion stress distribution area map of the conductive layer is generated, with detailed stress numerical annotations.

[0066] Step S343: identifying the stress concentration distribution area according to the conductive layer thermal expansion stress distribution area diagram, thereby obtaining the conductive layer thermal expansion stress concentration distribution area data; In this embodiment, the stress concentration distribution area is identified based on the thermal expansion stress distribution area map of the conductive layer. The area where the stress value exceeds a certain threshold is selected from the stress distribution area map. Generally, the stress concentration area is considered to be a high stress concentration area when the stress value exceeds 70% of the material yield strength. Through the image processing algorithm, the boundary of the high stress area is identified to determine the specific location and range of the stress concentration area. The identification result of the stress concentration area includes the size, stress peak value and position coordinate information of the area, and it is output as stress concentration area data. Finally, the conductive layer thermal expansion stress concentration distribution area data is formed for subsequent stripping risk assessment.

[0067] Step S344: obtaining yield strength data of the conductive layer material; In this embodiment, the yield strength data of the conductive layer material is obtained, and the yield strength data is usually obtained from the physical property database of the conductive layer material. The conductive layer material is mostly copper or copper alloy, and its yield strength is usually between 200 MPa and 400 MPa. In this step, the yield strength of the conductive layer material is verified by material testing. In the material test, the yield strength of the conductive layer is tested using a tensile testing machine, and the tensile force is gradually applied to record the stress value at which the material begins to undergo plastic deformation, which is the yield strength. The yield strength data obtained from the test is used as a standard for subsequent stress strength comparison to ensure that the conductive layer does not exceed the yield limit under actual working conditions.

[0068] Step S345: performing stress intensity comparison on the data of the concentrated distribution area of ​​thermal expansion stress of the conductive layer according to the yield strength data of the conductive layer material, so as to obtain high-risk stress intensity data; In this embodiment, based on the yield strength data of the conductive layer, the data of the concentrated distribution area of ​​the thermal expansion stress of the conductive layer is compared with the stress intensity. Through the stress comparison analysis software, the data of the concentrated distribution area of ​​the thermal expansion stress is compared with the yield strength data one by one to determine whether the stress value in the stress concentration area exceeds the yield strength of the conductive layer. If the stress value exceeds the yield strength, the area is a high-risk stress area. In the process of stress intensity comparison, the dynamic characteristics of stress changing with bending frequency and temperature must be considered to ensure the accuracy of the calculation results. The output of high-risk stress intensity data includes key information such as the location of the area where the stress exceeds the limit, the difference between the stress value and the yield strength.

[0069] Step S346: Conducting a conductive layer peeling risk assessment based on the high-risk stress intensity data, thereby obtaining conductive layer peeling data.

[0070] In this embodiment, the peeling risk of the conductive layer is assessed based on the obtained high-risk stress intensity data. The risk assessment determines the peeling risk of the conductive layer by analyzing the effects of stress concentration, temperature changes, and bending frequency on the fatigue life of the material in the high-risk stress area. By comparing the stress concentration in the high-risk area with the fatigue limit, the peeling trend of the conductive layer under long-term repeated bending is simulated. Using fatigue life assessment software, combined with the stress distribution and material fatigue curve in the high-risk stress area, the peeling risk of the conductive layer under specific working conditions is assessed to generate peeling probability data. The assessment results quantify the peeling risk of the conductive layer into a specific probability value, and mark the location and size of the high-risk peeling area. Finally, the conductive layer peeling data is output as an important input parameter for circuit board fatigue life prediction.

[0071] Optionally, step S35 is specifically: Step S351: simulating the thermal expansion stress of the insulation layer according to the dynamic bending thermal expansion data of the circuit board thickness, thereby obtaining the thermal expansion stress data of the insulation layer; In this embodiment, the thermal expansion stress of the insulating layer is simulated according to the dynamic bending thermal expansion data of the thickness of the circuit board. The stress state of the insulating layer under dynamic bending and temperature change conditions is simulated by the finite element analysis (FEA) tool. First, the relevant parameters of the insulating layer material, such as thermal expansion coefficient, Young's modulus, Poisson's ratio, etc., are input, and the temperature change range is set in combination with the dynamic bending thermal expansion data. It is generally set between room temperature 25°C and high temperature 150°C, and the bending frequency is 10 Hz to 1000 Hz. The stress simulation focuses on the stress concentration of the insulating layer at the bending point and the contact area with the conductive layer. Through simulation calculation, the stress distribution data of the insulating layer at different temperatures and frequencies are output to obtain the thermal expansion stress data of the insulating layer.

[0072] Step S352: performing dynamic bending thermal cycle statistics according to the dynamic bending thermal expansion data of the circuit board thickness, thereby obtaining dynamic bending thermal cycle data; In this embodiment, dynamic bending thermal cycle statistics are performed based on the dynamic bending thermal expansion data of the circuit board thickness. By recording the bending frequency of the insulating layer material at different temperatures, the number of thermal expansion and contraction cycles of the material is calculated. In the specific operation, the temperature change range and the bending frequency are set, assuming that each cycle includes a heating to a high temperature of 150°C and then cooling to a normal temperature of 25°C. During the statistical process, it is necessary to ensure that the bending process meets the actual working conditions. Usually 1000 to 10,000 thermal cycle cycles are simulated to evaluate the long-term fatigue of the material. The statistical results include the number of bends in each temperature range and the corresponding time period, and finally generate dynamic bending thermal cycle data.

[0073] Step S353: performing thermal expansion stress accumulation calculation on the thermal expansion stress data of the insulation layer according to the dynamic bending thermal cycle data, thereby obtaining the thermal expansion stress accumulation data of the insulation layer; In this embodiment, the thermal expansion stress of the insulating layer is cumulatively calculated based on the dynamic bending thermal cycle data. The magnitude of stress accumulation is determined by calculating the stress change caused to the insulating layer material by each thermal cycle. During each cycle, the thermal expansion and contraction stress experienced by the insulating layer will gradually accumulate, eventually leading to material fatigue failure. The calculation of stress accumulation is based on the formula of temperature change and thermal expansion coefficient, and the rate of change of cumulative stress depends on the bending frequency, the elastic limit of the material, and the number of cycles. During the calculation process, the stress accumulation trend in high temperature and high stress areas is monitored, and the stress accumulation data of the insulating layer at each cycle stage is output to form the thermal expansion stress accumulation data of the insulating layer.

[0074] Step S354: performing microcrack formation analysis on the insulation layer data according to the insulation layer thermal expansion stress accumulation data, thereby obtaining insulation layer microcrack formation data; In this embodiment, the microcrack formation of the insulating layer material is analyzed based on the cumulative data of thermal expansion stress of the insulating layer. The stress accumulation data is compared with the fatigue limit and fracture toughness of the material to identify potential crack formation areas. During the microcrack formation analysis process, the probability of crack formation in the material under a specific number of cycles is evaluated by combining the physical properties of the material and the cumulative stress data. The microcrack formation of the insulating layer is mainly concentrated in the stress concentration area, especially the contact point between the edge of the conductive layer and the insulating layer. The initial position of the microcrack and its expansion path are predicted by the stress fatigue analysis method. The analysis results are output as the microcrack formation data of the insulating layer, marking the crack formation area and the position where the cumulative stress exceeds the fracture toughness of the material.

[0075] Step S355: Perform insulation layer peeling risk assessment based on the insulation layer microcrack formation data to obtain insulation layer peeling data.

[0076] In this embodiment, the peeling risk of the insulating layer is assessed based on the microcrack formation data of the insulating layer. The possibility of peeling of the insulating layer under long-term bending and thermal expansion conditions is calculated through the analysis model of cumulative stress and crack extension. When evaluating, the material properties of the insulating layer, the extension rate of microcracks and the degree of fatigue damage in the stress concentration area are focused on. The fatigue damage assessment uses the SN curve (stress-life curve) of the material and is calculated in combination with the probability of crack formation. The results of the risk assessment include the probability of peeling, the estimated time of peeling, and the specific area of ​​crack extension. Finally, the peeling data of the insulating layer is generated, and the peeling area, crack length and peeling probability are output to provide a basis for the fatigue life prediction of the circuit board.

[0077] Optionally, the present specification also provides a computer-readable storage medium storing a computer program, wherein when the computer program is executed by a processor, the method for predicting the dynamic bending fatigue life of a circuit board described in any one of the above is implemented.

[0078] Optionally, the present specification also provides a circuit board dynamic bending fatigue life prediction system, which is used to execute the circuit board dynamic bending fatigue life prediction method as described above, and the circuit board dynamic bending fatigue life prediction system includes: Circuit board dynamic bending test module: used to obtain circuit board dynamic bending condition data, and perform circuit board dynamic bending test according to the circuit board dynamic bending condition data, so as to obtain circuit board dynamic bending test data; Circuit board dynamic bending analysis module: used to extract circuit board test material features according to circuit board dynamic bending test data, so as to obtain circuit board test material data; perform circuit board dynamic bending analysis according to circuit board test material data, so as to obtain circuit board material dynamic bending data; Circuit board interlayer peeling analysis module: used to extract circuit board thickness features and circuit board layer number features according to circuit board dynamic bending test data, so as to obtain circuit board thickness data and circuit board layer number data; perform circuit board interlayer peeling analysis according to circuit board thickness data and circuit board layer number data, so as to obtain circuit board interlayer peeling data; Circuit board crack propagation analysis module: used to construct a circuit board dynamic bending fatigue life prediction model based on the circuit board material dynamic bending data and the circuit board interlayer peeling data, thereby obtaining a circuit board dynamic bending fatigue life prediction model; perform crack propagation analysis based on the circuit board dynamic bending test data, thereby obtaining circuit board crack propagation data; Wire board dynamic bending fatigue life prediction module: used to perform dynamic bending fatigue life prediction on circuit board crack extension data according to the wire board dynamic bending fatigue life prediction model, so as to obtain the wire board dynamic bending fatigue life prediction data, and upload it to the circuit board management cloud platform to perform the circuit board dynamic bending fatigue life prediction task.

[0079] The circuit board dynamic bending fatigue life prediction system of the present invention can implement any circuit board dynamic bending fatigue life prediction method of the present invention, and is used to combine the operation and signal transmission medium between various modules to complete the circuit board dynamic bending fatigue life prediction method. The internal modules of the system cooperate with each other to improve the accuracy of the circuit board dynamic bending fatigue life prediction.

[0080] Therefore, the embodiments should be regarded as illustrative and non-restrictive from all points, and the scope of the present invention is limited by the appended claims rather than the above description, and it is therefore intended that all changes falling within the meaning and range of equivalent elements of the application documents are included in the present invention.

[0081] The above description is only a specific embodiment of the present invention, so that those skilled in the art can understand or implement the present invention. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but should conform to the widest scope consistent with the principles and novel features invented herein.

Claims

1. A method for predicting the dynamic bending fatigue life of a circuit board, characterized in that: The following steps are involved: Step S1: obtaining circuit board dynamic bending condition data, and performing a circuit board dynamic bending test according to the circuit board dynamic bending condition data, thereby obtaining circuit board dynamic bending test data; Step S2: extracting circuit board test material features according to the circuit board dynamic bending test data, thereby obtaining circuit board test material data; performing circuit board dynamic bending analysis according to the circuit board test material data, thereby obtaining circuit board material dynamic bending data; Step S3: performing circuit board thickness feature extraction and circuit board layer feature extraction according to the circuit board dynamic bending test data, thereby obtaining circuit board thickness data and circuit board layer data; performing circuit board interlayer peeling analysis according to the circuit board thickness data and circuit board layer data, thereby obtaining circuit board interlayer peeling data; Step S4: constructing a circuit board dynamic bending fatigue life prediction model according to the circuit board material dynamic bending data and the circuit board interlayer peeling data, thereby obtaining a circuit board dynamic bending fatigue life prediction model; performing crack propagation analysis according to the circuit board dynamic bending test data, thereby obtaining circuit board crack propagation data; Step S5: Perform dynamic bending fatigue life prediction on the circuit board crack extension data according to the line board dynamic bending fatigue life prediction model, so as to obtain the line board dynamic bending fatigue life prediction data, and upload it to the circuit board management cloud platform to execute the circuit board dynamic bending fatigue life prediction task.

2. The method for predicting the dynamic bending fatigue life of a circuit board according to claim 1, characterized in that: Step S2 is specifically as follows: Step S21: extracting circuit board test material features according to the circuit board dynamic bending test data, thereby obtaining circuit board test material data; Step S22: performing dynamic bending stress analysis according to the circuit board test material data, thereby obtaining dynamic bending stress data of the circuit board; Step S23: performing dynamic bending strain analysis according to the circuit board test material data, thereby obtaining dynamic bending strain data of the circuit board; Step S24: merging data according to the circuit board dynamic bending stress data and the circuit board dynamic bending strain data to obtain the circuit board material dynamic bending data.

3. The method for predicting the dynamic bending fatigue life of a circuit board according to claim 2, characterized in that: Step S22 is specifically as follows: Step S221: extracting circuit board via material features according to circuit board test material data, thereby obtaining circuit board via material data; Step S222: Acquire dynamic bending angle data and dynamic bending frequency data of the circuit board; Step S223: performing via bending thermal stress analysis on the via material data of the circuit board according to the dynamic bending frequency data of the circuit board, thereby obtaining the via bending thermal stress data of the circuit board; Step S224: performing via bending angle statistics on the via material data of the circuit board according to the dynamic bending angle data of the circuit board, thereby obtaining via bending angle data; Step S225: performing stress concentration analysis on the circuit board via bending thermal stress data according to the via bending angle data, thereby obtaining via stress concentration data; Step S226: identifying the circuit board via dynamic bending stress concentration area based on the circuit board test material data according to the via stress concentration data, thereby obtaining the circuit board dynamic bending stress data.

4. The method for predicting the dynamic bending fatigue life of a circuit board according to claim 2, characterized in that: Step S23 is specifically as follows: Step S231: extracting solder joint material features according to the circuit board test material data, thereby obtaining solder joint material data; Step S232: performing dynamic bending plastic deformation analysis according to the welding point material data, thereby obtaining dynamic bending plastic deformation data; Step S233: performing welding spot bending frequency area statistics on welding spot material data according to dynamic bending plastic deformation data, thereby obtaining high-frequency welding spot bending area data; Step S234: Calculating the probability of microcracks in dynamic bending of the weld spot according to the high-frequency weld spot bending area data, thereby obtaining the probability data of microcracks in dynamic bending of the weld spot; Step S235: identifying the dynamic bending strain concentration area of ​​the circuit board test material data according to the point dynamic bending microcrack probability data, thereby obtaining the circuit board dynamic bending strain data.

5. The method for predicting the dynamic bending fatigue life of a circuit board according to claim 3, characterized in that: Step S223 is specifically as follows: The via temperature data of the circuit board via material is statistically analyzed based on the dynamic bending frequency data of the circuit board, thereby obtaining high-temperature via temperature data; Obtain circuit board heat dissipation path data and circuit board electronic component data; A thermal coupling model of the circuit board is constructed according to the heat dissipation path data of the circuit board and the electronic component data of the circuit board, thereby obtaining a thermal coupling model of the circuit board; Extracting high-temperature via position features according to high-temperature via temperature data, thereby obtaining high-temperature via position data; Perform via heat dissipation simulation on the high-temperature via position data according to the circuit board thermal coupling model to obtain via heat dissipation data; The dynamic bending stress of the via is calculated based on the via heat dissipation data, so as to obtain the bending thermal stress data of the via of the circuit board.

6. The method for predicting the dynamic bending fatigue life of a circuit board according to claim 1, characterized in that: Step S3 is specifically as follows: Step S31: extracting circuit board thickness features and circuit board layer number features according to the circuit board dynamic bending test data, thereby obtaining circuit board thickness data and circuit board layer number data; Step S32: performing layer classification according to the circuit board layer number data, thereby obtaining conductive layer data and insulating layer data; Step S33: performing a dynamic bending thermal expansion test on the circuit board thickness data according to the circuit board dynamic bending frequency data, thereby obtaining the circuit board thickness dynamic bending thermal expansion data; Step S34: performing a conductive layer peeling analysis on the conductive layer data according to the dynamic bending thermal expansion data of the circuit board thickness, thereby obtaining the conductive layer peeling data; Step S35: performing insulation stripping analysis on the insulation layer data according to the dynamic bending thermal expansion data of the circuit board thickness, thereby obtaining insulation stripping data; Step S36: merging the circuit board interlayer stripping data according to the conductive layer stripping data and the insulating layer stripping data, thereby obtaining the circuit board interlayer stripping data.

7. The method for predicting the dynamic bending fatigue life of a circuit board according to claim 6, characterized in that: Step S34 is specifically as follows: Step S341: simulating the thermal expansion stress of the conductive layer according to the dynamic bending thermal expansion data of the circuit board thickness, thereby obtaining the thermal expansion stress data of the conductive layer; Step S342: drawing a stress distribution area map according to the thermal expansion stress data of the conductive layer, thereby obtaining a thermal expansion stress distribution area map of the conductive layer; Step S343: identifying the stress concentration distribution area according to the conductive layer thermal expansion stress distribution area diagram, thereby obtaining the conductive layer thermal expansion stress concentration distribution area data; Step S344: obtaining yield strength data of the conductive layer material; Step S345: performing stress intensity comparison on the data of the concentrated distribution area of ​​thermal expansion stress of the conductive layer according to the yield strength data of the conductive layer material, so as to obtain high-risk stress intensity data; Step S346: Conducting a conductive layer peeling risk assessment based on the high-risk stress intensity data, thereby obtaining conductive layer peeling data.

8. The method for predicting the dynamic bending fatigue life of a circuit board according to claim 6, characterized in that: Step S35 is specifically as follows: Step S351: simulating the thermal expansion stress of the insulation layer according to the dynamic bending thermal expansion data of the circuit board thickness, thereby obtaining the thermal expansion stress data of the insulation layer; Step S352: performing dynamic bending thermal cycle statistics according to the dynamic bending thermal expansion data of the circuit board thickness, thereby obtaining dynamic bending thermal cycle data; Step S353: performing thermal expansion stress accumulation calculation on the thermal expansion stress data of the insulation layer according to the dynamic bending thermal cycle data, thereby obtaining the thermal expansion stress accumulation data of the insulation layer; Step S354: performing microcrack formation analysis on the insulation layer data according to the insulation layer thermal expansion stress accumulation data, thereby obtaining insulation layer microcrack formation data; Step S355: Perform insulation layer peeling risk assessment based on the insulation layer microcrack formation data to obtain insulation layer peeling data.

9. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the method for predicting the dynamic bending fatigue life of a circuit board as claimed in any one of claims 1 to 8 is implemented.

10. A prediction system for dynamic bending fatigue life of a circuit board, characterized in that: Used to execute the prediction method of the dynamic bending fatigue life of a circuit board as claimed in claim 1, the prediction system of the dynamic bending fatigue life of the circuit board comprises: Circuit board dynamic bending test module: used to obtain circuit board dynamic bending condition data, and perform circuit board dynamic bending test according to the circuit board dynamic bending condition data, so as to obtain circuit board dynamic bending test data; Circuit board dynamic bending analysis module: used to extract circuit board test material features according to circuit board dynamic bending test data, so as to obtain circuit board test material data; perform circuit board dynamic bending analysis according to circuit board test material data, so as to obtain circuit board material dynamic bending data; Circuit board interlayer peeling analysis module: used to extract circuit board thickness features and circuit board layer number features according to circuit board dynamic bending test data, so as to obtain circuit board thickness data and circuit board layer number data; perform circuit board interlayer peeling analysis according to circuit board thickness data and circuit board layer number data, so as to obtain circuit board interlayer peeling data; Circuit board crack propagation analysis module: used to construct a circuit board dynamic bending fatigue life prediction model based on the circuit board material dynamic bending data and the circuit board interlayer peeling data, thereby obtaining a circuit board dynamic bending fatigue life prediction model; perform crack propagation analysis based on the circuit board dynamic bending test data, thereby obtaining circuit board crack propagation data; Wire board dynamic bending fatigue life prediction module: used to perform dynamic bending fatigue life prediction on circuit board crack extension data according to the wire board dynamic bending fatigue life prediction model, so as to obtain the wire board dynamic bending fatigue life prediction data, and upload it to the circuit board management cloud platform to perform the circuit board dynamic bending fatigue life prediction task.

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