Memory device including voltage generation circuit and operating method of memory device

Abstract

A memory device including a voltage generation circuit and an operating method of the memory device are disclosed. The memory device includes: a memory cell array including a plurality of memory cells; and a peripheral circuit configured to perform a plurality of operations on the memory cell array by using the plurality of operation voltages. The peripheral circuit includes a voltage generation circuit that includes a first pump block, a second pump block, and a first common pump block, and generates the plurality of operating voltages. The voltage generation circuit connects the first pump block and the first common pump block in parallel to generate a first operating voltage among the plurality of operating voltages, and connects the first common pump block and the second pump block in series to generate a second operating voltage among the plurality of operating voltages.

Description

[0001] This application claims the priority of Korean Patent Application No. 10-2023-0118965 filed on September 7, 2023, in the Korean Intellectual Property Office, and Korean Patent Application No. 10-2023-0167068 filed on November 27, 2023, in the Korean Intellectual Property Office, the disclosures of which are incorporated herein by reference in their entirety. Technical Field

[0002] Embodiments of the present disclosure described herein relate to a semiconductor memory, and more particularly, to a memory device including a voltage generating circuit and an operating method of the memory device. Background Art

[0003] Semiconductor memories are classified as volatile memories (such as static random access memory (SRAM) or dynamic random access memory (DRAM)) or nonvolatile memories (such as flash memory, phase change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), or ferroelectric RAM (FRAM)). Volatile memories lose data stored therein when power is disconnected, while nonvolatile memories retain data stored therein even when power is disconnected.

[0004] The flash memory device operates by using various operating voltages. The flash memory device generates various operating voltages by using a voltage generating circuit. In this case, since various operating voltages (e.g., read voltage, program voltage, and erase voltage) have various levels or correspond to various load sizes, the voltage generating circuit generates the operating voltage by using a voltage pump or a charge pump suitable for the characteristics of each operating voltage. However, when a voltage pump is used for each of the characteristics of the operating voltage, the area (or size) of the voltage generating circuit increases. Summary of the invention

[0005] Embodiments of the present disclosure provide a memory device including a voltage generating circuit with reduced cost and improved performance, and an operating method of the memory device.

[0006] According to one embodiment, a memory device includes: a memory cell array including a plurality of memory cells; and a peripheral circuit configured to perform a plurality of operations on the memory cell array by using a plurality of operating voltages. The peripheral circuit includes a voltage generating circuit, the voltage generating circuit includes a first pump block, a second pump block, and a first common pump block, and generates the plurality of operating voltages. The voltage generating circuit connects the first pump block and the first common pump block in parallel to generate a first operating voltage among the plurality of operating voltages; and connects the first common pump block and the second pump block in series to generate a second operating voltage among the plurality of operating voltages.

[0007] According to one embodiment, a memory device includes: a memory cell array including a plurality of memory cells; a control logic circuit generating a switching signal in response to a command received from an external device; and a voltage generating circuit including a first pump block, a second pump block, and a first common pump block. In response to the switching signal, the voltage generating circuit generates a first operating voltage by using the first pump block and the first common pump block, and generates a second operating voltage by using the second pump block and the first common pump block.

[0008] According to one embodiment, a method for operating a memory device includes: receiving an operation command from an external device; when the operation command is a read command, performing a read operation based on a read voltage; and when the operation command is a program command, performing a program operation based on a program voltage. The memory device connects a first pump block, a first common pump block, and a second common pump block in parallel to generate a read voltage; and connects the first common pump block and the second pump block in series to generate a program voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The above and other objects and features of the present disclosure will become apparent by describing embodiments of the present disclosure in detail with reference to the attached drawings.

[0010] Figure 1 is a block diagram illustrating a memory device according to an embodiment of the present disclosure.

[0011] Figure 2 is a diagram showing a voltage generating circuit.

[0012] Figure 3 It is shown Figure 1 Schematic diagram of a voltage generating circuit.

[0013] Figure 4 and Figure 5 Is used to describe Figure 3 FIG. 1 is a diagram of the operation of a voltage generating circuit.

[0014] Figure 6 It is shown Figure 1 Block diagram of a voltage generating circuit.

[0015] Figures 7 to 9 Is used to describe Figure 6 FIG. 1 is a diagram of the operation of a voltage generating circuit.

[0016] Fig.10 It is shown Figure 1 Block diagram of a voltage generating circuit.

[0017] Figures 11 to 15 Is used to describe Fig.10 FIG. 1 is a diagram of the operation of a voltage generating circuit.

[0018] Fig.16 It is shown Figure 1 A flow chart of the operation of a memory device.

[0019] Fig.17 is a diagram for describing a memory device according to an embodiment of the present disclosure.

[0020] Fig.18 is a block diagram illustrating a memory system according to an embodiment of the present disclosure.

[0021] Fig.19 is a diagram illustrating a system according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0022] Hereinafter, embodiments of the present disclosure will be described in detail and clearly to the extent that a person having ordinary skill in the art can easily perform the present disclosure.

[0023] Figure 1 1 is a block diagram showing a memory device according to an embodiment of the present disclosure. In one embodiment, the memory device 100 may be a non-volatile memory device including a NAND flash memory. However, the present disclosure is not limited thereto. Figure 1 , the memory device 100 may include a memory cell array 110, a row address decoding circuit (or row decoding circuit) 120, a page buffer circuit 130, a data input / output (I / O) circuit 140, a buffer circuit 150, a control logic circuit 160 and a voltage generating circuit 170.

[0024] The memory cell array 110 may include a plurality of memory blocks. Each of the plurality of memory blocks includes a plurality of memory cells. Each of the plurality of memory blocks may be connected to the row decoding circuit 120 through at least one ground selection line GSL, a word line WL, and at least one string selection line SSL. The plurality of memory blocks may be connected to a plurality of bit lines BL in common. The plurality of memory blocks may be connected to the page buffer circuit 130 through a plurality of bit lines BL. In one embodiment, each of the plurality of memory cells may be operated as a single-level cell (SLC), a multi-level cell (MLC), a triple-level cell (TLC), a quad-level cell (QLC), a penta-level cell (PLC), etc., depending on the mode of operation.

[0025] In one embodiment, each of the plurality of memory blocks may be a unit of erase operation. Memory cells included in the same memory block among the plurality of memory blocks may be erased simultaneously. In one embodiment, each of the plurality of memory blocks may be divided into sub-blocks. Each of the plurality of sub-blocks may correspond to a unit of erase operation. Memory cells included in the same sub-block among the plurality of sub-blocks may be erased simultaneously.

[0026] The row decoding circuit 120 may be connected to the memory cell array 110 through the string selection line SSL, the word line WL, and the ground selection line GSL. The row decoding circuit 120 may operate under the control of the control logic circuit 160. For example, under the control of the control logic circuit 160, the row decoding circuit 120 may decode the row address RA received from the buffer circuit 150; based on the decoding result, the row decoding circuit 120 may control or drive the string selection line SSL, the word line WL, and the ground selection line GSL, or may control the voltages applied to the string selection line SSL, the word line WL, and the ground selection line GSL.

[0027] The page buffer circuit 130 may be connected to the memory cell array 110 through a plurality of bit lines BL. The page buffer circuit 130 may be connected to the data input / output circuit 140 through a plurality of data lines DL. The page buffer circuit 130 may operate under the control of the control logic circuit 160. For example, in a program operation of the memory device 100, the page buffer circuit 130 may store data to be programmed in the memory cell array 110 under the control of the control logic circuit 160. In a read operation of the memory device 100, the page buffer circuit 130 may sense voltages of the plurality of bit lines BL and may store the sensed voltages as read data.

[0028] The data input / output circuit 140 may be connected to the page buffer circuit 130 through a plurality of data lines DL. The data input / output circuit 140 may receive a column address CA from the buffer circuit 150. The data input / output circuit 140 may transfer read data read by the page buffer circuit 130 to the buffer circuit 150 according to the column address CA. The data input / output circuit 140 may transfer data received from the buffer circuit 150 to the page buffer circuit 130 based on the column address CA.

[0029] The buffer circuit 150 may receive a command CMD and an address ADDR through the first signal line SIGL1 and may exchange data “DATA” with an external device (eg, a controller) through the first signal line SIGL1. In one embodiment, the first signal line SIGL1 may be a data signal line (eg, a DQ line).

[0030] The buffer circuit 150 may operate under the control of the control logic circuit 160. The buffer circuit 150 may transmit a command CMD to the control logic circuit 160. The buffer circuit 150 may transmit a row address RA of the address ADDR to the row decoding circuit 120, and may transmit a column address CA of the address ADDR to the data input / output circuit 140. The buffer circuit 150 may exchange data “DATA” with the data input / output circuit 140.

[0031] The control logic circuit 160 may exchange a control signal CTRL with an external device (e.g., a controller) through a second signal line SIGL2. The control logic circuit 160 may control the buffer circuit 150 based on the control signal CTRL so that the buffer circuit 150 routes a command CMD, an address ADDR, and data "DATA". The control logic circuit 160 may decode the command CMD received from the buffer circuit 150, and may control the memory device 100 or various components of the memory device 100 based on the decoding result.

[0032] Under the control of the control logic circuit 160, the voltage generation circuit 170 may generate various operation voltages VOP for use in the memory device 100. For example, in a program operation of the memory device 100, the voltage generation circuit 170 may generate a program voltage to be provided to a selected word line among a plurality of word lines WL. In a read operation of the memory device 100, the voltage generation circuit 170 may generate a read voltage to be provided to a selected word line among a plurality of word lines WL. In an erase operation of the memory device 100, the voltage generation circuit 170 may generate an erase voltage to be provided to a substrate or a common source line of the memory device 100. The various operation voltages (e.g., program voltage, read voltage, and erase voltage) described above are provided as examples, and the various operation voltages used by the memory device 100 may also include various voltages such as a non-select read voltage, a pass voltage, and a verification voltage.

[0033] In one embodiment, the voltage generating circuit 170 can generate various operating voltages VOP by using an external voltage EVC. For example, the voltage generating circuit 170 may include a plurality of voltage pumps (or charge pumps). Each of the plurality of voltage pumps can generate various voltage levels by using the external voltage EVC. The voltage generating circuit 170 can generate various operating voltages VOP by using a plurality of voltage pumps.

[0034] In one embodiment, the remaining components except the memory cell array 110 (e.g., the row decoding circuit 120, the page buffer circuit 130, the data input / output circuit 140, the buffer circuit 150, the control logic circuit 160, and the voltage generating circuit 170) may constitute a peripheral circuit, and the peripheral circuit may perform various operations (e.g., a read operation, a programming operation, or an erase operation) of the memory device 100 or the memory cell array 110 by using various operating voltages generated by the voltage generating circuit 170.

[0035] Figure 2 is a diagram showing a voltage generating circuit. For ease of description, it is assumed that Figure 2The voltage generating circuit 10 generates first to third operating voltages VOP1, VOP2, and VOP3 used in the memory device 100. However, the present disclosure is not limited thereto, and the voltage generating circuit 10 may perform (or generate) various other operating voltages.

[0036] Reference Figure 2 , the voltage generating circuit 10 may include a plurality of voltage pumps 11 to 13. The plurality of voltage pumps 11 to 13 may respectively generate a plurality of operating voltages VOP1 to VOP3. For example, the first voltage pump 11 may generate a first operating voltage VOP1 by using an external voltage EVC. The second voltage pump 12 may generate a second operating voltage VOP2 by using an external voltage EVC. The third voltage pump 13 may generate a third operating voltage VOP3 by using an external voltage EVC.

[0037] In one embodiment, the first voltage pump 11 to the third voltage pump 13 may have different structures according to the characteristics of the corresponding operating voltages VOP1, VOP2 and VOP3. For example, each of the plurality of voltage pumps 11 to 13 may include a plurality of unit pumps. The unit pump of the first voltage pump 11 may be connected according to the first series size s1 and the first parallel size p1. The unit pump of the second voltage pump 12 may be connected according to the second series size s2 and the second parallel size p2. The unit pump of the third voltage pump 13 may be connected according to the third series size s3 and the third parallel size p3. In one embodiment, in each voltage pump, the series size s1, s2 or s3 may indicate the number of unit pumps connected in series, and the parallel size p1, p2 or p3 may indicate the number of unit pumps connected in parallel. That is, the unit pumps included in the first voltage pump 11 may be connected in series up to s1, and the unit pumps connected in series up to s1 may be connected in parallel up to p1.

[0038] Below, for ease of description, the cell pumps connected in series are referred to as "stages". That is, the first voltage pump 11 may include "p1" stages connected in parallel, and each stage may include "s1" cell pumps connected in series. The second voltage pump 12 may include "p2" stages connected in parallel, and each stage may include "s2" cell pumps connected in series. The third voltage pump 13 may include "p3" stages connected in parallel, and each stage may include "s3" cell pumps connected in series.

[0039] The above description is provided as an example to describe the embodiments of the present disclosure, and the present disclosure is not limited thereto. For example, a parallel size such as p1, p2, or p3 may not be limited to the number of stages connected in parallel, and may indicate the size of a unit pump included in the stage. That is, a large parallel size may indicate that the size of a unit pump included in the stage is large. As an example, a case where the size of a unit pump is large may be suitable for a larger load.

[0040] The operating voltages VOP1 to VOP3 generated from the plurality of voltage pumps 11 to 13, respectively, may have different characteristics. For example, the levels of the operating voltages VOP1, VOP2, and VOP3 may be different from each other, or the load sizes corresponding to the operating voltages VOP1, VOP2, and VOP3, respectively, may be different from each other. For example, the target level of the first operating voltage VOP1 may be relatively low, and the load corresponding to the first operating voltage VOP1 may be large. The second operating voltage VOP2 may be relatively high, and the load corresponding to the second operating voltage VOP2 may be relatively small. The third operating voltage VOP3 may be relatively high, and the load corresponding to the third operating voltage VOP3 may be medium.

[0041] In this case, the number of parallel stages included in the first voltage pump 11 (i.e., p1) may be relatively large, and the number of serially connected unit pumps included in each stage of the first voltage pump 11 (i.e., s1) may be relatively small. The number of parallel stages included in the second voltage pump 12 (i.e., p2) may be relatively small, and the number of serially connected unit pumps included in each stage of the second voltage pump 12 (i.e., s2) may be relatively large. The number of parallel stages included in the third voltage pump 13 (i.e., p3) may be relatively medium, and the number of serially connected unit pumps included in each stage of the third voltage pump 13 (i.e., s3) may be relatively large.

[0042] In other words, as the number of serially connected unit pumps included in one stage increases, an operating voltage of a relatively high level may be generated, and as the number of parallel-connected stages increases, an operating voltage suitable for a relatively large load may be generated.

[0043] As described above, since the structure of the voltage pump varies according to the characteristics of the operating voltage (ie, target level and load state), various structures of the voltage pump are required to generate various operating voltages required by the memory device 100. In this case, the area of ​​the voltage generating circuit 10 may increase.

[0044] Figure 3 It is shown Figure 1 Schematic diagram of a voltage generating circuit. Figure 1 and Figure 3 , the voltage generating circuit 170 may include a first pump block PB1 , a second pump block PB2 , a common pump block PB_C, and a switch block (or switching block) 171 .

[0045] The first pump block PB1 , the second pump block PB2 , and the common pump block PB_C may be operated by using an external voltage EVC For example, each of the first pump block PB1 , the second pump block PB2 , and the common pump block PB_C may generate an output voltage by using the external voltage EVC.

[0046] The switch block 171 may control the connection relationship between the first pump block PB1, the second pump block PB2, and the common pump block PB_C in response to the switch signal SS. For example, the control logic circuit 160 may provide the switch signal SS to the voltage generation circuit 170 according to the operation of the memory device 100. When the first operating voltage VOP1 is required in the operation of the memory device 100, the switch block 171 may output the first operating voltage VOP1 based on the output V1 of the first pump block PB1 and the output VC of the common pump block PB_C in response to the switch signal SS. Alternatively, when the second operating voltage VOP2 or the third operating voltage VOP3 is required in the operation of the memory device 100, the switch block 171 may provide the output VC of the common pump block PB_C to the second pump block PB2 in response to the switch signal SS. In this case, the second pump block PB2 can generate the second operating voltage VOP2 or the third operating voltage VOP3 by using the output VC of the common pump block PB_C and the external voltage EVC.

[0047] In one embodiment, when the first operating voltage VOP1 is generated, the first pump block PB1 and the common pump block PB_C may be connected in parallel through the switch block 171, and the second pump block PB2 may not be used. When the second operating voltage VOP2 or the third operating voltage VOP3 is generated, the common pump block PB_C and the second pump block PB2 may be connected in series through the switch block 171, and the first pump block PB1 may not be used. That is, because the common pump block PB_C is used or shared in common to generate the first operating voltage VOP1 to the third operating voltage VOP3, the entire area of ​​the voltage generating circuit 170 may be reduced. The reduction in the area of ​​the voltage generating circuit 170 may make it possible to add any other components (e.g., a memory cell or any other peripheral circuit). This may mean that the bit density of the memory device 100 is improved.

[0048] Figure 4 and Figure 5 Is used to describe Figure 3 1. Hereinafter, for ease of description, it is assumed that the first operating voltage VOP1 is a read voltage VRD of the memory device 100, the second operating voltage VOP2 is a program voltage VPGM of the memory device 100, and the third operating voltage VOP3 is an erase voltage VERS of the memory device 100. However, the present disclosure is not limited thereto.

[0049] Reference Figure 1 , Figure 3 and Figure 4, when the memory device 100 performs a read operation, it may be necessary to provide a read voltage VRD to a selected word line or an unselected word line. In this case, the voltage generating circuit 170 may generate a read voltage VRD (i.e., a first operating voltage VOP1) in response to a switching signal SS from the control logic circuit 160. For example, the switch block 171 of the voltage generating circuit 170 may connect the output V1 of the first pump block PB1 and the output VC of the common pump block PB_C in parallel in response to the switching signal SS. In this way, the read voltage VRD (i.e., the first operating voltage VOP1) may be output.

[0050] In one embodiment, the read voltage VRD may be an operating voltage corresponding to a relatively large load among the operating voltages of the memory device 100. Therefore, when the first pump block PB1 and the common pump block PB_C are connected in parallel, the read voltage VRD (ie, the first operating voltage VOP1) may handle a relatively large load.

[0051] In one embodiment, when the first pump block PB1 and the common pump block PB_C are connected in parallel, the first pump block PB1 and the common pump block PB_C may operate as a voltage pump (e.g., a read voltage pump VP_RD) for generating a read voltage VRD. In one embodiment, when the read voltage VRD is generated by using the first pump block PB1 and the common pump block PB_C, the second pump block PB2 may not operate.

[0052] Next, refer to Figure 1 , Figure 3 and Figure 5 , when the memory device 100 performs a programming operation, it may be necessary to provide a programming voltage VPGM to a selected word line. Alternatively, when the memory device 100 performs an erase operation, it may be necessary to provide an erase voltage VERS to a substrate or a common source line of the memory device 100. In this case, the voltage generating circuit 170 may generate a programming voltage VPGM or an erase voltage VERS (i.e., a second operating voltage VOP2 or a third operating voltage VOP3) in response to a switching signal SS from the control logic circuit 160. For example, the switch block 171 of the voltage generating circuit 170 may connect the output VC of the common pump block PB_C in series to the second pump block PB2 in response to the switching signal SS. In this way, the programming voltage VPGM or the erase voltage VERS (i.e., the second operating voltage VOP2 or the third operating voltage VOP3) may be output from the second pump block PB2.

[0053] In one embodiment, the program voltage VPGM or the erase voltage VERS may be an operating voltage having a relatively high target level among the operating voltages of the memory device 100. Therefore, when the output VC of the common pump block PB_C is connected in series to the second pump block PB2, a relatively high level of the program voltage VPGM or the erase voltage VERS may be generated.

[0054] In one embodiment, when the common pump block PB_C and the second pump block PB2 are connected in series, the common pump block PB_C and the second pump block PB2 may operate as a voltage pump (e.g., a programming voltage pump VP_PGM or an erasure voltage pump VP_ERS) for generating a programming voltage VPGM or an erasure voltage VERS. In one embodiment, when the programming voltage VPGM or the erasure voltage VERS is generated by using the common pump block PB_C and the second pump block PB2, the first pump block PB1 may not operate.

[0055] As described above, the voltage generating circuit 170 according to an embodiment of the present disclosure may use or share a common pump block PB_C for the purpose of generating various operating voltages. Therefore, since each operating voltage does not require a separate pump block, the entire area of ​​the voltage generating circuit 170 may be reduced.

[0056] Figure 6 It is shown Figure 1 In one embodiment, it can be understood that Figure 1 The voltage generating circuit 170 is Figure 6 Hereinafter, for convenience of description, it is assumed that the voltage generating circuit 170-1 generates the first to third operating voltages VOP1, VOP2, and VOP3 under the control of the control logic circuit 160. However, the present disclosure is not limited thereto, and the voltage generating circuit 170-1 may also generate other operating voltages.

[0057] Reference Figure 1 and Figure 6 The voltage generating circuit 170 - 1 may include a first pump block PB1 , a second pump block PB2 , a third pump block PB3 , a first common pump block PB_C1 , a second common pump block PB_C2 , a read voltage generator GEN_RD, an erase voltage generator GEN_ERS, and a switch block 171 .

[0058] The first pump block PB1, the first common pump block PB_C1, the second common pump block PB_C2, the second pump block PB2, and the third pump block PB3 may operate in response to an external voltage EVC. In one embodiment, the first pump block PB1 may have a first series size s1 and a first parallel size p1, the second pump block PB2 may have a second series size s2 and a second parallel size p2, and the third pump block PB3 may have a third series size s3 and a third parallel size p3. The first common pump block PB_C1 may have a first series size s1 and a second parallel size p2, and the second common pump block PB_C2 may have a first series size s1 and a third parallel size p3.

[0059] The switch block 171 may control the connection of the outputs of the first common pump block PB_C1 and the second common pump block PB_C2 in response to the switching signal SS from the control logic circuit 160. For example, in a read operation of the memory device 100, the switch block 171 may transfer or connect the outputs of the first common pump block PB_C1 and the second common pump block PB_C2 to the read voltage generator GEN_RD. In a program operation of the memory device 100, the switch block 171 may transfer or connect the output of the first common pump block PB_C1 to the second pump block PB2. In an erase operation of the memory device 100, the switch block 171 may transfer or connect the output of the first common pump block PB_C1 to the second pump block PB2, and may transfer or connect the output of the second common pump block PB_C2 to the third pump block PB3.

[0060] The read voltage generator GEN_RD may generate a first operating voltage VOP1 based on an output of the first pump block PB1 and an output of the switch block 171. For example, in a read operation of the memory device 100, the read voltage generator GEN_RD may connect the output of the first pump block PB1, the output of the first common pump block PB_C1, and the output of the second common pump block PB_C2 in parallel, and may output the first operating voltage VOP1.

[0061] The erase voltage generator GEN_ERS may generate a third operating voltage VOP3 based on the output of the second pump block PB2 and the output of the third pump block PB3. For example, in an erase operation of the memory device 100, the erase voltage generator GEN_ERS may connect the output of the second pump block PB2 and the output of the third pump block PB3 in parallel and may output the third operating voltage VOP3.

[0062] As described above, since the first pump block PB1, the first common pump block PB_C1, and the second common pump block PB_C2 are connected in parallel, a first operating voltage VOP1 corresponding to a relatively large load may be generated. Alternatively, when the first common pump block PB_C1 and the second pump block PB2 are connected in series, a second operating voltage VOP2 having a relatively high level may be generated. Alternatively, since the first common pump block PB_C1 and the second pump block PB2 are connected in series, the second common pump block PB_C2 and the third pump block PB3 are connected in series, and the second pump block PB2 and the third pump block PB3 are connected in parallel, a third operating voltage VOP3 corresponding to a relatively large load and having a relatively high level may be generated. In this case, since the first common pump block PB_C1 and the second common pump block PB_C2 are commonly used or shared to generate the corresponding operating voltage, the entire area of ​​the voltage generating circuit 170-1 may be reduced.

[0063] Figures 7 to 9 Is used to describe Figure 6 The operation of the voltage generating circuit will be shown in FIG. Figures 7 to 9 The configuration in which the voltage generating circuit 170 - 1 generates the read voltage VRD, the program voltage VPGM, or the erase voltage VERS is described However, the present disclosure is not limited thereto, and the voltage generating circuit 170 - 1 may also generate various other operating voltages.

[0064] Reference Figure 1 , Figure 6 and Figure 7 , the memory device 100 may perform a read operation. In this case, the voltage generating circuit 170 - 1 may generate a read voltage VRD in response to a switching signal SS from the control logic circuit 160 .

[0065] For example, in a read operation of the memory device 100, the first pump block PB1, the first common pump block PB_C1, and the second common pump block PB_C2 may be activated. In response to the switching signal SS, the switch block 171 provides the outputs of the first common pump block PB_C1 and the second common pump block PB_C2 to the read voltage generator GEN_RD. The read voltage generator GEN_RD may connect the outputs of the first pump block PB1, the first common pump block PB_C1, and the second common pump block PB_C2 in parallel, and may output a first operating voltage VOP1 (or a read voltage VRD).

[0066] In one embodiment, as described above, in the read operation of the memory device 100, the read voltage VRD may be generated based on the first pump block PB1, the first common pump block PB_C1, and the second common pump block PB_C2. That is, in the read operation of the memory device 100, the first pump block PB1, the first common pump block PB_C1, and the second common pump block PB_C2 may be operated as a read voltage pump. Because the pump blocks (e.g., PB1, PB_C1, and PB_C2) included in the read voltage pump are connected in parallel, each pump block may have an output voltage of the same level. In this case, as described above, the series size of each pump block may correspond to the level of the output voltage. That is, the first pump block PB1, the first common pump block PB_C1, and the second common pump block PB_C2 may have the same series size (e.g., s1). In one embodiment, because the pump blocks (e.g., PB1, PB_C1, and PB_C2) included in the read voltage pump are connected in parallel, the total parallel size of the read voltage pump may be (p1+p2+p3). That is, as the parallel size increases, the read voltage VRD corresponding to a relatively large load may be normally generated.

[0067] In one embodiment, when the memory device 100 performs a read operation, the second pump block PB2 and the third pump block PB3 may be deactivated or may not be used.

[0068] Next, refer to Figure 1 , Figure 6 and Figure 8 , the memory device 100 may perform a program operation. In this case, the voltage generating circuit 170 - 1 may generate the program voltage VPGM in response to the switching signal SS from the control logic circuit 160 .

[0069] For example, in a programming operation of the memory device 100, the first common pump block PB_C1 and the second pump block PB2 may be activated. In response to the switching signal SS, the switch block 171 may transmit the output of the first common pump block PB_C1 to the second pump block PB2. The second pump block PB2 and the first common pump block PB_C1 may be connected in series. The second pump block PB2 may output a second operating voltage VOP2 (or a programming voltage VPGM).

[0070] In one embodiment, as described above, in the programming operation of the memory device 100, the programming voltage VPGM may be generated based on the first common pump block PB_C1 and the second pump block PB2. That is, in the programming operation of the memory device 100, the first common pump block PB_C1 and the second pump block PB2 may be operated as a programming voltage pump. Because the pump blocks (e.g., PB_C1 and PB2) included in the programming voltage pump are connected in series, the pump blocks may have the same parallel size (e.g., p2) for efficient operation. In one embodiment, because the pump blocks (e.g., PB_C1 and PB2) included in the programming voltage pump are connected in series, the total series size of the programming voltage pump may be (s1+s2). That is, as the series size increases, a programming voltage VPGM having a relatively high level may be normally generated.

[0071] In one embodiment, when the memory device 100 performs a program operation, the first pump block PB1, the second common pump block PB_C2, and the third pump block PB3 may be deactivated. In one embodiment, when the memory device 100 performs a program operation, the first pump block PB1 may be used to generate a pass voltage or a program verification voltage.

[0072] Next, refer to Figure 1 , Figure 6 and Fig. 9 , the memory device 100 may perform an erase operation. In this case, the voltage generating circuit 170 - 1 may generate the erase voltage VERS in response to the switching signal SS from the control logic circuit 160 .

[0073] For example, in an erase operation of the memory device 100, the first common pump block PB_C1, the second common pump block PB_C2, the second pump block PB2, and the third pump block PB3 may be activated. In response to the switching signal SS, the switch block 171 may transmit the output of the first common pump block PB_C1 to the second pump block PB2, and may transmit the output of the second common pump block PB_C2 to the third pump block PB3. The second pump block PB2 and the first common pump block PB_C1 may be connected in series, and the third pump block PB3 and the second common pump block PB_C2 may be connected in series. The output of the second pump block PB2 and the output of the third pump block PB3 may be provided to the erase voltage generator GEN_ERS. The erase voltage generator GEN_ERS may connect the output of the second pump block PB2 and the output of the third pump block PB3 in parallel, and may generate a third operating voltage VOP3 (or erase voltage VERS).

[0074] In one embodiment, as described above, in the erase operation of the memory device 100, the erase voltage VERS may be generated based on the first common pump block PB_C1, the second common pump block PB_C2, the second pump block PB2, and the third pump block PB3. That is, in the erase operation of the memory device 100, the first common pump block PB_C1, the second common pump block PB_C2, the second pump block PB2, and the third pump block PB3 may be used as an erase voltage pump.

[0075] Because the pump blocks (e.g., PB_C1, PB_C2, PB2, and PB3) included in the erase voltage pump are connected in series or in parallel, some pump blocks may have the same parallel size for efficient operation. For example, the first common pump block PB_C1 and the second pump block PB2 connected in series may have the same parallel size (e.g., p2). The second common pump block PB_C2 and the third pump block PB3 connected in series may have the same parallel size (e.g., p3). In one embodiment, because the output of the second pump block PB2 and the output of the third pump block PB3 are connected in parallel through the erase voltage generator GEN_ERS, the output of the second pump block PB2 and the output of the third pump block PB3 may have the same level. Because the output of the second pump block PB2 is generated by the first common pump block PB_C1 and the second pump block PB2 connected in series, and the output of the third pump block PB3 is generated by the second common pump block PB_C2 and the third pump block PB3 connected in series, the series size (i.e., s1+s2) of the first common pump block PB_C1 and the second pump block PB2 connected in series may be the same as the series size (i.e., s1+s3) of the second common pump block PB_C2 and the third pump block PB3 connected in series. Therefore, the erase voltage VERS having a relatively high level and corresponding to a relatively large load may be normally generated.

[0076] Fig.10 It is shown Figure 1For the convenience of description, the same description as above will be omitted to avoid redundancy. Figure 1 and Fig.10 , the voltage generating circuit 170 - 2 may include a plurality of pump blocks PB1 , PB2 , PB3 , PB4 , PB5 , and PB6 , a common pump block PB_C, a switch block 171 , a first voltage generator GEN1 , and a second voltage generator GEN2 .

[0077] The plurality of pump blocks PB1, PB2, PB3, PB4, PB5, and PB6 and the common pump block PB_C may be operated by using an external voltage EVC. Outputs of the first to third pump blocks PB1, PB2, and PB3 among the plurality of pump blocks PB1, PB2, PB3, PB4, PB5, and PB6 may be provided to a first voltage generator GEN1, and outputs of the fourth to sixth pump blocks PB4, PB5, and PB6 among the plurality of pump blocks PB1, PB2, PB3, PB4, PB5, and PB6 may be provided to a second voltage generator GEN2.

[0078] The switch block 171 may connect at least some of the output of the common pump block PB_C to the first voltage generator GEN1 , or may provide at least some of the output of the common pump block PB_C to the fourth to sixth pump blocks PB4 , PB5 , and PB6 .

[0079] The first voltage generator GEN1 may receive outputs of the first to third pump blocks PB1, PB2, and PB3 and may be connected to at least some of the outputs of the common pump block PB_C through the switch block 171. The first voltage generator GEN1 may connect the received outputs in parallel to generate a first operating voltage VOP1.

[0080] The second voltage generator GEN2 may receive outputs of the fourth to sixth pump blocks PB4, PB5, and PB6, and may connect the received outputs in parallel to output a second operating voltage VOP2. In one embodiment, at least some of the fourth to sixth pump blocks PB4, PB5, and PB6 may be connected in series to at least some of the outputs of the common pump block PB_C through the switch block 171. That is, the fourth to sixth pump blocks PB4, PB5, and PB6 may output a relatively high level voltage through the above-mentioned series connection.

[0081] In one embodiment, the first pump block PB1 may have a first series dimension s1 and a first parallel dimension p1. The second pump block PB2 may have a second series dimension s2 and a second parallel dimension p2. The third pump block PB3 may have a third series dimension s3 and a third parallel dimension p3. The fourth pump block PB4 may have a fourth series dimension s4 and a fourth parallel dimension p4. The fifth pump block PB5 may have a fifth series dimension s5 and a fifth parallel dimension p5. The sixth pump block PB6 may have a sixth series dimension s6 and a sixth parallel dimension p6.

[0082] The common pump block PB_C may have a series size of sc and a parallel size of pc. In this case, the unit pumps included in the common pump block PB_C may be divided or reconfigured into various series sizes and various parallel sizes.

[0083] As described above, the voltage generating circuit 170-2 may include a plurality of pump blocks, and various operating voltages may be generated by a combination of a plurality of pump blocks and a common pump block. In this case, the unit pumps included in the common pump block PB_C may be divided or reconfigured into various series sizes and various parallel sizes, and the reconfigured parts and the plurality of pump blocks may form a series connection, a parallel connection, or a series-parallel connection. In this case, when generating various operating voltages, because at least some of the unit pumps of the common pump block are used or shared in common, the entire area of ​​the voltage generating circuit 170-2 may be reduced.

[0084] Figures 11 to 15 Is used to describe Fig.10 For convenience of description, an example of generating some operating voltages will be described, but the present disclosure is not limited thereto.

[0085] Reference Figure 1 , Fig.10 and Fig.11 , the voltage generating circuit 170-2 may generate the 1-1th operating voltage VOP1-1 by using the first pump block PB1 and the a-th part PB_Ca of the common pump block PB_C. For example, when the 1-1th operating voltage VOP1-1 is needed, the first pump block PB1 and the a-th part PB_Ca of the common pump block PB_C may be activated. The a-th part PB_Ca of the common pump block PB_C may include some of the plurality of unit pumps included in the common pump block PB_C. The a-th part PB_Ca of the common pump block PB_C may have a series size s1 and may have a parallel size pa. That is, the unit pumps included in the a-th part PB_Ca of the common pump block PB_C may be connected in series-parallel to correspond to the series size s1 and the parallel size pa.

[0086] The switch block 171 may transmit the output of the ath portion PB_Ca of the common pump block PB_C to the first voltage generator GEN1. The first voltage generator GEN1 may connect the output of the first pump block PB1 and the output of the ath portion PB_Ca of the common pump block PB_C in parallel to output the 1-1th operating voltage VOP1-1.

[0087] In one embodiment, since the output of the first pump block PB1 and the output of the a-th part PB_Ca of the common pump block PB_C are connected in parallel as described above, the first pump block PB1 and the a-th part PB_Ca of the common pump block PB_C may have the same series size (e.g., s1). That is, the a-th part PB_Ca of the common pump block PB_C may include at least some of the plurality of unit pumps of the common pump block PB_C, and the at least some of the unit pumps may be connected to have a series size of s1.

[0088] In one embodiment, since the output of the first pump block PB1 and the output of the ath portion PB_Ca of the common pump block PB_C are connected in parallel to generate the 1-1th operating voltage VOP1-1, the parallel size of the total voltage pump for generating the 1-1th operating voltage VOP1-1 may correspond to (p1+pa).

[0089] In one embodiment, when the 1-1th operating voltage VOP1-1 is generated, the remaining pump blocks PB2, PB3, PB4, PB5, and PB6 and the remaining portion of the common pump block PB_C may be deactivated. Alternatively, the remaining pump blocks PB2, PB3, PB4, PB5, and PB6 and the remaining portion of the common pump block PB_C may be used to generate any other operating voltage.

[0090] Next, refer to Figure 1 , Fig.10 and Fig.12 , the voltage generating circuit 170-2 can generate the 1-2nd operating voltage VOP1-2 by using the third pump block PB3 and the b-th part PB_Cb of the common pump block PB_C. For example, when the 1-2nd operating voltage VOP1-2 is needed, the third pump block PB3 and the b-th part PB_Cb of the common pump block PB_C can be activated. The b-th part PB_Cb of the common pump block PB_C may include some of the multiple unit pumps included in the common pump block PB_C. The b-th part PB_Cb of the common pump block PB_C may have a series size s3 and may have a parallel size pb. That is, the unit pumps included in the b-th part PB_Cb of the common pump block PB_C may be connected in series-parallel to correspond to the series size s3 and the parallel size pb.

[0091] The switch block 171 may transmit the output of the bth portion PB_Cb of the common pump block PB_C to the first voltage generator GEN1. The first voltage generator GEN1 may connect the output of the third pump block PB3 and the output of the bth portion PB_Cb of the common pump block PB_C in parallel to output the 1-2nd operating voltage VOP1-2.

[0092] In one embodiment, since the output of the third pump block PB3 and the bth portion PB_Cb of the common pump block PB_C are connected in parallel as described above, the third pump block PB3 and the bth portion PB_Cb of the common pump block PB_C may have the same series size (eg, s3).

[0093] In one embodiment, since the output of the third pump block PB3 and the output of the b-th part PB_Cb of the common pump block PB_C are connected in parallel to generate the 1-2 th operating voltage VOP1-2, the parallel size of the total voltage pump for generating the 1-2 th operating voltage VOP1-2 may correspond to (p3+pb).

[0094] In one embodiment, when generating the 1-2nd operating voltage VOP1-2, the remaining pump blocks PB1, PB2, PB4, PB5 and PB6 and the remaining part of the common pump block PB_C may be deactivated. Alternatively, the remaining pump blocks PB1, PB2, PB4, PB5 and PB6 and the remaining part of the common pump block PB_C may be used to generate any other operating voltage.

[0095] In one embodiment, the series size (i.e., s1) of the first pump block PB1 may be smaller than the series size (i.e., s3) of the third pump block PB3. In this case, as described above, the 1-1st operating voltage VOP1-1 generated by the first pump block PB1 and the a-th portion PB_Ca of the common pump block PB_C may be lower than the 1-2nd operating voltage VOP1-2 generated by the b-th portion PB_Cb of the common pump block PB_C.

[0096] Next, refer to Figure 1 , Fig.10 and Fig.13, the voltage generating circuit 170-2 can generate the 2-1st operating voltage VOP2-1 by using the fourth pump block PB4 and the c-th part PB_Cc of the common pump block PB_C. For example, when the 2-1st operating voltage VOP2-1 is needed, the fourth pump block PB4 and the c-th part PB_Cc of the common pump block PB_C may be activated. The c-th part PB_Cc of the common pump block PB_C may include some of the multiple unit pumps included in the common pump block PB_C. The c-th part PB_Cc of the common pump block PB_C may have a series size sc and may have a parallel size p4. That is, the unit pumps included in the c-th part PB_Cc of the common pump block PB_C may be connected in series-parallel to correspond to the series size sc and the parallel size p4.

[0097] The switch block 171 may transmit the output of the c-th part PB_Cc of the common pump block PB_C to the fourth pump block PB4. The outputs of the fourth pump block PB4 and the c-th part PB_Cc of the common pump block PB_C may be connected in series. The output of the fourth pump block PB4 may be provided to the second voltage generator GEN2. The second voltage generator GEN2 may output the 2-1st operating voltage VOP2-1 based on the output of the fourth pump block PB4.

[0098] In one embodiment, since the fourth pump block PB4 and the c-th portion PB_Cc of the common pump block PB_C are connected in series as in the above description, the fourth pump block PB4 and the c-th portion PB_Cc of the common pump block PB_C may have the same parallel size (eg, p4).

[0099] In one embodiment, since the output of the cth portion PB_Cc of the common pump block PB_C and the output of the fourth pump block PB4 are connected in series to generate the 2-1st operating voltage VOP2-1, the series size of the total voltage pump for generating the 2-1st operating voltage VOP2-1 may correspond to (sc+s4).

[0100] In one embodiment, when generating the 2-1st operating voltage VOP2-1, the remaining pump blocks PB1, PB2, PB3, PB5, and PB6 and the remaining portion of the common pump block PB_C may be deactivated. Alternatively, the remaining pump blocks PB1, PB2, PB3, PB5, and PB6 and the remaining portion of the common pump block PB_C may be used to generate any other operating voltage.

[0101] Next, refer to Figure 1 , Fig.10 and Fig.14, the voltage generating circuit 170-2 can generate the 2-2nd operating voltage VOP2-2 by using the fifth pump block PB5, the sixth pump block PB6, and the d-th part PB_Cd and the e-th part PB_Ce of the common pump block PB_C. For example, when the 2-2nd operating voltage VOP2-2 is needed, the fifth pump block PB5, the sixth pump block PB6, and the d-th part PB_Cd and the e-th part PB_Ce of the common pump block PB_C may be activated. Each of the d-th part PB_Cd and the e-th part PB_Ce of the common pump block PB_C may include some of the multiple unit pumps included in the common pump block PB_C. The d-th part PB_Cd of the common pump block PB_C may have a series size sd and a parallel size p5, and the e-th part PB_Ce of the common pump block PB_C may have a series size se and a parallel size p6. That is, the unit pumps included in the dth part PB_Cd of the common pump block PB_C can be connected in series-parallel to correspond to the series size sd and the parallel size p5, and the unit pumps included in the eth part PB_Ce of the common pump block PB_C can be connected in series-parallel to correspond to the series size se and the parallel size p6.

[0102] The switch block 171 may transmit the output of the d-th portion PB_Cd of the common pump block PB_C to the fifth pump block PB5, and may transmit the output of the e-th portion PB_Ce of the common pump block PB_C to the sixth pump block PB6. The fifth pump block PB5 and the d-th portion PB_Cd of the common pump block PB_C may be connected in series, and the sixth pump block PB6 and the e-th portion PB_Ce of the common pump block PB_C may be connected in series.

[0103] The outputs of the fifth pump block PB5 and the dth part PB_Cd of the common pump block PB_C connected in series may be provided to the second voltage generator GEN2, and the outputs of the sixth pump block PB6 and the eth part PB_Ce of the common pump block PB_C connected in series may be provided to the second voltage generator GEN2. The second voltage generator GEN2 may connect the received voltages in parallel to generate the 2-2nd operating voltage VOP2-2.

[0104] In one embodiment, since the fifth pump block PB5 and the dth portion PB_Cd of the common pump block PB_C are connected in series as in the above description, the fifth pump block PB5 and the dth portion PB_Cd of the common pump block PB_C may have the same parallel size (e.g., p5). Since the sixth pump block PB6 and the eth portion PB_Ce of the common pump block PB_C are connected in series as in the above description, the sixth pump block PB6 and the eth portion PB_Ce of the common pump block PB_C may have the same parallel size (e.g., p6).

[0105] In one embodiment, because "the fifth pump block PB5 connected in series and the dth part PB_Cd of the common pump block PB_C" and "the sixth pump block PB6 connected in series and the eth part PB_Ce of the common pump block PB_C" are connected in parallel, the "series size of the fifth pump block PB5 connected in series and the dth part PB_Cd of the common pump block PB_C" and "the series size of the sixth pump block PB6 connected in series and the eth part PB_Ce of the common pump block PB_C" can be the same (i.e., sd+s5=se+s6).

[0106] In one embodiment, when generating the 2-2nd operating voltage VOP2-2, the remaining pump blocks PB1, PB2, PB3, and PB4 and the remaining portion of the common pump block PB_C may be deactivated. Alternatively, the remaining pump blocks PB1, PB2, PB3, and PB4 and the remaining portion of the common pump block PB_C may be used to generate any other operating voltage.

[0107] Next, refer to Figure 1 , Fig.10 and Fig.15 , the voltage generating circuit 170-2 may generate the 1st-3rd operating voltage VOP1-3 and the 2nd-3rd operating voltage VOP2-3. For example, when the 1st-3rd operating voltage VOP1-3 and the 2nd-3rd operating voltage VOP2-3 are needed, the second pump block PB2, the sixth pump block PB6, and the fth part PB_Cf and the gth part PB_Cg of the common pump block PB_C may be activated. Each of the fth part PB_Cf and the gth part PB_Cg of the common pump block PB_C may include some of the multiple unit pumps included in the common pump block PB_C. The fth part PB_Cf of the common pump block PB_C may have a series size s2 and a parallel size pf, and the gth part PB_Cg of the common pump block PB_C may have a series size sg and a parallel size p6. That is, the unit pumps included in the fth part PB_Cf of the common pump block PB_C can be connected in series-parallel to correspond to the series size s2 and the parallel size pf, and the unit pumps included in the gth part PB_Cg of the common pump block PB_C can be connected in series-parallel to correspond to the series size sg and the parallel size p6.

[0108] The switch block 171 may transmit the output of the f-th portion PB_Cf of the common pump block PB_C to the first voltage generator GEN1, and may provide the output of the g-th portion PB_Cg of the common pump block PB_C to the sixth pump block PB6. The first voltage generator GEN1 may connect the output of the f-th portion PB_Cf of the common pump block PB_C in parallel with the output of the second pump block PB2 to generate the 1st-3rd operating voltages VOP1-3. When the sixth pump block PB6 and the g-th portion PB_Cg of the common pump block PB_C are connected in series, the sixth pump block PB6 may output the 2nd-3rd operating voltages VOP2-3.

[0109] In one embodiment, because the fth portion PB_Cf of the common pump block PB_C and the second pump block PB2 are connected in parallel, the fth portion PB_Cf of the common pump block PB_C and the second pump block PB2 may have the same series size (e.g., s2). Because the gth portion PB_Cg of the common pump block PB_C and the sixth pump block PB6 are connected in series, the gth portion PB_Cg of the common pump block PB_C and the sixth pump block PB6 may have the same parallel size (e.g., p6).

[0110] In one embodiment, when generating the 1st-3rd operating voltage VOP1-3 and the 2nd-3rd operating voltage VOP2-3, the remaining pump blocks PB1, PB3, PB4 and PB5 and the remaining part of the common pump block PB_C may be deactivated. Alternatively, the remaining pump blocks PB1, PB3, PB4 and PB5 and the remaining part of the common pump block PB_C may be used to generate any other operating voltage.

[0111] As described above, the voltage generating circuit according to an embodiment of the present disclosure can generate various operating voltages by using a plurality of pump blocks and a common pump block. In this case, since the common pump block and any other pump blocks are connected in series or in parallel, various operating voltages can be generated. That is, when generating various operating voltages, the common pump block can be used in common or can be shared. Therefore, the entire area of ​​the voltage generating circuit can be reduced.

[0112] Fig.16 It is shown Figure 1 A flowchart of the operation of the memory device. Figure 1 and Fig.16 In operation S100, the memory device 100 may receive an operation command from an external device (eg, a controller). In one embodiment, the operation command may include a read command (RD), a program command (PGM), or an erase command (ERS).

[0113] In operation S110, the memory device 100 may determine the type of the received operation command. For example, the control logic circuit 160 of the memory device 100 may decode the operation command received from the external device and may determine the type of the operation command based on the decoding result.

[0114] When the operation command is a read command, in operation S121, the memory device 100 may generate a read voltage. For example, the voltage generating circuit 170 of the memory device 100 may generate the read voltage by using the first pump block and the common pump block. In one embodiment, the read voltage may have a relatively low level and may correspond to a relatively large load. In this case, the voltage generating circuit 170 may connect the first pump block and the common pump block in parallel, and may generate the read voltage.

[0115] When the operation command is a program command, in operation S122, the memory device 100 may generate a programming voltage. For example, the voltage generating circuit 170 of the memory device 100 may generate a programming voltage by using the second pump block and the common pump block. In one embodiment, the programming voltage may have a relatively high level and may correspond to a relatively small load. In this case, the voltage generating circuit 170 may connect the second pump block and the common pump block in series, and may generate a programming voltage.

[0116] When the operation command is an erase command, in operation S123, the memory device 100 may generate an erase voltage. For example, the voltage generation circuit 170 of the memory device 100 may generate an erase voltage by using a second pump block, a third pump block, and a common pump block. In one embodiment, the erase voltage may have a relatively high level and may correspond to a relatively medium load. In this case, the voltage generation circuit 170 may generate an erase voltage by connecting the common pump block in series with each of the second pump block and the third pump block and connecting the outputs of the second pump block and the third pump block in parallel.

[0117] In one embodiment, the memory device 100 may also generate various operating voltages necessary to perform a read operation, a program operation, and an erase operation.

[0118] In operation S130, the memory device 100 may perform an operation corresponding to the operation command based on the generated voltage. For example, when the operation command is a read command, the memory device 100 may perform a read operation by using the generated read voltage. When the operation command is a program command, the memory device 100 may perform a program operation by using the generated program voltage. When the operation command is an erase command, the memory device 100 may perform an erase operation by using the generated erase voltage.

[0119] Fig.17 is a cross-sectional view showing a memory device 500 according to an embodiment of the present disclosure.

[0120] Reference Fig.17 , the memory device 500 may have a chip-to-chip (C2C) structure. Here, in the C2C structure, after at least one upper chip including a cell area CELL and at least one lower chip including a peripheral circuit area PERI are separately manufactured, the upper chip and the lower chip may be bonded to each other by a bonding method. As an example, the bonding method may refer to a method of electrically or physically connecting a bonding metal pattern formed in the uppermost metal layer of the upper chip to a bonding metal pattern formed in the uppermost metal layer of the lower chip. For example, when the bonding metal pattern is formed of copper (Cu), the bonding method may be referred to as a "Cu-Cu bonding method". As another example, the bonding metal pattern may also be formed of aluminum (Al) or tungsten (W).

[0121] The memory device 500 may include at least one upper chip, and the at least one upper chip includes a cell region. Fig.17 As shown in , the memory device 500 may be implemented to include two upper chips. However, this is schematic, and the number of upper chips is not limited thereto. In the case where the memory device 500 is implemented to include two upper chips, the memory device 500 may be manufactured by separately manufacturing a first upper chip including a first cell area CELL1, a second upper chip including a second cell area CELL2, and a lower chip including a peripheral circuit area PERI, and thereafter connecting the first upper chip, the second upper chip, and the lower chip by a bonding method. The first upper chip may be flipped over and connected to the lower chip by a bonding method, and the second upper chip may also be flipped over and connected to the first upper chip by a bonding method. In the following description, the upper and lower portions of the first upper chip and the second upper chip are defined based on before the first upper chip and the second upper chip are flipped over. That is, in Fig.17 In the figure, the upper part of the lower chip refers to the upper part defined based on the +Z axis direction, and the upper parts of the first upper chip and the second upper chip refer to the upper parts defined based on the -Z axis direction. However, this is schematic, and only one of the first upper chip and the second upper chip can be flipped and connected by a bonding method.

[0122] Each of the peripheral circuit region PERI, and the first and second cell regions CELL1 and CELL2 of the memory device 500 may include an external pad bonding region PA, a word line bonding region WLBA, and a bit line bonding region BLBA.

[0123] The peripheral circuit region PERI may include a first substrate 210 and a plurality of circuit elements 220a, 220b, and 220c formed on the first substrate 210. An interlayer insulating layer 215 including one or more insulating layers may be provided on the plurality of circuit elements 220a, 220b, and 220c, and a plurality of metal lines connecting the plurality of circuit elements 220a, 220b, and 220c may be provided in the interlayer insulating layer 215. For example, the plurality of metal lines may include first metal lines 230a, 230b, and 230c connected to the plurality of circuit elements 220a, 220b, and 220c, respectively, and second metal lines 240a, 240b, and 240c formed on the first metal lines 230a, 230b, and 230c. The plurality of metal lines may be formed of at least one of various conductive materials. For example, the first metal lines 230 a , 230 b , and 230 c may be formed of tungsten having a relatively high resistivity, and the second metal lines 240 a , 240 b , and 240 c may be formed of copper having a relatively low resistivity.

[0124] In this specification, only the first metal lines 230a, 230b, and 230c and the second metal lines 240a, 240b, and 240c are shown and described. However, without limitation thereto, one or more additional metal lines may be further formed on the second metal lines 240a, 240b, and 240c. In this case, the second metal lines 240a, 240b, and 240c may be formed of aluminum. At least some of the additional metal lines formed on the second metal lines 240a, 240b, and 240c may be formed of copper having a lower resistivity than the aluminum of the second metal lines 240a, 240b, and 240c.

[0125] The interlayer insulating layer 215 may be disposed on the first substrate 210 and may include an insulating material such as silicon oxide or silicon nitride.

[0126] Each of the first cell region CELL1 and the second cell region CELL2 may include at least one memory block. The first cell region CELL1 may include a second substrate 310 and a common source line 320. A plurality of word lines 330 (331 to 338) may be stacked on the second substrate 310 in a direction perpendicular to the upper surface of the second substrate 310 (Z-axis direction). A string selection line and a ground selection line may be disposed above and below the word line 330, and a plurality of word lines 330 may be disposed between the string selection line and the ground selection line. Similarly, the second cell region CELL2 may include a third substrate 410 and a common source line 420, and a plurality of word lines 430 (431 to 438) may be stacked in a direction perpendicular to the upper surface of the third substrate 410 (Z-axis direction). The second substrate 310 and the third substrate 410 may be formed of various materials, and may be, for example, a silicon substrate, a silicon germanium substrate, a germanium substrate, or a substrate having a single crystal epitaxial layer grown on a single crystal silicon substrate. A plurality of channel structures CH may be formed in the first cell region CELL1 and the second cell region CELL2 .

[0127] In one embodiment, as shown in region A1 as an alternative embodiment of region "A", the channel structure CH may be disposed in the bit line bonding region BLBA and may extend in a direction perpendicular to the upper surface of the second substrate 310 to penetrate the word line 330, the string selection line, and the ground selection line. The channel structure CH may include a data storage layer, a channel layer, and a buried insulating layer. The channel layer may be electrically connected to the first metal line 350c and the second metal line 360c in the bit line bonding region BLBA. For example, the second metal line 360c may be a bit line and may be connected to the channel structure CH through the first metal line 350c. The bit line 360c may extend in a first direction (Y-axis direction) parallel to the upper surface of the second substrate 310.

[0128] In one embodiment, as shown in region A2 as an alternative embodiment of region "A", the channel structure CH may include a lower channel LCH and an upper channel UCH connected to each other. For example, the channel structure CH may be formed by a process for the lower channel LCH and a process for the upper channel UCH. The lower channel LCH may extend in a direction perpendicular to the upper surface of the second substrate 310, and may penetrate the common source line 320 and the lower word lines 331 and 332. The lower channel LCH may include a data storage layer, a channel layer, and a buried insulating layer, and may be connected to the upper channel UCH. The upper channel UCH may penetrate the upper word lines 333 to 338. The upper channel UCH may include a data storage layer, a channel layer, and a buried insulating layer, and the channel layer of the upper channel UCH may be electrically connected to the first metal line 350c and the second metal line 360c. As the channel length increases, it may be difficult to form a channel with a constant width due to process reasons. The memory device 500 according to an embodiment of the present disclosure may include a channel having improved width uniformity through a lower channel LCH and an upper channel UCH formed by sequential processes.

[0129] In the case where the channel structure CH includes a lower channel LCH and an upper channel UCH as shown in A2, a word line located near the boundary between the lower channel LCH and the upper channel UCH may be a dummy word line. For example, word lines 332 and 333 forming the boundary between the lower channel LCH and the upper channel UCH may be dummy word lines. In this case, data may not be stored in the memory cells connected to the dummy word lines. Optionally, the number of pages corresponding to the memory cells connected to the dummy word lines may be less than the number of pages corresponding to the memory cells connected to the normal word lines. The voltage level applied to the dummy word line may be different from the voltage level applied to the normal word line, and thus the effect of the uneven channel width between the lower channel LCH and the upper channel UCH on the operation of the memory device may be reduced.

[0130] Meanwhile, it is shown in A2 that the number of lower word lines 331 and 332 penetrated by the lower channel LCH is less than the number of upper word lines 333 to 338 penetrated by the upper channel UCH. However, this is exemplary, and the present disclosure is not limited thereto. In another example, the number of lower word lines penetrated by the lower channel LCH may be equal to or greater than the number of upper word lines penetrated by the upper channel UCH. In addition, the above-described structure and connection relationship of the channel structure CH disposed in the first cell region CELL1 may be identically applied to the channel structure CH disposed in the second cell region CELL2.

[0131] In the bit line bonding area BLBA, a first through electrode THV1 may be disposed in the first cell area CELL1, and a second through electrode THV2 may be disposed in the second cell area CELL2. Fig.17As shown in , the first through electrode THV1 may penetrate the common source line 320 and the plurality of word lines 330. However, this is schematic, and the first through electrode THV1 may additionally penetrate the second substrate 310. The first through electrode THV1 may include a conductive material. Alternatively, the first through electrode THV may include a conductive material surrounded by an insulating material. The second through electrode THV2 may have the same shape and structure as the first through electrode THV1.

[0132] In one embodiment, the first through electrode THV1 and the second through electrode THV2 may be electrically connected by the first through metal pattern 372d and the second through metal pattern 472d. The first through metal pattern 372d may be formed on the lower side of the first upper chip including the first cell area CELL1, and the second through metal pattern 472d may be formed on the upper side of the second upper chip including the second cell area CELL2. The first through electrode THV1 may be electrically connected to the first metal line 350c and the second metal line 360c. The second through electrode THV2 may be electrically connected to the first metal line 450c and the second metal line 460c. The lower via 371d may be formed between the first through electrode THV1 and the first through metal pattern 372d, and the upper via 471d may be formed between the second through electrode THV2 and the second through metal pattern 472d. The first through metal pattern 372d and the second through metal pattern 472d may be connected by a bonding method.

[0133] In addition, in the bit line bonding area BLBA, an upper metal pattern 252 may be formed on the uppermost metal layer of the peripheral circuit area PERI, and an upper metal pattern 392 having the same shape as the upper metal pattern 252 may be formed on the uppermost metal layer of the first cell area CELL1. The upper metal pattern 392 of the first cell area CELL1 and the upper metal pattern 252 of the peripheral circuit area PERI may be electrically connected to each other by a bonding method. In the bit line bonding area BLBA, the bit line 360c may be electrically connected to a page buffer included in the peripheral circuit area PERI. For example, some of the circuit elements 220c of the peripheral circuit area PERI may provide a page buffer, and the bit line 360c may be electrically connected to the circuit element 220c providing the page buffer through the upper bonding metal 370c of the first cell area CELL1 and the upper bonding metal 270c of the peripheral circuit area PERI.

[0134] Continue to refer to Fig.17In the word line bonding area WLBA, the word lines 330 of the first cell area CELL1 may extend in a second direction (X-axis direction) parallel to the upper surface of the second substrate 310, and may be connected to a plurality of cell contact plugs 340 (341 to 347). The first metal line 350b and the second metal line 360b may be sequentially connected to the upper portions of the cell contact plugs 340 connected to the word lines 330. In the word line bonding area WLBA, the cell contact plugs 340 may be connected to the peripheral circuit area PERI through the upper bonding metal 370b of the first cell area CELL1 and the upper bonding metal 270b of the peripheral circuit area PERI.

[0135] The cell contact plug 340 may be electrically connected to a row decoder included in the peripheral circuit region PERI. For example, some of the circuit elements 220b of the peripheral circuit region PERI may provide a row decoder, and the cell contact plug 340 may be electrically connected to the circuit element 220b providing the row decoder through the upper bonding metal 370b of the first cell region CELL1 and the upper bonding metal 270b of the peripheral circuit region PERI. In one embodiment, the operating voltage of the circuit element 220b providing the row decoder may be different from the operating voltage of the circuit element 220c providing the page buffer. For example, the operating voltage of the circuit element 220c providing the page buffer may be greater than the operating voltage of the circuit element 220b providing the row decoder.

[0136] Similarly, in the word line bonding area WLBA, the word lines 430 of the second cell area CELL2 may extend in a second direction (X-axis direction) parallel to the upper surface of the third substrate 410, and may be connected to a plurality of cell contact plugs 440 (441 to 447). The cell contact plugs 440 may be connected to the peripheral circuit area PERI through the upper metal pattern of the second cell area CELL2, the lower and upper metal patterns of the first cell area CELL1, and the cell contact plugs 348.

[0137] In the word line bonding area WLBA, the upper bonding metal 370b may be formed in the first cell area CELL1, and the upper bonding metal 270b may be formed in the peripheral circuit area PERI. The upper bonding metal 370b of the first cell area CELL1 and the upper bonding metal 270b of the peripheral circuit area PERI may be electrically connected to each other by a bonding method. The upper bonding metal 370b and the upper bonding metal 270b may be formed of aluminum, copper, or tungsten.

[0138] In the external pad bonding area PA, a lower metal pattern 371e may be formed on a lower portion of the first cell area CELL1, and an upper metal pattern 472a may be formed on an upper portion of the second cell area CELL2. The lower metal pattern 371e of the first cell area CELL1 and the upper metal pattern 472a of the second cell area CELL2 may be connected in the external pad bonding area PA by a bonding method. Similarly, an upper metal pattern 372a may be formed on an upper portion of the first cell area CELL1, and an upper metal pattern 272a may be formed on an upper portion of the peripheral circuit area PERI. The upper metal pattern 372a of the first cell area CELL1 and the upper metal pattern 272a of the peripheral circuit area PERI may be connected to each other by a bonding method.

[0139] Common source line contact plugs 380 and 480 may be disposed in the external pad bonding area PA. Common source line contact plugs 380 and 480 may be formed of a conductive material such as a metal, a metal compound, or doped polysilicon. The common source line contact plug 380 of the first cell area CELL1 may be electrically connected to the common source line 320, and the common source line contact plug 480 of the second cell area CELL2 may be electrically connected to the common source line 420. The first metal line 350a and the second metal line 360a may be sequentially stacked on the upper portion of the common source line contact plug 380 of the first cell area CELL1, and the first metal line 450a and the second metal line 460a may be sequentially stacked on the upper portion of the common source line contact plug 480 of the second cell area CELL2.

[0140] The input / output pads 205, 405, and 406 may be disposed in the external pad bonding area PA. Fig.17 , a lower insulating layer 201 may cover a lower surface of the first substrate 210, and a first input / output pad 205 may be formed on the lower insulating layer 201. The first input / output pad 205 may be connected to at least one of a plurality of circuit elements 220a disposed in the peripheral circuit region PERI through a first input / output contact plug 203, and may be separated from the first substrate 210 by the lower insulating layer 201. In addition, a side insulating layer may be disposed between the first input / output contact plug 203 and the first substrate 210, and may electrically isolate the first input / output contact plug 203 from the first substrate 210.

[0141] An upper insulating layer 401 may be formed on the third substrate 410 to cover an upper surface of the third substrate 410. A second input / output pad 405 and / or a third input / output pad 406 may be disposed on the upper insulating layer 401. The second input / output pad 405 may be connected to at least one of the plurality of circuit elements 220a disposed in the peripheral circuit region PERI through the second input / output contact plugs 403 and 303, and the third input / output pad 406 may be connected to at least one of the plurality of circuit elements 220a disposed in the peripheral circuit region PERI through the third input / output contact plugs 404 and 304.

[0142] In one embodiment, the third substrate 410 may not be disposed in a region where the input / output contact plug is disposed. For example, as shown in B, the third input / output contact plug 404 may be separated from the third substrate 410 in a direction parallel to the upper surface of the third substrate 410, may penetrate the interlayer insulating layer 415 of the second cell region CELL2, and may be connected to the third input / output pad 406. In this case, the third input / output contact plug 404 may be formed by various processes.

[0143] For example, as shown in region B1 as an alternative embodiment of region “B”, the third input / output contact plug 404 may extend in the third direction (Z-axis direction) and may have a diameter that increases toward the upper insulating layer 401. That is, although the channel structure CH described with reference to A1 has a diameter that decreases toward the upper insulating layer 401, the third input / output contact plug 404 may have a diameter that increases toward the upper insulating layer 401. For example, the third input / output contact plug 404 may be formed after the second cell region CELL2 and the first cell region CELL1 are combined by a bonding method.

[0144] For example, as shown in region B2 as an alternative embodiment of region “B”, the third input / output contact plug 404 may extend in the third direction (Z-axis direction) and may have a diameter that decreases toward the upper insulating layer 401. That is, similar to the channel structure CH, the third input / output contact plug 404 may have a diameter that decreases toward the upper insulating layer 401. For example, the third input / output contact plug 404 may be formed together with the cell contact plug 440 before the second cell region CELL2 and the first cell region CELL1 are combined by a bonding method.

[0145] In one embodiment, the input / output contact plug may be disposed to overlap with the third substrate 410. For example, as shown in C, the second input / output contact plug 403 may be formed through the interlayer insulating layer 415 of the second cell region CELL2 in the third direction (Z-axis direction), and may be electrically connected to the second input / output pad 405 through the third substrate 410. In this case, the connection structure of the second input / output contact plug 403 and the second input / output pad 405 may be implemented in various ways.

[0146] For example, as shown in region C1 as an alternative embodiment of region “C”, an opening 408 may be formed through the third substrate 410, and the second input / output contact plug 403 may be directly connected to the second input / output pad 405 through the opening 408 formed in the third substrate 410. In this case, as shown in C1, the second input / output contact plug 403 may have a diameter that increases toward the second input / output pad 405. However, this is exemplary, and the second input / output contact plug 403 may have a diameter that decreases toward the second input / output pad 405.

[0147] For example, as shown in region C2 as an alternative embodiment of region “C”, an opening 408 may be formed through the third substrate 410, and a contact 407 may be formed in the opening 408. One end of the contact 407 may be connected to the second input / output pad 405, and the opposite end of the contact 407 may be connected to the second input / output contact plug 403. Therefore, the second input / output contact plug 403 may be electrically connected to the second input / output pad 405 through the contact 407 in the opening 408. In this case, as shown in C2, the contact 407 may have a diameter that increases toward the second input / output pad 405, and the second input / output contact plug 403 may have a diameter that decreases toward the second input / output pad 405. For example, the third input / output contact plug 403 may be formed together with the cell contact plug 440 before the second cell region CELL2 and the first cell region CELL1 are combined by a bonding method, and the contact 407 may be formed after the second cell region CELL2 and the first cell region CELL1 are combined by a bonding method.

[0148] For example, as shown in region C3 as an alternative embodiment of region “C”, a stopper (or barrier) 409 may be additionally formed on the upper surface of the opening 408 of the third substrate 410. The stopper 409 may be a metal line formed on the same layer as the common source line 420. However, this is exemplary, and the stopper 409 may be a metal line formed on the same layer as at least one of the word lines 430. The second input / output contact plug 403 may be electrically connected to the second input / output pad 405 through the contact 407 and the stopper 409.

[0149] Meanwhile, similar to the second input / output contact plug 403 and the third input / output contact plug 404 of the second cell region CELL2, the second input / output contact plug 303 and the third input / output contact plug 304 of the first cell region CELL1 may have a diameter that decreases toward the lower metal pattern 371e, or may have a diameter that increases toward the lower metal pattern 371e.

[0150] Meanwhile, in some embodiments, a slit 411 may be formed in the third substrate 410. For example, the slit 411 may be formed at any position in the external pad bonding area PA. For example, as shown in D, when viewed on a plane, the slit 411 may be located between the second input / output pad 405 and the cell contact plug 440. However, this is schematic, and the slit 411 may be formed so that when viewed on a plane, the second input / output pad 405 is located between the slit 411 and the cell contact plug 440.

[0151] For example, as shown in region D1 as an alternative embodiment of region "D", slits 411 may be formed through the third substrate 410. For example, when the opening 408 is formed, the slits 411 may be used to prevent the third substrate 410 from being finely broken. However, this is exemplary, and the slits 411 may be formed to have a depth in the range of about 60% to about 70% of the thickness of the third substrate 410.

[0152] For example, as shown in region D2 as an alternative embodiment of region "D", a conductive material 412 may be formed in the slit 411. For example, the conductive material 412 may be used to discharge leakage current generated when the circuit element in the external pad bonding region PA is driven. In this case, the conductive material 412 may be connected to an external ground line.

[0153] For example, as shown in region D3 as an alternative embodiment of region "D", an insulating material 413 may be formed in the slit 411. For example, the insulating material 413 may be formed to electrically isolate the second input / output pad 405 and the second input / output contact plug 403 disposed in the external pad bonding area PA from the word line bonding area WLBA. By forming the insulating material 413 in the slit 411, the influence of the voltage provided through the second input / output pad 405 on the metal layer on the third substrate 410 disposed in the word line bonding area WLBA may be interrupted.

[0154] Meanwhile, in some embodiments, the first to third input / output pads 205, 405, and 406 may be selectively formed. For example, the memory device 500 may be implemented to include only the first input / output pad 205 disposed on the first substrate 210, only the second input / output pad 405 disposed on the third substrate 410, or only the third input / output pad 406 disposed on the upper insulating layer 401.

[0155] Meanwhile, in some embodiments, at least one of the second substrate 310 of the first cell region CELL1 and the third substrate 410 of the second cell region CELL2 may be used as a sacrificial substrate and may be completely or partially removed before or after the bonding process. An additional layer may be stacked after the substrate is removed. For example, the second substrate 310 of the first cell region CELL1 may be removed before or after the peripheral circuit region PERI and the first cell region CELL1 are bonded to each other, and an insulating layer for covering the upper surface of the common source line 320 or a conductive layer for connection may be formed. Similarly, the third substrate 410 of the second cell region CELL2 may be removed before or after the first cell region CELL1 and the second cell region CELL2 are bonded to each other, and an upper insulating layer 401 for covering the upper surface of the common source line 420 or a conductive layer for connection may be formed.

[0156] In one embodiment, the voltage generating circuit 170, 170-1 or 170-2 according to the embodiment of the present disclosure may be formed in a peripheral circuit area, and various operating voltages generated by the voltage generating circuit 170, 170-1 or 170-2 may be provided to word lines, bit lines, string selection lines, ground selection lines, common source lines, substrates, etc.

[0157] Fig.18 1 is a block diagram of a memory system 1000 according to an embodiment. Fig.18 , the memory system 1000 may include a memory device 1100 and a memory controller 1200 .

[0158] The memory device 1100 may include first to eighth pins P11 to P18 , a memory interface circuitry 1110 , a control logic circuitry 1120 , and a memory cell array 1130 .

[0159] The memory interface circuit system 1110 may receive a chip enable signal nCE from the memory controller 1200 through the first pin P11. The memory interface circuit system 1110 may send and receive signals to and from the memory controller 1200 through the second pin P12 to the eighth pin P18 in response to the chip enable signal nCE. For example, when the chip enable signal nCE is in an enabled state (e.g., a low level), the memory interface circuit system 1110 may send and receive signals to and from the memory controller 1200 through the second pin P12 to the eighth pin P18.

[0160] The memory interface circuit system 1110 may receive a command latch enable signal CLE, an address latch enable signal ALE, and a write enable signal nWE from the memory controller 1200 through the second pin P12 to the fourth pin P14. The memory interface circuit system 1110 may receive a data signal DQ from the memory controller 1200 or send the data signal DQ to the memory controller 1200 through the seventh pin P17. The command CMD, the address ADDR, and the data may be sent via the data signal DQ. For example, the data signal DQ may be sent through a plurality of data signal lines. In this case, the seventh pin P17 may include a plurality of pins corresponding to the plurality of data signals DQ, respectively.

[0161] The memory interface circuit system 1110 may obtain a command CMD from a data signal DQ received in an enable section (e.g., a high level state) of a command latch enable signal CLE based on a switching time point of a write enable signal nWE. The memory interface circuit system 1110 may obtain an address ADDR from a data signal DQ received in an enable section (e.g., a high level state) of an address latch enable signal ALE based on a switching time point of a write enable signal nWE.

[0162] In an example embodiment, the write enable signal nWE may be maintained at a static state (e.g., a high level or a low level) and switched between a high level and a low level. For example, the write enable signal nWE may be switched in a section where a command CMD or an address ADDR is sent. Therefore, the memory interface circuit system 1110 may obtain the command CMD or the address ADDR based on the switching time point of the write enable signal nWE.

[0163] The memory interface circuitry 1110 may receive a read enable signal nRE from the memory controller 1200 through a fifth pin P15. The memory interface circuitry 1110 may receive a data strobe signal DQS from the memory controller 1200 or transmit the data strobe signal DQS to the memory controller 1200 through a sixth pin P16.

[0164] In the data (DATA) output operation of the memory device 1100, the memory interface circuit system 1110 may receive a switched read enable signal nRE through the fifth pin P15 before outputting the data DATA. The memory interface circuit system 1110 may generate a data strobe signal DQS that switches based on the switching of the read enable signal nRE. For example, the memory interface circuit system 1110 may generate a data strobe signal DQS based on the switching start time of the read enable signal nRE, and the data strobe signal DQS starts switching after a predetermined delay (e.g., tDQSRE). The memory interface circuit system 1110 may send a data signal DQ including data DATA based on the switching time point of the data strobe signal DQS. Therefore, the data DATA may be aligned with the switching time point of the data strobe signal DQS and sent to the memory controller 1200.

[0165] In the data (DATA) input operation of the memory device 1100, when a data signal DQ including data DATA is received from the memory controller 1200, the memory interface circuit system 1110 may receive a switched data strobe signal DQS together with the data DATA from the memory controller 1200. The memory interface circuit system 1110 may obtain the data DATA from the data signal DQ based on the switching time point of the data strobe signal DQS. For example, the memory interface circuit system 1110 may sample the data signal DQ at the rising edge and the falling edge of the data strobe signal DQS and obtain the data DATA.

[0166] The memory interface circuit system 1110 may transmit the ready / busy output signal nR / B to the memory controller 1200 through the eighth pin P18. The memory interface circuit system 1110 may transmit the state information of the memory device 1100 to the memory controller 1200 through the ready / busy output signal nR / B. When the memory device 1100 is in a busy state (i.e., when an operation is being performed in the memory device 1100), the memory interface circuit system 1110 transmits the ready / busy output signal nR / B indicating the busy state to the memory controller 1200. When the memory device 1100 is in a ready state (i.e., when no operation is being performed or the operation is completed in the memory device 1100), the memory interface circuit system 1110 may transmit the ready / busy output signal nR / B indicating the ready state to the memory controller 1200. For example, when the memory device 1100 is reading data DATA from the memory cell array 1130 in response to a page read command, the memory interface circuit system 1110 may transmit a ready / busy output signal nR / B indicating a busy state (e.g., a low level) to the memory controller 1200. For example, when the memory device 1100 is programming data DATA to the memory cell array 1130 in response to a program command, the memory interface circuit system 1110 may transmit a ready / busy output signal nR / B indicating a busy state to the memory controller 1200.

[0167] The control logic circuit system 1120 may control all operations of the memory device 1100. The control logic circuit system 1120 may receive the command / address CMD / ADDR obtained from the memory interface circuit system 1110. The control logic circuit system 1120 may generate control signals for controlling other components of the memory device 1100 in response to the received command / address CMD / ADDR. For example, the control logic circuit system 1120 may generate various control signals for programming data DATA into the memory cell array 1130 or reading data DATA from the memory cell array 1130.

[0168] The memory cell array 1130 may store data obtained from the memory interface circuit system 1110 via the control of the control logic circuit system 1120. The memory cell array 1130 may output the stored data DATA to the memory interface circuit system 1110 via the control of the control logic circuit system 1120.

[0169] The memory cell array 1130 may include a plurality of memory cells. For example, the plurality of memory cells may be flash memory cells. However, the inventive concept is not limited thereto, and the memory cell may be an RRAM cell, a FRAM cell, a PRAM cell, a thyristor RAM (TRAM) cell, or an MRAM cell. Hereinafter, an embodiment in which the memory cell is a NAND flash memory cell will be mainly described.

[0170] The memory controller 1200 may include first to eighth pins P21 to P28 and a controller interface circuit system 1210. The first to eighth pins P21 to P28 may correspond to first to eighth pins P11 to P18 of the memory device 1100, respectively.

[0171] The controller interface circuit system 1210 may send a chip enable signal nCE to the memory device 1100 through the first pin P21. The controller interface circuit system 1210 may send and receive signals to and from the memory device 1100 through the second to eighth pins P22 to P28, the memory device 1100 being selected by the chip enable signal nCE.

[0172] The controller interface circuit system 1210 may transmit the command latch enable signal CLE, the address latch enable signal ALE, and the write enable signal nWE to the memory device 1100 through the second pin P22 to the fourth pin P24. The controller interface circuit system 1210 may transmit or receive the data signal DQ to or from the memory device 1100 through the seventh pin P27.

[0173] The controller interface circuit system 1210 may transmit the data signal DQ including the command CMD or the address ADDR together with the switched write enable signal nWE to the memory device 1100. The controller interface circuit system 1210 may transmit the data signal DQ including the command CMD to the memory device 1100 by transmitting the command latch enable signal CLE having an enable state. In addition, the controller interface circuit system 1210 may transmit the data signal DQ including the address ADDR to the memory device 1100 by transmitting the address latch enable signal ALE having an enable state.

[0174] The controller interface circuitry 1210 may transmit the read enable signal nRE to the memory device 1100 through the fifth pin P25. The controller interface circuitry 1210 may receive or transmit the data strobe signal DQS from the memory device 1100 through the sixth pin P26.

[0175] In the data (DATA) output operation of the memory device 1100, the controller interface circuit system 1210 may generate a switched read enable signal nRE and send the read enable signal nRE to the memory device 1100. For example, before outputting the data DATA, the controller interface circuit system 1210 may generate a read enable signal nRE that changes from a static state (e.g., a high level or a low level) to a switched state. Therefore, the memory device 1100 may generate a switched data strobe signal DQS based on the read enable signal nRE. The controller interface circuit system 1210 may receive a data signal DQ including data DATA from the memory device 1100 together with the switched data strobe signal DQS. The controller interface circuit system 1210 may obtain data DATA from the data signal DQ based on the switching time point of the data strobe signal DQS.

[0176] In the data (DATA) input operation of the memory device 1100, the controller interface circuit system 1210 may generate a switched data strobe signal DQS. For example, before sending the data DATA, the controller interface circuit system 1210 may generate a data strobe signal DQS that changes from a static state (e.g., a high level or a low level) to a switched state. The controller interface circuit system 1210 may send a data signal DQ including data DATA to the memory device 1100 based on a switching time point of the data strobe signal DQS.

[0177] The controller interface circuit system 1210 may receive the ready / busy output signal nR / B from the memory device 1100 through the eighth pin P28. The controller interface circuit system 1210 may determine the status information of the memory device 1100 based on the ready / busy output signal nR / B.

[0178] In one embodiment, the voltage generating circuit according to the embodiment of the present disclosure may be included in Fig.18 in a memory device and can be based on a reference Figures 1 to 16 The described method generates various operating voltages. The memory device 1100 may operate based on various operating voltages generated by the voltage generating circuit according to an embodiment of the present disclosure.

[0179] Fig.19 is a diagram of a system 2000 to which a storage device is applied according to an embodiment. Fig.19 The system 2000 may basically be a mobile system such as a portable communication terminal (e.g., a mobile phone), a smart phone, a tablet personal computer (PC), a wearable device, a healthcare device, or an Internet of Things (IOT) device). However, Fig.19 The system 2000 is not necessarily limited to a mobile system and may be a PC, a laptop computer, a server, a media player, or an automotive device (eg, a navigation device).

[0180] Reference Fig.19 , the system 2000 may include a main processor 2100, a memory (e.g., 2200a and 2200b), and a storage device (e.g., 2300a and 2300b). In addition, the system 2000 may include at least one of an image capture device 2410, a user input device 2420, a sensor 2430, a communication device 2440, a display 2450, a speaker 2460, a power supply device 2470, and a connection interface 2480.

[0181] The main processor 2100 may control all operations of the system 2000, and more specifically, operations of other components in the system 2000. The main processor 2100 may be implemented as a general-purpose processor, a dedicated processor, or an application processor.

[0182] The main processor 2100 may include at least one CPU core 2110, and also include a controller 2120 configured to control memories 2200a and 2200b and / or storage devices 2300a and 2300b. In some embodiments, the main processor 2100 may also include an accelerator 2130, which is a dedicated circuit for high-speed data operations (such as artificial intelligence (AI) data operations). The accelerator 2130 may include a graphics processing unit (GPU), a neural processing unit (NPU) and / or a data processing unit (DPU), and may be implemented as a chip physically separated from other components of the main processor 2100.

[0183] The memories 2200a and 2200b may be used as main memory devices of the system 2000. Although each of the memories 2200a and 2200b may include a volatile memory such as a static random access memory (SRAM) and / or a dynamic RAM (DRAM), each of the memories 2200a and 2200b may include a nonvolatile memory such as a flash memory, a phase change RAM (PRAM), and / or a resistive RAM (RRAM). The memories 2200a and 2200b may be implemented in the same package as the main processor 2100.

[0184] The storage devices 2300a and 2300b may be used as non-volatile storage devices configured to store data regardless of whether power is supplied thereto, and have a larger storage capacity than the memories 2200a and 2200b. The storage devices 2300a and 2300b may include storage controllers (STRG CTRL) 2310a and 2310b and NVM (non-volatile memory) 2320a and 2320b, respectively, and the NVM (non-volatile memory) 2320a and 2320b are configured to store data via the control of the storage controllers 2310a and 2310b. Although the NVM 2320a and 2320b may include a flash memory having a two-dimensional (2D) structure or a three-dimensional (3D) V-NAND structure, the NVM 2320a and 2320b may include other types of NVM (such as, PRAM and / or RRAM).

[0185] The storage devices 2300a and 2300b may be physically separated from the main processor 2100 and included in the system 2000 or implemented in the same package as the main processor 2100. In addition, the storage devices 2300a and 2300b may have various types of solid-state devices (SSDs) or memory cards, and may be removably combined with other components of the system 2000 through an interface (such as a connection interface 2480 to be described below). The storage devices 2300a and 2300b may be devices that apply a standard protocol (such as universal flash storage (UFS), embedded multimedia card (eMMC), or non-volatile memory express (NVMe)), but are not limited thereto.

[0186] The image capture device 2410 may capture a still image or a moving image. The image capture device 2410 may include a camera, a video camera, and / or a webcam.

[0187] The user input device 2420 may receive various types of data input by a user of the system 2000 and include a touch pad, a keypad, a keyboard, a mouse, and / or a microphone.

[0188] The sensor 2430 may detect various types of physical quantities that may be obtained from the outside of the system 2000 and convert the detected physical quantities into electrical signals. The sensor 2430 may include a temperature sensor, a pressure sensor, an illumination sensor, a position sensor, an acceleration sensor, a biosensor, and / or a gyro sensor.

[0189] The communication device 2440 may transmit and receive signals between other devices outside the system 2000 according to various communication protocols. The communication device 2440 may include an antenna, a transceiver, and / or a modem.

[0190] Display 2450 and speaker 2460 may be used as output devices configured to output visual information and auditory information, respectively, to a user of system 2000.

[0191] The power supply device 2470 may appropriately convert power supplied from a battery (not shown) embedded in the system 2000 and / or an external power source, and supply the converted power to each of the components of the system 2000 .

[0192] The connection interface 2480 may provide a connection between the system 2000 and an external device that is connected to the system 2000 and is capable of transmitting and receiving data to and from the system 2000. The connection interface 2480 may be implemented by using various interface schemes such as Advanced Technology Attachment (ATA), Serial ATA (SATA), External SATA (e-SATA), Small Computer Small Interface (SCSI), Serial Attached SCSI (SAS), Peripheral Component Interconnect (PCI), PCI Express (PCIe), NVMe, IEEE 1394, Universal Serial Bus (USB) interface, Secure Digital (SD) card interface, Multimedia Card (MMC) interface, eMMC interface, UFS interface, embedded UFS (eUFS) interface, and Compact Flash (CF) card interface.

[0193] In one embodiment, the voltage generating circuit according to the embodiment of the present disclosure may be included in Fig.19 The various components of the system 2000 and may be based on reference Figures 1 to 16 The described method generates various operating voltages.

[0194] According to the present disclosure, a voltage generating circuit can generate various operating voltages by using a common pump block. That is, when generating various operating voltages, because the common pump block is commonly used or shared, the entire area of ​​the voltage generating circuit can be reduced. Therefore, a memory device including a voltage generating circuit with reduced cost and improved performance and an operating method of the memory device are provided.

[0195] While the present disclosure has been described with reference to the embodiments thereof, it will be apparent to those skilled in the art that various changes and modifications can be made thereto without departing from the spirit and scope of the present disclosure as set forth in the appended claims.

Claims

1. A memory device, comprising: a memory cell array comprising a plurality of memory cells; as well as The peripheral circuit is configured to perform a plurality of operations on the memory cell array by using a plurality of operation voltages, The peripheral circuit includes: a voltage generating circuit including a first pump block, a second pump block and a first common pump block, and configured to generate the plurality of operating voltages, and Wherein, the voltage generating circuit is configured as follows: connecting the first pump block and the first common pump block in parallel to generate a first operating voltage among the plurality of operating voltages; and The first common pump block and the second pump block are connected in series to generate a second operating voltage among the plurality of operating voltages.

2. The memory device according to claim 1, wherein: A level of the first operating voltage is lower than a level of the second operating voltage.

3. The memory device according to claim 1, wherein: The load corresponding to the first operating voltage is greater than the load corresponding to the second operating voltage.

4. The memory device according to claim 1, wherein: The first pump block includes a plurality of first unit pumps, wherein the plurality of first unit pumps are connected to have a first series connection size and a first parallel connection size, Wherein, the second pump block includes a plurality of second unit pumps, and The plurality of second unit pumps are connected to have a second series size and a second parallel size.

5. The memory device according to claim 4, wherein: The first common pump block includes a plurality of first common unit pumps, and Wherein, the plurality of first common unit pumps are connected to have a first series size and a second parallel size.

6. The memory device according to claim 5, wherein: The voltage generating circuit further includes a third pump block and a second common pump block, The voltage generating circuit is further configured to: connect the first common pump block, the second common pump block and the first pump block in parallel to generate a first operating voltage, and The voltage generating circuit is further configured to generate a third operating voltage by connecting the first common pump block and the second pump block in series, connecting the second common pump block and the third pump block in series, and connecting the output of the second pump block and the output of the third pump block in parallel.

7. The memory device according to claim 6, wherein: The third pump block includes a plurality of third unit pumps, The plurality of third unit pumps are connected to have a third series connection size and a third parallel connection size. Wherein, the second common pump block includes a plurality of second common unit pumps, and Wherein, the plurality of second common unit pumps are connected to have a first series connection size and a third parallel connection size.

8. The memory device according to claim 6, wherein: The first operation voltage is a read voltage used in a read operation on the memory cell array. The second operating voltage is a programming voltage used in a programming operation on the memory cell array, and The third operating voltage is an erasing voltage used in an erasing operation on the memory cell array.

9. The memory device according to any one of claims 1 to 8, wherein: The peripheral circuit further includes: a control logic circuit configured to generate a switching signal, and The voltage generating circuit further includes: a switch block configured to connect the first common pump block and the first pump block in parallel or connect the first common pump block and the second pump block in series in response to a switching signal.

10. The memory device according to claim 9, wherein: The peripheral circuit further includes: a buffer circuit configured to receive a command, an address, and data from an external device through the first signal line, The control logic circuit is further configured to: receive the command from the buffer circuit, and control the switching signal based on the command.

11. A memory device comprising: a memory cell array comprising a plurality of memory cells; a control logic circuit configured to generate a switching signal in response to a command received from an external device; as well as A voltage generating circuit includes a first pump block, a second pump block and a first common pump block, Wherein, in response to the switching signal, the voltage generating circuit is configured to generate a first operating voltage by using the first pump block and the first common pump block, and to generate a second operating voltage by using the second pump block and the first common pump block.

12. The memory device according to claim 11, wherein: The first operation voltage is a read voltage used in a read operation on a memory cell array, and The second operating voltage is a programming voltage used in a programming operation on the memory cell array.

13. The memory device according to claim 11, wherein: The level of the first operating voltage is lower than the level of the second operating voltage, and The load corresponding to the first operating voltage is greater than the load corresponding to the second operating voltage.

14. The memory device according to claim 13, wherein: The voltage generation circuit is configured as: connecting the first pump block and the first common pump block in parallel to generate a first operating voltage; and The first common pump block and the second pump block are connected in series to generate a second operating voltage.

15. The memory device according to any one of claims 11 to 14, wherein: The voltage generating circuit further includes a second common pump block, wherein the voltage generating circuit generates a first operating voltage by connecting the first pump block, the first common pump block, and the second common pump block in parallel, and The voltage generating circuit generates a third operating voltage by connecting the first common pump block and the second pump block in series, connecting the second common pump block and the third pump block in series, and connecting the output of the second pump block and the output of the third pump block in parallel.

16. The memory device of claim 15, wherein: The third operating voltage is an erase voltage used in an erase operation of the memory cell array.

17. A method for operating a memory device, the method comprising: receiving an operation command from an external device; When the operation command is a read command, performing a read operation based on the read voltage; as well as When the operation command is a program command, a program operation is performed based on a program voltage. Wherein, the memory device is configured as: connecting the first pump block, the first common pump block, and the second common pump block in parallel to generate a read voltage; and The first common pump block and the second pump block are connected in series to generate a programming voltage.

18. The operating method according to claim 17, further comprising: When the operation command is an erase command, an erase operation is performed based on an erase voltage. The memory device is configured to generate an erase voltage by connecting a first common pump block and a second pump block in series, connecting a second common pump block and a third pump block in series, and connecting an output of the second pump block and an output of the third pump block in parallel.

19. The operating method according to claim 18, wherein: The series dimensions of the first pump block, the first common pump block, and the second common pump block are the same.

20. The operating method according to claim 18, wherein: The second pump block has the same parallel dimensions as the first common pump block, and The parallel dimensions of the third pump block and the second common pump block are the same.

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