Multi-wafer stacking edge processing method
By using inclined cutting and oxide layer formation methods during multi-wafer stacking to process the wafer edges, the problems of chip effective area reduction, particle aggregation, edge patterning and breakdown risks in wafers in the prior art are solved, and a larger effective area and better process performance are achieved.
Patent Information
- Application Number
- CN202311143883.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-09-06
- Publication Date
- 2025-03-07
AI Technical Summary
During multi-wafer stacking, the prior art leads to a decrease in the effective area of the chip in the wafer, particle aggregation, edge patterning problems and increased risk of breakdown.
The wafer edges are treated with inclined cutting and oxide layer formation, forming steps and forming an oxide layer thereon, ensuring that the top of the oxide layer is flush with the top of the wafer.
Reduce the cutting width by tilting cutting, increase the effective area of the chip in the wafer, reduce particle aggregation, improve edge patterning problems and reduce breakdown risk.
Smart Images
Figure CN119581314A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor technology, and in particular to a multi-wafer stacking edge processing method. Background Art
[0002] When multiple wafers are stacked, the edges of the wafers need to be trimmed before and after each bonding. Each subsequent wafer added on the top needs to have complete support on the bottom during the grinding process to avoid splitting during the thinning process.
[0003] Figure 1A to Figure 1F Schematic diagram of the cross section of the corresponding steps in the prior art multi-wafer stacking edge processing method. Figure 1A , along the first surface of the second wafer 12, the edge of the first surface of the second wafer 12 is vertically cut, so that the width of the vertically cut edge of the first surface of the second wafer 12 is d1. Please refer to Figure 1B , the first surface of the second wafer 12 is bonded to the first wafer 11. Please refer to Figure 1C , first thin the second wafer 12 along the second surface of the second wafer 12, then vertically cut the edges of the second wafer 12 and the first wafer 11, and vertically cut into the first wafer 11, and the width of the vertically cut edges of the second wafer 12 and the first wafer 11 is d2, and d2 is greater than d1. Please refer to Figure 1D , along the first surface of the third wafer 13, the edge of the first surface of the third wafer 13 is vertically cut, so that the width of the first surface edge of the third wafer 13 that is vertically cut is d3, and d3 is greater than d2. Please refer to Figure 1E , first bond the first surface of the third wafer 13 to the second wafer 12. Please refer to Figure 1F First, the third wafer 13 is thinned along the second surface of the third wafer 13, and then the edges of the third wafer 13, the second wafer 12 and the first wafer 11 are vertically cut, and the edges of the third wafer 13, the second wafer 12 and the first wafer 11 are vertically cut into the first wafer 11. The width of the edges of the third wafer 13, the second wafer 12 and the first wafer 11 that are vertically cut is d4, and d4 is greater than d3. Figure 1A to Figure 1F A bonding layer is formed between two adjacent wafers (the dark filled part in the figure is not marked). Similarly, as the number of wafer stacks increases, the width of the vertical cut will also increase, which will reduce the effective area of the chip in the wafer and limit the number of wafer stacks; and when cutting along the first side of the wafer, particles (particles generated when cutting the wafer) are easily aggregated at the cutting point; and the edge of the wafer has a step morphology, which is easy to produce patterns at the edge of the wafer in the subsequent photolithography process, and it is easy to produce a breakdown risk at the edge of the wafer during the etching process. Summary of the invention
[0004] The object of the present invention is to provide a multi-wafer stack edge processing method to increase the effective area of chips in the wafer, reduce particle aggregation, improve the graphics problem of the wafer edge and reduce the breakdown risk of the wafer edge.
[0005] In order to achieve the above object, the present invention provides a multi-wafer stack edge processing method, comprising:
[0006] Providing the first to Nth wafers to be bonded sequentially, where N is an integer greater than or equal to 3;
[0007] Cutting and bonding the second wafer and the first wafer to form steps at the edges of the second wafer and the first wafer, and forming a first oxide layer on the steps with the top of the first oxide layer flush with the top of the second wafer;
[0008] Performing an inclined cutting on the edge of the first surface of the i-th wafer so that the edge of the first surface of the i-th wafer is inclined, where i is greater than 2 and less than or equal to N;
[0009] Bonding the first surface of the i-th wafer to the i-1-th wafer;
[0010] Performing an inclined cutting on the edge of the bonded i-th wafer, so that the edge of the bonded i-th wafer is inclined, and the width of the inclined cutting of the edge of the bonded i-th wafer is less than or equal to the width of the step; and,
[0011] An i-1th oxide layer is formed at the edge of the i-th wafer after bonding, the i-1th oxide layer is located on the first oxide layer, and the top of the i-1th oxide layer is flush with the top of the i-th wafer after bonding.
[0012] Optionally, the step of cutting and bonding the second wafer and the first wafer includes:
[0013] Performing an inclined cutting on the edge of the first surface of the second wafer so that the edge of the first surface of the second wafer is inclined;
[0014] Bonding the first surface of the second wafer to the first wafer;
[0015] The edges of the bonded second wafer and the first wafer are vertically cut, and the cutting is vertically cut into the first wafer to form the step at the edges of the second wafer and the first wafer, and the width of the step is greater than the width of the inclined cutting of the first surface edge of the second wafer.
[0016] Optionally, the inclined surface of the edge of the first surface of the second wafer, the inclined surface of the edge of the first surface of the i-th wafer, and the inclined surface of the edge of the i-th wafer after bonding are all arc surfaces.
[0017] Optionally, the width of the first surface edge of the second wafer cut obliquely is the same as the width of the first surface edge of the i-th wafer cut obliquely.
[0018] Optionally, the width of the inclined cutting of the edge of the first surface of the second wafer is 1 mm to 2 mm.
[0019] Optionally, the width of the step is 1 mm to 3 mm.
[0020] Optionally, the step of forming the first oxide layer includes:
[0021] Forming the first oxide layer on the step by using a CVD process, wherein the first oxide layer extends to cover the top of the second wafer;
[0022] The first oxide layer on the top of the second wafer is ground and removed by a grinding process, so that the top of the first oxide layer is flush with the top of the second wafer.
[0023] Optionally, when the edge of the i-th wafer after bonding is cut obliquely, it also includes synchronously cutting the i-2nd oxide layer of the edge of the i-1th wafer obliquely.
[0024] Optionally, when the i-1th oxide layer is formed on the edge of the i-th wafer after bonding, the step further includes forming the i-1th oxide layer on the edge of the i-1th wafer, and the step of forming the i-1th oxide layer includes:
[0025] Using a CVD process to form the i-1th oxide layer on the edges of the i-th wafer and the i-1th wafer after bonding, the i-1th oxide layer is located on the first oxide layer, and the i-1th oxide layer extends to cover the top of the i-th wafer after bonding;
[0026] The i-1th oxide layer on the top of the i-th wafer is ground and removed by a grinding process, so that the top of the i-1th oxide layer is flush with the top of the i-th wafer.
[0027] Optionally, an inclined cut is performed along the side of the wafer in a direction from bottom to top.
[0028] The multi-wafer stacking edge processing method provided by the present invention includes: providing the first to Nth wafers to be bonded in sequence, N being an integer greater than or equal to 3; cutting and bonding the second wafer and the first wafer to form a step at the edge of the second wafer and the first wafer, and forming a first oxide layer on the step, and the top of the first oxide layer is flush with the top of the second wafer; obliquely cutting the edge of the first surface of the i-th wafer so that the edge of the first surface of the i-th wafer is inclined, i is greater than 2 and less than or equal to N; bonding the first surface of the ith wafer to the i-1th wafer; bevel cutting the edge of the i-th wafer after bonding, so that the edge of the i-th wafer after bonding is inclined, and the width of the bevel cutting of the edge of the i-th wafer after bonding is less than or equal to the width of the step; and forming an i-1th oxide layer on the edge of the i-th wafer after bonding, the i-1th oxide layer is located on the first oxide layer, and the top of the i-1th oxide layer is flush with the top of the i-th wafer after bonding. The present invention can reduce the cutting width through inclined cutting, so that the width of the inclined cutting after each bonding is less than or equal to the width of the step, and the cutting width will not gradually increase with the stacking of multiple wafers, so that the effective area of the chip in the wafer can be increased; and the particles generated by the inclined cutting are easy to wash, which reduces particle aggregation and avoids affecting the first side of the wafer and subsequent processes; and an oxide layer (such as the first oxide layer and the i-1th oxide layer) is formed at the edge of the wafer. In the subsequent photolithography process, the oxide layer protects the edge of the wafer, improves the patterning problem of the wafer edge and reduces the risk of breakdown at the wafer edge. BRIEF DESCRIPTION OF THE DRAWINGS
[0029] Figure 1A to Figure 1F It is a cross-sectional schematic diagram of corresponding steps in the edge processing method of multi-wafer stacking in the prior art;
[0030] Figure 2 A flow chart of a multi-wafer stack edge processing method provided by an embodiment of the present invention;
[0031] Figure 3A to Figure 3I A cross-sectional schematic diagram of corresponding steps in a multi-wafer stack edge processing method provided by an embodiment of the present invention.
[0032] Wherein, the accompanying drawings are marked as follows:
[0033] 11, 110 - the first wafer; 12, 120 - the second wafer; 13, 130 - the third wafer; 310 - the first oxide layer; 320 - the second oxide layer. DETAILED DESCRIPTION
[0034] In order to make the purpose, advantages and features of the present invention clearer, the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. In addition, the structure shown in the drawings is often a part of the actual structure. In particular, the emphasis of each drawing is different, and sometimes different scales are used.
[0035] As used in the present invention, the singular forms "one", "an", and "the" include plural objects, the term "or" is usually used to include the meaning of "and / or", the term "several" is usually used to include the meaning of "at least one", and the term "at least two" is usually used to include the meaning of "two or more". In addition, the terms "first", "second", and "third" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first", "second", and "third" may explicitly or implicitly include one or at least two of the features, and "one end" and "the other end" generally refer to two corresponding parts. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.
[0036] Figure 2 This is a flow chart of the multi-wafer stack edge processing method provided in this embodiment. Please refer to Figure 2 , this embodiment provides a multi-wafer stack edge processing method, including:
[0037] Step S1: providing the first to Nth wafers to be bonded in sequence, where N is an integer greater than or equal to 3;
[0038] Step S2: cutting and bonding the second wafer and the first wafer to form a step at the edges of the second wafer and the first wafer, and forming a first oxide layer on the step with the top of the first oxide layer flush with the top of the second wafer;
[0039] Step S3: performing an inclined cutting on the edge of the first surface of the i-th wafer so that the edge of the first surface of the i-th wafer is inclined, where i is greater than 2 and less than or equal to N;
[0040] Step S4: bonding the first surface of the i-th wafer to the i-1-th wafer;
[0041] Step S5: performing an inclined cutting on the edge of the i-th wafer after bonding, so that the edge of the i-th wafer after bonding is inclined, and the width of the inclined cutting of the edge of the i-th wafer after bonding is less than or equal to the width of the step;
[0042] Step S6: forming an i-1th oxide layer on the edge of the i-th wafer after bonding, the i-1th oxide layer is located on the first oxide layer, and the top of the i-1th oxide layer is flush with the top of the i-th wafer after bonding.
[0043] Figure 3A to Figure 3I The cross-sectional schematic diagram of the corresponding steps in the multi-wafer stack edge processing method provided in this embodiment is shown below in combination with Figure 3A to Figure 3I The multi-wafer stacking edge processing method provided in this embodiment is described in detail.
[0044] Execute step S1: provide the 1st to Nth wafers to be bonded in sequence, where N is an integer greater than or equal to 3, so as to realize stacking and bonding of N wafers, and the N wafers have the same size; for example, the wafer includes a device structure, and multiple wafers are stacked to realize the interconnection of the device structure; or, the wafer does not include a device structure, an oxide layer is formed on the surface of the wafer, and multiple wafers are stacked to form an SOI structure (such as a single-layer SOI structure, a double-layer SOI structure).
[0045] Executing step S2: the step of cutting and bonding the second wafer and the first wafer includes:
[0046] Please refer to Figure 3A , the first surface edge of the second wafer 120 is cut obliquely ( Figure 3A The upward surface in the middle is the first surface of the second wafer 120, only the edge of the first surface of the second wafer 120 is removed by tilting the cut, and the entire edge of the second wafer 120 is not removed by cutting), so that the edge of the first surface of the second wafer 120 is tilted, and the tilted surface of the edge of the first surface of the second wafer 120 is preferably a curved surface. In this embodiment, the width of the tilted cut of the edge of the first surface of the second wafer 120 is D1, and D1 is preferably 1mm to 2mm, but is not limited thereto. In this embodiment, along the side of the second wafer 120 from bottom to top (the direction from the second surface of the second wafer 120 to the first surface of the second wafer 120), Figure 3A The second wafer 120 is cut obliquely (the surface facing downward is the second surface of the second wafer 120). A bonding layer ( Figure 3A Medium dark part, not marked).
[0047] Please refer to Figure 3B ,Will Figure 3A The second wafer 120 in the embodiment is turned over, and the first surface ( Figure 3B The downwardly facing surface) is bonded to the first wafer 110 (the first surface of the first wafer 110, i.e., Figure 3B The first wafer 110 is bonded with its upward surface. Figure 3B The darker part is the bonding layer. Figure 3BThe dotted box shows the part that needs to be cut and removed later).
[0048] Please refer to Figure 3C , after bonding, along the second surface ( Figure 3C The second wafer 120 is thinned by cutting the second wafer 120 (the surface of the second wafer 120 facing upward). Then, the edges of the bonded second wafer 120 and the first wafer 110 are vertically cut, and the cutting is vertically cut into the first wafer 110 to form a step at the edge of the second wafer 120 and the first wafer 110, and the bottom of the step is located in the first wafer 110, and the width of the step is D2. In this embodiment, the width D2 of the step is greater than the width D1 of the oblique cutting of the first surface edge of the second wafer 120, and D2 is preferably 1mm to 3mm, but is not limited thereto; for example, the width D1 of the oblique cutting of the first surface edge of the second wafer 120 is 1mm, and the width D2 of the step is greater than 1mm and less than or equal to 3mm.
[0049] Please refer to Figure 3D After a step is formed at the edge of the bonded second wafer 120 and the first wafer 110, a first oxide layer 310 is formed on the step (on the edge of the second wafer 120 and the first wafer 110), and the top of the first oxide layer 310 is flush with the top of the second wafer 120. Specifically, the first oxide layer 310 is formed on the step by a CVD process, and the first oxide layer extends to cover the top of the second wafer 120 (not shown in the figure); then, the first oxide layer on the top of the second wafer 120 is ground and removed by a grinding process, so that the top of the first oxide layer 310 is flush with the top of the second wafer 120.
[0050] After completing the bonding and edge processing of the second wafer and the first wafer, it is necessary to continue to complete the bonding and edge processing of the remaining wafers. The bonding and edge processing steps of the remaining wafers (such as the third wafer, the fourth wafer, etc.) are the same, but different from the bonding and edge processing steps of the second wafer and the first wafer.
[0051] Execute step S3: perform an inclined cutting on the edge of the first surface of the i-th wafer, so that the edge of the first surface of the i-th wafer is inclined, i is greater than 2 and less than or equal to N, for example, i can be 3, 4, 5. In this embodiment, the inclined surface of the edge of the first surface of the i-th wafer is preferably a curved surface, and the width D1 of the inclined cutting of the edge of the first surface of the second wafer (see Figure 3A ) is the same as the width of the inclined cutting at the edge of the first surface of the i-th wafer.
[0052] Please refer to Figure 3E , the first edge of the third wafer 130 is cut obliquely, so that the first edge of the third wafer 130 is inclined ( Figure 3EThe upward surface is the first surface of the third wafer 130, only the edge of the first surface of the third wafer 130 is removed by an inclined cut, and the entire edge of the third wafer 120 is not removed by cutting), so that the edge of the first surface of the third wafer 130 is inclined, and the inclined surface of the edge of the first surface of the third wafer 130 is preferably a curved surface. In this embodiment, the width of the inclined cut of the edge of the first surface of the third wafer 130 is D3, and the width D3 of the inclined cut of the edge of the first surface of the third wafer 130 is the same as the width D1 of the inclined cut of the edge of the first surface of the second wafer, and D3 is preferably 1mm to 2mm, but is not limited thereto. In this embodiment, along the side of the third wafer 130 from bottom to top (the direction from the second surface of the third wafer 130 to the first surface of the third wafer 130, Figure 3E The downwardly facing surface in the middle is the second surface of the third wafer 130 ) and the third wafer 130 is cut obliquely.
[0053] Execute step S4: bond the first surface of the i-th wafer to the i-1-th wafer.
[0054] Please refer to Figure 3E , for example, on the first surface of the third wafer 130 ( Figure 3E A bonding layer ( Figure 3E The darker part is not marked). Please refer to Figure 3F , for example, on the second surface of the second wafer 120 ( Figure 3F A bonding layer ( Figure 3F Medium dark part, not marked).
[0055] Please refer to Figure 3G , the example will Figure 3E The third wafer 130 in the embodiment is turned over, and the first surface ( Figure 3G The downwardly facing surface) is bonded to the second wafer 120 (the second surface of the second wafer 120, i.e. Figure 3G The second wafer 120 is bonded with its upward surface. Figure 3G The darker part is the bonding layer).
[0056] Execute step S5: After bonding, thin the i-th wafer along the second surface of the i-th wafer. Then, the edge of the i-th wafer after bonding is cut obliquely, so that the edge of the i-th wafer after bonding is inclined, and the inclined surface of the edge of the i-th wafer after bonding is preferably a curved surface, and the width of the inclined cutting of the edge of the i-th wafer after bonding is less than or equal to the width D2 of the step. In this embodiment, when the edge of the i-th wafer after bonding is cut obliquely, it also includes synchronously cutting the i-2 oxide layer of the edge of the i-1 wafer obliquely.
[0057] Please refer to Figure 3G and Figure 3H , example, after bonding, along the second surface ( Figure 3F The third wafer 130 is thinned by cutting the third wafer 130 along the side of the bonded third wafer 130 from bottom to top (the direction from the second wafer 120 to the third wafer 130) to achieve the edge of the bonded third wafer 130 being cut obliquely (removing the edge of the third wafer 130), so that the edge of the third wafer 130 is inclined, and the inclined surface of the edge of the third wafer 130 is preferably a curved surface. In this embodiment, the width of the inclined cutting of the edge of the third wafer 130 is D4, and the width D4 of the inclined cutting of the edge of the third wafer 130 is less than or equal to the width D2 of the step. In the present embodiment, since the oblique cutting is performed from bottom to top, the i-2 oxide layer at the edge of part of the i-1 wafer will inevitably be cut. For example, when the edge of the third wafer 130 after bonding is obliquely cut, the first oxide layer 310 at the edge of the second wafer 120 will be cut, and the first oxide layer 310 also has an inclined surface (preferably a curved surface). Therefore, the first oxide layer 310 and the third wafer 130 are obliquely cut in sequence along the side surface of the first oxide layer 310 from bottom to top (the direction from the second wafer 120 to the third wafer 130).
[0058] Execute step S6: In order to improve the patterning problem of the edge of the wafer and reduce the breakdown phenomenon of the edge of the wafer, an i-1th oxide layer is formed at the edge of the i-th wafer after bonding, the i-1th oxide layer is located on the first oxide layer, and the top of the i-1th oxide layer is flush with the top of the i-th wafer after bonding, and the oxide layer (such as the first oxide layer and the i-1th oxide layer) will protect the edge of the wafer in the subsequent photolithography process, improve the patterning problem of the edge of the wafer and reduce the risk of breakdown at the edge of the wafer. In this embodiment, since the oxide layer (such as the first oxide layer or the i-1th oxide layer) at the edge of a portion of the i-1th wafer will be cut when performing the oblique cutting in step S5, when the i-1th oxide layer is formed at the edge of the i-1th wafer, it also includes forming the i-1th oxide layer at the edge of the i-1th wafer.
[0059] Please refer to Fig. 3I, the second oxide layer 320 is formed on the edge of the third wafer 130 and the edge 120 of the second wafer after bonding, the second oxide layer 320 is located on the first oxide layer 310 and the top of the second oxide layer 320 is flush with the top of the third wafer 130. Specifically, the second oxide layer 320 is formed on the edge of the third wafer 130 and the second wafer 120 by a CVD process, the second oxide layer 320 is located on the first oxide layer 310, and the second oxide layer extends to cover the top of the third wafer 130 (not shown in the figure); then, the second oxide layer on the top of the third wafer 130 is ground and removed by a grinding process, so that the top of the second oxide layer 320 is flush with the top of the third wafer 130.
[0060] Figure 3E to Figure 3I The process of bonding the third wafer 130 to the second wafer 120, performing an oblique cut on the edge of the bonded third wafer 130, and forming a second oxide layer 320 on the edge of the third wafer 130 is illustrated. In addition, the fourth wafer to the Nth wafer are stacked in the same steps, and each wafer undergoes the above steps of bonding, oblique cutting, and forming an oxide layer. When the edge of the fourth wafer, the fifth wafer, ... or the Nth wafer is obliquely cut, the second oxide layer, the third oxide layer, ... or the N-2 oxide layer of the edge of the third wafer, the fourth wafer, ... or the N-1th wafer will be cut (the first oxide layer will not be cut). By analogy, a multi-wafer stack is formed, and after the multi-wafer stack is formed, the top of the Nth wafer is flush with the top of the N-1 oxide layer of the edge of the Nth wafer, and the width of the oblique cutting of the edges of the third wafer to the Nth wafer after bonding is less than the width of the step.
[0061] In the present embodiment, all inclined cuts are performed along the side of the wafer from bottom to top. The particles generated by the inclined cutting are located on the side for easy washing, reducing particle aggregation and avoiding affecting the first side of the wafer and subsequent processes; the inclined cutting can reduce the cutting width, so that the width of the inclined cut after each bonding is less than or equal to the width of the step (the width of the edge inclined cuts from the 3rd wafer to the Nth wafer after bonding is less than the width of the step), and will not gradually increase with the cutting width of multiple wafers stacked, thereby increasing the effective area of the chip in the wafer; and, an oxide layer (such as the first oxide layer and the i-1th oxide layer) is formed at the edge of the wafer. In the subsequent photolithography process, the oxide layer protects the edge of the wafer, improves the patterning problem of the wafer edge and reduces the risk of breakdown at the wafer edge.
[0062] In summary, the multi-wafer stacking edge processing method provided by the present invention includes: providing the first to Nth wafers to be bonded in sequence, N being an integer greater than or equal to 3; cutting and bonding the second wafer and the first wafer to form a step at the edge of the second wafer and the first wafer, and forming a first oxide layer on the step, and the top of the first oxide layer is flush with the top of the second wafer; bevel cutting the edge of the first surface of the i-th wafer, so that the edge of the first surface of the i-th wafer is tilted, i is greater than 2 and is less than or equal to N; bonding the first surface of the ith wafer to the i-1th wafer; performing an inclined cut on the edge of the bonded ith wafer, so that the edge of the bonded ith wafer is inclined, and the width of the inclined cut of the edge of the bonded ith wafer is less than or equal to the width of the step; and forming an i-1th oxide layer on the edge of the bonded ith wafer, the i-1th oxide layer is located on the first oxide layer, and the top of the i-1th oxide layer is flush with the top of the bonded ith wafer. The present invention can reduce the cutting width through inclined cutting, so that the width of the inclined cutting after each bonding is less than or equal to the width of the step, and the cutting width will not gradually increase with the stacking of multiple wafers, so that the effective area of the chip in the wafer can be increased; and the particles generated by the inclined cutting are easy to wash, which reduces particle aggregation and avoids affecting the first side of the wafer and subsequent processes; and an oxide layer (such as the first oxide layer and the i-1th oxide layer) is formed at the edge of the wafer. In the subsequent photolithography process, the oxide layer protects the edge of the wafer, improves the patterning problem of the wafer edge and reduces the risk of breakdown at the wafer edge.
[0063] The above is only a preferred embodiment of the present invention and does not limit the present invention in any way. Any technician in the relevant technical field, without departing from the scope of the technical solution of the present invention, makes any form of equivalent replacement or modification to the technical solution and technical content disclosed in the present invention, which does not depart from the content of the technical solution of the present invention and still falls within the protection scope of the present invention.
Claims
1. A method for edge processing of a multi-wafer stack, characterized in that: include: Providing the first to Nth wafers to be bonded sequentially, where N is an integer greater than or equal to 3; Cutting and bonding the second wafer and the first wafer to form steps at the edges of the second wafer and the first wafer, and forming a first oxide layer on the steps with the top of the first oxide layer flush with the top of the second wafer; Performing an inclined cutting on the edge of the first surface of the i-th wafer so that the edge of the first surface of the i-th wafer is inclined, where i is greater than 2 and less than or equal to N; Bonding the first surface of the i-th wafer to the i-1-th wafer; Performing an inclined cutting on the edge of the bonded i-th wafer, so that the edge of the bonded i-th wafer is inclined, and the width of the inclined cutting of the edge of the bonded i-th wafer is less than or equal to the width of the step; and, An i-1th oxide layer is formed at the edge of the i-th wafer after bonding, the i-1th oxide layer is located on the first oxide layer, and the top of the i-1th oxide layer is flush with the top of the i-th wafer after bonding.
2. The multi-wafer stack edge processing method according to claim 1, characterized in that: The steps of cutting and bonding the second wafer and the first wafer include: Performing an inclined cutting on the edge of the first surface of the second wafer so that the edge of the first surface of the second wafer is inclined; Bonding the first surface of the second wafer to the first wafer; The edges of the bonded second wafer and the first wafer are vertically cut, and the cutting is vertically cut into the first wafer to form the step at the edges of the second wafer and the first wafer, and the width of the step is greater than the width of the inclined cutting of the first surface edge of the second wafer.
3. The multi-wafer stack edge processing method according to claim 2, characterized in that: The inclined surface of the edge of the first surface of the second wafer, the inclined surface of the edge of the first surface of the i-th wafer, and the inclined surface of the edge of the i-th wafer after bonding are all arc surfaces.
4. The multi-wafer stack edge processing method according to claim 2, characterized in that: The width of the first surface edge of the second wafer cut obliquely is the same as the width of the first surface edge of the i-th wafer cut obliquely.
5. The multi-wafer stack edge processing method according to claim 2, characterized in that: The width of the inclined cutting of the edge of the first surface of the second wafer is 1 mm to 2 mm.
6. The multi-wafer stack edge processing method according to claim 1 or 5, characterized in that: The width of the step is 1 mm to 3 mm.
7. The multi-wafer stack edge processing method according to claim 1, characterized in that: The step of forming the first oxide layer comprises: Forming the first oxide layer on the step by using a CVD process, wherein the first oxide layer extends to cover the top of the second wafer; The first oxide layer on the top of the second wafer is ground and removed by a grinding process, so that the top of the first oxide layer is flush with the top of the second wafer.
8. The multi-wafer stack edge processing method according to claim 1, characterized in that: When the edge of the i-th wafer after bonding is cut obliquely, it also includes synchronously cutting the i-2nd oxide layer of the edge of the i-1th wafer obliquely.
9. The multi-wafer stack edge processing method according to claim 8, characterized in that: When the i-1th oxide layer is formed on the edge of the i-th wafer after bonding, the step of forming the i-1th oxide layer on the edge of the i-th wafer includes: Using a CVD process to form the i-1th oxide layer on the edges of the i-th wafer and the i-1th wafer after bonding, the i-1th oxide layer is located on the first oxide layer, and the i-1th oxide layer extends to cover the top of the i-th wafer after bonding; The i-1th oxide layer on the top of the i-th wafer is ground and removed by a grinding process, so that the top of the i-1th oxide layer is flush with the top of the i-th wafer.
10. The multi-wafer stack edge processing method according to claim 1, characterized in that: The wafer is cut obliquely from bottom to top along the side surface.