Connection method of memory chip and substrate and packaging structure
By attaching the adapter board on the chip and connecting it to the substrate, the problems of complex wiring and opening the substrate are solved, and higher packaging reliability and lower cost are achieved.
Patent Information
- Application Number
- CN202411530347.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-30
- Publication Date
- 2025-03-07
AI Technical Summary
In the existing chip packaging technology, the wiring process is complicated, and the long wire length leads to an increase in resistance and inductance, affecting chip performance; at the same time, the thin substrate window opening and WLP copper layer lead to high reliability and packaging costs.
The adapter board is used to move the Pad position in the center of the chip out to the side of the chip, and connect the adapter board and the substrate through wire drawing, simplifying the process flow, shortening the length of the wire drawing, and avoiding the problem of substrate window opening and WLP copper layer thin.
It effectively reduces the risk of short circuit during packaging, improves wiring reliability, simplifies the process flow, and reduces packaging costs and product size.
Smart Images
Figure CN119581341A_ABST
Abstract
Description
Technical Field
[0001] The invention relates to a method for connecting a storage chip and a substrate and a packaging structure, belonging to the technical field of chip packaging. Background Art
[0002] Wire bonding (WB) is the most commonly used method for interconnecting circuits between chips and packaging substrates. Wire bonding requires the use of welding technology to weld metal pads (pad positions) on the chip to metal pads (pins) on the substrate through metal leads to achieve electrical connection. The pad position of a memory chip is usually located in the center of the chip. If the wire length is too long, it will cause an increase in resistance and inductance, which will cause the chip performance to deteriorate electrically. Therefore, the following two packaging methods are usually used: The first is the Window BGA package, where the pad at the bottom of the chip is connected to the pins on the substrate through wire bonding. The advantage of this type of package is that the wires can be directly bonded to the substrate to lead out the chip signal. However, the disadvantage of Window BGA package is that the substrate needs to have a window, which reduces reliability. At the same time, plastic sealing requires special molds, which increases the packaging cost. Conventional packaging factories do not have such packaging lines.
[0003] The second method is to move the pad position to the edge of the chip through WLP package RDL rewiring, and then connect it to the substrate through WB / fc packaging. The advantage of this type of packaging is that the pad position can be flexibly re-arranged and the packaging form can be converted; the disadvantage of WLP packaging is that the number of processes increases and the yield is reduced, and the copper layer of WLP packaging is thin, which cannot lead to large current signals.
[0004] As the design of packaged chips becomes more and more complex and the combination of multiple chips becomes more and more popular, the wire bonding process during packaging becomes more and more complicated. The wire bonding space is small and the density is high. The wire bonding (WB line) is prone to excessive offset during the plastic sealing process, resulting in short circuits with nearby wire bonding or chip edges, which seriously affects the reliability and safety of the package structure. At present, the processing of these risky wire bonding is done by experienced engineers constantly adjusting the angle of the chip, but this method sometimes cannot solve the problem of risky wire bonding well. In addition, the existing chip packaging technology requires a large spacing between adjacent chip groups to reserve space for wire bonding, resulting in an increase in the required substrate space, which leads to a large product package size. Summary of the invention
[0005] The method for connecting a memory chip and a substrate provided by the present invention shortens the length of a single bonding wire, avoids opening a window on the substrate and encapsulating a WLP copper layer on the chip surface, simplifies the process flow, increases the operating space and adjustment angle of a single bonding wire on the chip, effectively reduces the risk of short circuits between adjacent bonding wires and between bonding wires and chips during the packaging process, improves bonding reliability, and reduces the probability of risky bonding. The present invention also provides a packaging structure of a memory chip and a substrate.
[0006] In order to achieve the above object, the technical solution adopted by the present invention is: A method for connecting a memory chip to a substrate comprises a substrate and a chip mounted on the substrate, wherein the pad is located at the center of the chip, and is characterized in that the method comprises the following steps: First, a transfer plate is prepared according to the arrangement and number of the pad positions at the center of the chip, and a conductive position one corresponding to the pad position is set on the transfer plate; Next, mount the adapter plates on the chip along the sides of the chip, and align the conductive position on the adapter plate with the pad position; Afterwards, adjacent pad positions on the chip are connected to conductive positions on different adapter plates through wire bonding, so that the wire bonding directions of adjacent pad positions on the chip are opposite; Then, the adapter board is connected to the substrate to form a connection between the chip and the substrate.
[0007] Preferably, a second conductive position is provided on the adapter board, the second conductive position is electrically connected to the first conductive position correspondingly, and the second conductive position is connected to a pin on the substrate by wire bonding to form a connection between the adapter board and the substrate.
[0008] Preferably, the conductive position 2 and the conductive position 1 on the adapter board are combined to form a conductive area, the number of adapter blocks is two, the two adapter boards are distributed and mounted on both sides of the Pad position, and the conductive areas are distributed in parallel on the adapter boards.
[0009] Preferably, the adapter plate is an insulating plate formed by depositing a seed layer on the surface of a silicon oxide plate, a groove corresponding to the conductive area is provided on the upper surface of the adapter plate, and the conductive area is formed in the groove by an electroplating process.
[0010] Preferably, there are two methods for forming the conductive area on the adapter plate; The first method: first, a conductive metal layer is formed on the surface of the adapter board through an electroplating process according to the distribution position of the conductive area on the adapter board, and then an insulating layer is covered on the conductive metal layer. After that, the conductive metal layer at the location of the conductive area is exposed through an exposure or development process to form a groove and a conductive area in the groove.
[0011] The second method is to first etch a groove on the adapter board, and then electroplate a conductive metal layer in the groove to form a conductive area.
[0012] Preferably, the adapter plate is a metal plate wrapped by an insulating layer, the number of which is the same as the number of pad positions on the chip, the conductive position one is the metal surface exposed on the top surface of the adapter plate, and the lower end of the adapter plate is welded to the pin of the substrate.
[0013] Preferably, the adapter board is set to a right-angle shape, and the adapter board is overlapped and pasted on the chip so that the top surface of the adapter board is parallel to the chip. An upper chip is arranged above the adapter board, and the upper chip is supported on the adapter board by mounting, and the upper chip is connected to the adapter board by wire bonding.
[0014] Preferably, the adapter plates are evenly distributed on both sides of the chip to form a symmetrical support structure around the chip.
[0015] The packaging structure of a memory chip and a substrate using the above-mentioned method for connecting a memory chip and a substrate includes a substrate and a chip mounted on the substrate, wherein the Pad position is located at the center of the chip, and is characterized in that: an adapter board is mounted on the chip close to the side of the chip, a conductive position one corresponding to the Pad position is arranged on the adapter board, the conductive position one is connected to the Pad position by wire bonding, and the adapter board is connected to the substrate.
[0016] Preferably, it also includes an upper chip, which is supported on the adapter board by mounting and connected to the adapter board by wire bonding.
[0017] The beneficial effects of the invention are: The method for connecting a memory chip and a substrate of the present invention prepares an adapter board according to the arrangement and number of pad positions in the center of a chip, sets a conductive position one on the adapter board, and mounts the adapter board on the side of the chip, which is equivalent to using the adapter board and bonding wires to move the pad position outward to the side of the chip, bonding wires connect the chip and the adapter board, the adapter board connects the substrate, and uses the adapter board as an intermediate transition to avoid connecting the pad position to the substrate through long bonding wires, shorten the length of a single bonding wire, avoid opening windows on the substrate and encapsulating the WLP copper layer on the chip surface, and simplify the process flow.
[0018] The conductive positions on the adapter board are aligned with the Pad positions, and the adjacent Pad positions on the chip are connected to the conductive positions on different adapter boards through bonding, so that the bonding directions of adjacent Pad positions on the chip are opposite, increasing the operating space and adjustment angle of a single bonding wire on the chip, avoiding frequent adjustment of the chip angle during the bonding process, improving the convenience and efficiency of bonding, separating adjacent bonding wires in reverse and making the short bonding wires less offset during the packaging process, effectively reducing the risk of short circuits between adjacent bonding wires and between bonding wires and chips during the packaging process, improving bonding reliability, and reducing the probability of risky bonding.
[0019] When an adapter board made of insulating material is used, the adapter board is connected to the substrate and the chip respectively through bonding wires. The long bonding wire connection between the chip and the substrate is improved to multiple short bonding wire connections, shortening the length of a single bonding wire. The conductive connection between the second conductive position and the first conductive position is realized on the adapter board, reducing the space occupied by the bonding wire around the chip, reducing the packaging space required for a single chip and the spacing between adjacent chips, and effectively reducing the packaging size of multiple chips.
[0020] When a metal plate wrapped by an insulating layer is used as an adapter plate, the lower end of the adapter plate is directly welded to the substrate to form a rigid structure that spans from the chip to the substrate. The adapter plate can realize the connection between the chip and the upper chip and the substrate respectively, and serves as a cushioning support for the upper chip, playing the role of a cushioning layer, ensuring the reliability of the upper chip setting and simplifying the packaging structure of the multi-layer chip. BRIEF DESCRIPTION OF THE DRAWINGS
[0021] Figure 1 This is a schematic diagram of the connection between the chip, substrate, and adapter board in Example 1.
[0022] Figure 2 for Figure 1 Top view of the .
[0023] Figure 3 FIG. 1 is a schematic diagram of forming a conductive area on a transfer board by using the first method.
[0024] Figure 4 FIG. 1 is a schematic diagram of forming a conductive area on a transfer board by using the second method.
[0025] Figure 5 This is a schematic diagram of the connection between the chip, substrate, adapter board and upper chip in Example 2.
[0026] Figure 6 The figure is a schematic diagram of a packaging structure of a memory chip and a substrate of the present invention.
[0027] Figure 7 The figure is a schematic diagram of another packaging structure of a memory chip and a substrate according to the present invention. DETAILED DESCRIPTION
[0028] Combine the following Figures 1 to 7 The embodiments of the present invention are described in detail. Embodiment 1:
[0029] A method for connecting a memory chip to a substrate comprises a substrate 1, a chip 2 mounted on the substrate 1, wherein a pad position 21 is located at the center of the chip 2, and is characterized in that the method comprises the following steps: First, a transfer plate 3 is prepared according to the arrangement and number of the pad positions in the center of the chip, and a conductive position 31 corresponding to the pad position 21 is set on the transfer plate 3; Next, the adapter plate 3 is mounted on the chip close to the side of the chip, and the conductive position 31 on the adapter plate 2 is aligned with the Pad position; Afterwards, the adjacent pad positions 21 on the chip 2 are connected to the conductive positions 1 on different adapter plates 3 through bonding wires A, so that the bonding directions of the adjacent pad positions 21 on the chip 2 are opposite; Then, the adapter board 3 is connected to the substrate 1 to form a connection between the chip 2 and the substrate 1 .
[0030] The method for connecting the memory chip and the substrate described above prepares an adapter board 3 according to the arrangement and number of the Pad position 21 in the center of the chip, sets a conductive position 31 on the adapter board 3, and mounts the adapter board on the side of the chip, which is equivalent to using the adapter board 3 and the bonding wire A to move the Pad position outward to the side of the chip. The bonding wire A connects the chip 2 and the adapter board 3, and the adapter board 3 connects the substrate 1. The adapter board 3 is used as an intermediate transition to avoid the Pad position 21 being connected to the substrate 1 through a long bonding wire, shorten the length of a single bonding wire, avoid opening a window on the substrate 1 and encapsulating the WLP copper layer on the surface of the chip 2, and simplify the process flow. The conductive positions 31 on the adapter board 3 are aligned with the Pad positions 21 respectively, and the adjacent Pad positions 21 on the chip 2 are connected to the conductive positions 31 on different adapter boards 3 through bonding, so that the bonding directions of adjacent Pad positions 21 on the chip 2 are opposite, thereby increasing the operating space and adjustment angle of a single bonding wire on the chip, avoiding frequent adjustment of the chip angle during the bonding process, improving the convenience and efficiency of bonding, separating adjacent bonding wires in reverse and making the short bonding wires less offset during the packaging process, effectively reducing the risk of short circuits between adjacent bonding wires and between bonding wires and chips during the packaging process, improving bonding reliability, and reducing the probability of risky bonding.
[0031] Among them, the conductive position 2 32 is set on the adapter board 3, the conductive position 2 31 is connected to the conductive position 1 31 correspondingly, and the conductive position 2 32 is connected to the pin on the substrate 1 through the bonding wire 4, so as to form a connection between the adapter board 3 and the substrate 1. The adapter board 3 is connected to the substrate 1 and the chip 2 through bonding wires respectively, and the chip 2 and the substrate 1 are connected by a long bonding wire connection to a multi-segment short bonding wire connection, shortening the length of a single bonding wire, and the conductive connection between the conductive position 2 32 and the conductive position 1 31 is realized on the adapter board, reducing the space occupied by the bonding wire around the chip, reducing the packaging space required for a single chip and the spacing between adjacent chips, and effectively reducing the packaging size of multiple chips.
[0032] The conductive position 2 32 and the conductive position 1 31 on the adapter board 3 are combined to form a conductive area 4. There are two adapter blocks 3. The two adapter boards 3 are mounted on both sides of the pad position 21. The conductive areas 4 are arranged in parallel on the adapter board 3. The conductive position 1 31 and the conductive position 2 32 are combined into the conductive area 4, which reduces the number of conductive positions on the adapter board 3 and facilitates the setting of the conductive positions on the adapter board 3. Figure 1~2 As shown, two adapter plates 3 are respectively arranged on both sides of the Pad position, and the conductive areas 4 on the adapter plates 3 are respectively aligned with one Pad position, and the conductive positions on the two adapter plates 3 are not aligned. The bonding directions between two adjacent Pad positions 21 and the conductive position areas 4 are opposite, and the bonding between the conductive area 4 and the Pad position 21 is set inward, while the bonding between the conductive area 4 and the substrate 1 is set outward. The two bonding directions in the same conductive area 4 are opposite, the bonding operation angle is large, the space is large, the bonding operation is convenient, the interference risk of adjacent or close bonding during the packaging process is reduced, the bonding reliability is improved, and the probability of risk bonding is reduced.
[0033] The adapter plate 3 is an insulating plate formed by depositing a seed layer on the surface of a silicon oxide plate. A groove 5 corresponding to the conductive area 4 is provided on the upper surface of the adapter plate 3, and the conductive area 4 is formed in the groove 5 by an electroplating process. The adapter plate 3 is a dielectric layer mounted on the chip 2 and forms an insulating film by depositing a seed layer. The conductive area 4 is arranged in the groove 5 on the adapter plate 3. The conductive area 4 is used as a transfer position to ensure that the chip 2 is effectively connected to the substrate 1 and is reliably isolated from the circuit layer on the chip 2, thereby ensuring the reliability of the chip package.
[0034] There are two methods for forming the conductive area 4 on the adapter plate 3; The first method is to form a conductive metal layer on the upper surface of the adapter plate 3 by electroplating according to the distribution position of the conductive area 4, and then cover the conductive metal layer with an insulating layer 7, and then expose the conductive metal layer at the location of the conductive area 4 by an exposure or development process to form a groove 5 and a conductive area 4 in the groove, such as Figure 3 shown.
[0035] The second type: Figure 4 As shown, a groove 5 is first etched on the adapter plate 3 , and then a conductive metal layer is electroplated in the groove 5 to form a conductive area 4 .
[0036] The molding of the above two methods is simple, and the conductivity reliability of the conductive area 4 and the insulation reliability of the adapter plate are ensured. Embodiment 2:
[0037] The difference from the first embodiment is that the adapter board 3 is a metal plate wrapped by an insulating layer, and the number is the same as the number of pad positions 21 on the chip. The conductive position 1 31 is the metal surface exposed on the top of the adapter board 3, and the lower end of the adapter board 3 is welded to the pin of the substrate 1. In this embodiment, the adapter board 3 is mounted on the chip, and the lower end is directly welded to the substrate 1 to form a rigid structure spanning from the chip 2 to the substrate 1. The upper chip can be set on the chip 2, and the connection between the chip 2 and the substrate 1 is realized through the adapter board 3. It also serves as a cushioning support for the upper chip and plays the role of a cushioning layer to ensure the reliability of the upper chip setting.
[0038] The adapter board 3 is set to a right-angle shape, and the adapter board 3 is overlapped and pasted on the chip so that the top surface of the adapter board 3 is parallel to the chip 2. The upper chip 6 is arranged above the adapter board 3, and the upper chip 6 is supported on the adapter board 3 by mounting, and the upper chip 6 is connected to the adapter board 3 by bonding wire A. The adapter board 3 is in a right-angle shape, mounted on the chip 2 and welded to the substrate 1. The top surface of the adapter board 3 serves as a supporting surface parallel to the chip 2. The adapter board 3 realizes the connection between the chip 2 and the upper chip 6 and the substrate 1 respectively, and also serves as a cushioning support for the upper chip 6, ensuring the reliability of the upper chip setting and simplifying the packaging structure of the multi-layer chip.
[0039] The adapter plates 3 are evenly distributed on both sides of the chip 2 to form a symmetrical support structure around the chip 2. The adapter plates 3 are distributed on both sides of the chip 2 to form a symmetrical support structure around the chip 2, which can support multiple upper chips 6. At the same time, the adapter plates 3 also serve as a transition structure between the upper chip 6 and the substrate. The upper chip 6 is connected to the adapter plates 3 by wire bonding to achieve the connection between the upper chip 3 and the substrate 1.
[0040] The present invention also protects a packaging structure of a memory chip and a substrate using the above-mentioned method for connecting a memory chip and a substrate, comprising a substrate 1, a chip 2 mounted on the substrate 1, a pad position 21 located at the center of the chip 2, and characterized in that: an adapter board is mounted on the chip 1 close to the side of the chip, a conductive position 31 corresponding to the pad position 21 is provided on the adapter board 3, the conductive position 31 is wiredly connected to the pad position 21, and the adapter board 3 is connected to the substrate 1.
[0041] The packaging structure of the memory chip and the substrate described above mounts the adapter board 3 on the outside of the Pad position 21, which is equivalent to using the adapter board 3 and the bonding wire A to move the Pad position outward to the side of the chip. The bonding wire A connects the chip 2 and the adapter board 3, and the adapter board 3 connects the substrate 1. The adapter board 3 is used as an intermediate transition to avoid connecting the Pad position 21 to the substrate 1 through a long bonding wire, shorten the length of a single bonding wire, avoid opening a window on the substrate 1 and encapsulating the WLP copper layer on the surface of the chip 2, and simplify the process flow. The conductive positions 31 on the adapter board 3 are aligned with the Pad positions 21 respectively, and the adjacent Pad positions 21 on the chip 2 are connected to the conductive positions 31 on different adapter boards 3 through bonding, so that the bonding directions of adjacent Pad positions 21 on the chip 2 are opposite, thereby increasing the operating space and adjustment angle of a single bonding wire on the chip, avoiding frequent adjustment of the chip angle during the bonding process, improving the convenience and efficiency of bonding, separating adjacent bonding wires in reverse and making the short bonding wires less offset during the packaging process, effectively reducing the risk of short circuits between adjacent bonding wires and between bonding wires and chips during the packaging process, improving bonding reliability, and reducing the probability of risky bonding.
[0042] The upper chip 6 is also included, and the upper chip 6 is supported on the adapter board 3 by mounting, and connected to the adapter board 3 by bonding wires A. The adapter board 3 is used as a cushioning support for the upper chip 6, and also as a transition transfer structure between the upper chip 6 and the chip 2 and the substrate 1, so as to realize the packaging of multi-layer chips.
[0043] The above is a complete description of the technical solutions of the embodiments of the present invention in conjunction with the accompanying drawings. It should be noted that the described embodiments are only part of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.
Claims
1. A method for connecting a memory chip to a substrate, comprising a substrate and a chip mounted on the substrate, wherein the pad is located at the center of the chip, and is characterized in that: The following steps are involved: First, a transfer plate is prepared according to the arrangement and number of the pad positions at the center of the chip, and a conductive position one corresponding to the pad position is set on the transfer plate; Next, mount the adapter plates on the chip along the sides of the chip, and align the conductive position on the adapter plate with the pad position; Afterwards, adjacent pad positions on the chip are connected to conductive positions on different adapter plates through wire bonding, so that the wire bonding directions of adjacent pad positions on the chip are opposite; Then, the adapter board is connected to the substrate to form a connection between the chip and the substrate.
2. The method for connecting a memory chip to a substrate according to claim 1, wherein: A second conductive position is set on the adapter board, the second conductive position is connected to the first conductive position correspondingly, and the second conductive position is connected to the pin on the substrate by wire bonding to form a connection between the adapter board and the substrate.
3. The method for connecting a memory chip to a substrate according to claim 2, wherein: The conductive position 2 and the conductive position 1 on the adapter board are combined to form a conductive area. There are two adapter blocks. The two adapter boards are mounted on both sides of the Pad position, and the conductive areas are distributed in parallel on the adapter boards.
4. The method for connecting a memory chip to a substrate according to claim 3, characterized in that: The adapter plate is an insulating plate formed by depositing a seed layer on the surface of a silicon oxide plate. A groove corresponding to the conductive area is provided on the upper surface of the adapter plate, and a conductive area is formed in the groove by an electroplating process.
5. The method for connecting a memory chip to a substrate according to claim 4, wherein: There are two ways to form the conductive area on the adapter plate; The first method: firstly, a conductive metal layer is formed on the surface of the transfer board by an electroplating process according to the distribution position of the conductive area on the transfer board, and then an insulating layer is covered on the conductive metal layer. Then, the conductive metal layer at the location of the conductive area is exposed by an exposure or development process to form a groove and a conductive area in the groove; The second method is to first etch a groove on the adapter board, and then electroplate a conductive metal layer in the groove to form a conductive area.
6. The method for connecting a memory chip to a substrate according to claim 1, wherein: The adapter plate is a metal plate wrapped by an insulating layer, and the number is the same as the number of pad positions on the chip. The conductive position one is the metal surface exposed on the top surface of the adapter plate, and the lower end of the adapter plate is welded to the pin of the substrate.
7. The method for connecting a memory chip to a substrate according to claim 6, wherein: The adapter board is set to a right-angle shape, and the adapter board is overlapped and pasted on the chip so that the top surface of the adapter board is parallel to the chip. An upper chip is set above the adapter board, and the upper chip is supported on the adapter board by mounting, and the upper chip is connected to the adapter board by wire bonding.
8. The method for connecting a memory chip to a substrate according to claim 7, wherein: The adapter plates are evenly distributed on both sides of the chip to form a symmetrical support structure around the chip.
9. A connection structure of a memory chip and a substrate using the method for connecting a memory chip and a substrate according to any one of claims 1 to 8, comprising a substrate and a chip mounted on the substrate, wherein the pad is located at the center of the chip, and characterized in that: An adapter board is mounted on the chip near the side of the chip, a conductive position one corresponding to the pad position is arranged on the adapter board, the conductive position one is connected to the pad position by wire bonding, and the adapter board is connected to the substrate.
10. The connection structure between the memory chip and the substrate according to claim 9, characterized in that: It also includes an upper chip, which is supported on the adapter board by mounting and connected to the adapter board by wire bonding.