Silicon through hole structure and manufacturing method thereof
By forming trenches or holes in the substrate of the silicon perforated structure and filling a material layer with a moderate coefficient of thermal expansion, the problem of stress around the silicon perforation is solved, and the performance of the transistor and the density of the chip are improved.
Patent Information
- Application Number
- CN202311229980.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2023-09-07
- Filing Date
- 2023-09-21
- Publication Date
- 2025-03-07
AI Technical Summary
Due to the different thermal expansion coefficients of the conductive materials in the substrate and silicon perforations, stress occurs in the substrate around the silicon perforation when the temperature changes, affecting the electron mobility and performance of the transistor.
A silicon perforated structure is designed to relieve stress around the silicon perforation by forming trenches in the substrate and filling a material layer with a moderate coefficient of thermal expansion, or forming a plurality of holes in the substrate and filling a corresponding material layer. The material layer includes tungsten, chromium, iridium, rhenium, zirconium, carbon oxide glass, hydrogen-containing silicon oxynitride, silicon oxide or spin-coated glass.
By introducing a material layer with a moderate coefficient of thermal expansion, the volume expansion gap between copper and silicon is reduced, and the influence range of stress changes is reduced, thereby improving the performance of the transistor and the density of the chip.
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Figure CN119581444A_ABST
Abstract
Description
Technical Field
[0001] The invention relates to a through silicon via structure, in particular to a structure for reducing stress around a through silicon via and a manufacturing method thereof. Background Art
[0002] Manufacturing more reliable, lightweight, compact, fast, multifunctional, and efficient low-cost semiconductor products has always been an important goal of the electronics industry. With the development of highly integrated semiconductor products, the number of input / output pins has increased significantly. The technology of connecting semiconductor chips by using silicon through-hole plugs with small pitches has been widely developed. In this type of packaging structure, the connection between chips is achieved through silicon through-hole structures. Silicon through-holes are conductive through-hole structures that can pass through the entire silicon wafer or chip to provide electrical continuity.
[0003] However, due to the different thermal expansion coefficients of the substrate and the conductive material in the silicon via, when the temperature changes, the deformation of the substrate and the silicon via is different, causing stress in the substrate around the silicon via. The stress will affect the electron mobility of the transistor and thus affect the performance of the transistor. Summary of the invention
[0004] In view of this, the present invention provides a structure for reducing stress around a TSV and a manufacturing method thereof to solve the above-mentioned problem.
[0005] According to a first preferred embodiment of the present invention, a silicon via structure includes a substrate, a through hole penetrating the substrate, a copper layer filling the through hole, a trench buried in the substrate and surrounding the copper layer, and a material layer filling the trench, wherein the material layer includes tungsten (W), chromium (Cr), iridium (Ir), rhenium (Re), zirconium (Zr), carbide oxide glass (SiOC glass), hydrogen-containing silicon oxynitride (SiONH), silicon oxide or spin-on glass.
[0006] According to a second preferred embodiment of the present invention, a silicon via structure includes a substrate, a via penetrating the substrate, a copper layer filling the via, a plurality of holes buried in the substrate and arranged together into a pattern, the pattern surrounds the copper layer and a plurality of material layers fill each hole respectively, each material layer includes tungsten (W), chromium (Cr), iridium (Ir), rhenium (Re), zirconium (Zr), carbon oxide glass, hydrogenated silicon oxynitride, silicon oxide or spin-on glass.
[0007] According to a third preferred embodiment of the present invention, a method for manufacturing a silicon through-hole structure includes providing a substrate, then forming a groove to bury the substrate, then forming a copper layer to fill the groove, and then forming a plurality of holes to bury the substrate and the holes are arranged together into a pattern, the pattern surrounds the copper layer, and finally forming a material layer to fill each hole respectively, wherein the material layer is hydrogen-containing silicon nitride oxide, and the material layer is formed by using flow chemical vapor deposition.
[0008] In order to make the above-mentioned objectives, features and advantages of the present invention more clearly understood, the following is a detailed description of the preferred embodiments and the accompanying drawings. However, the following preferred embodiments and drawings are only for reference and explanation, and are not intended to limit the present invention. BRIEF DESCRIPTION OF THE DRAWINGS
[0009] Figure 1 to Figure 2 A schematic diagram of a method for manufacturing a through silicon via structure according to a first preferred embodiment of the present invention;
[0010] Figure 3 is a top view of the TSV structure in the first preferred embodiment;
[0011] Figures 4 to 5 A schematic diagram of a method for manufacturing a through silicon via structure according to a second preferred embodiment of the present invention;
[0012] Figure 6 is a top view of a through silicon via structure in a second preferred embodiment;
[0013] Figure 7 and Figure 8 A schematic diagram of a method for manufacturing a through silicon via structure according to a third preferred embodiment of the present invention;
[0014] Fig. 9 FIG. 4 is a schematic diagram of a through silicon via structure according to a fourth preferred embodiment of the present invention.
[0015] Explanation of symbols
[0016] 10: Base
[0017] 10a: Front
[0018] 10b: reverse side
[0019] 12: Groove
[0020] 14: Silicon oxide layer
[0021] 16: Buffer layer
[0022] 18: Copper layer
[0023] 18a: Top surface
[0024] 18b: Bottom surface
[0025] 20: Groove
[0026] 22: Material layer
[0027] 22a: Top surface
[0028] 24:Piercing
[0029] 26a: Pattern
[0030] 26b: Pattern
[0031] 26c: Pattern
[0032] 26d: Pattern
[0033] 26e: Pattern
[0034] 28: Holes
[0035] 30a: Pattern
[0036] 30b: Pattern
[0037] 30c: Pattern
[0038] 30d: Pattern
[0039] 30e: Pattern
[0040] 30f: Pattern
[0041] 100:Through silicon structure
[0042] 200:Through silicon structure
[0043] 300:Through silicon structure
[0044] 400:Through silicon structure
[0045] D: Depth
[0046] D1: Depth
[0047] D2: Shortest distance
[0048] D3: Depth
[0049] D4: Shortest distance
[0050] W1: Width
[0051] W2: diameter
[0052] X: Second direction
[0053] Y: First direction DETAILED DESCRIPTION
[0054] Figure 1 to Figure 2 A method for manufacturing a through silicon via structure is shown in accordance with a first preferred embodiment of the present invention. Figure 3 Depicted is a top view of the TSV structure in the first preferred embodiment.
[0055] like Figure 1 As shown, a substrate 10 is provided, and the substrate 10 includes a silicon substrate, a germanium substrate, a gallium arsenide substrate, a silicon germanium substrate, an indium phosphide substrate, a gallium nitride substrate, a silicon carbide substrate or a silicon-coated insulating substrate. The substrate 10 includes a front side 10a and a back side 10b. Then, the substrate 10 is etched starting from the front side 10a of the substrate 10 to form a groove 12 in the substrate 10, and then a silicon oxide layer 14 is formed to conformally cover the sidewall and bottom of the groove 12 and the front side 10a of the substrate 10, and then a buffer layer 16 is formed to conformally cover the silicon oxide layer 12, and then a copper layer 18 is formed to fill the groove 12 and cover the front side 10a of the substrate 10. The silicon oxide layer 14, the buffer layer 16 and the copper layer 18 are made by physical vapor deposition, chemical vapor deposition, atomic layer deposition or electroplating. Then, a grinding process is performed to remove the copper layer 18, the buffer layer 16 and the silicon oxide layer 14 outside the trench 12, so that the top surface of the remaining silicon oxide layer 14 and the top surface of the copper layer 18 are aligned with the front surface 10a of the substrate 10. The buffer layer 16 includes Ti, Ta, TiN or TaN.
[0056] Then, a trench 20 is formed around the outer side of the trench 12 to surround the trench 12, and then a material layer 22 is formed to fill the trench 20. The material layer 22 includes tungsten (W), chromium (Cr), iridium (Ir), rhenium (Re), zirconium (Zr), carbon oxide glass (SiOC glass), hydrogenated silicon oxynitride (SiONH), silicon oxide or spin-on glass. The material layer 22 fills the trench 20 by using flow chemical vapor deposition, physical vapor deposition, chemical vapor deposition or atomic layer deposition. Taking the material layer 22 as hydrogenated silicon oxynitride as an example, the material layer 22 fills the trench 20 by using flow chemical vapor deposition to form the material layer 22. The operating conditions of the flow chemical vapor deposition can be to input the precursor trisilylamine (TSA), ammonia (NH3) and oxygen at a temperature of 65°C to deposit the material layer 22, and then solidify the material layer 22 at 105°C. The advantage of flow-type chemical vapor deposition is that since the precursor at the beginning of deposition is a fluid, the fluid can fill the trench 20 more completely.
[0057] Then, a grinding process is performed to remove the material layer 22 outside the groove 20, so that the top surface 22a of the remaining material layer 22 is aligned with the front surface 10a of the substrate 10. Figure 2As shown, the reverse side 10b of the substrate 10 is ground until the copper layer 18 is exposed. At this time, the groove 12 is transformed into a through hole 24. The bottom surface 18b of the copper layer 18 is flush with the reverse side 10b of the substrate 10. At this point, the TSV structure 100 of the present invention has been completed.
[0058] like Figure 2 As shown, a silicon through hole structure 100 of the present invention comprises a substrate 10, a through hole 24 penetrating the substrate 10, a copper layer 18 filling the through hole 24, a groove 22 buried in the substrate 10 and surrounding the copper layer 18, and a material layer 22 filling the groove 20, the material layer 22 comprises tungsten (W), chromium (Cr), iridium (Ir), rhenium (Re), zirconium (Zr), carbon oxide glass, hydrogen-containing silicon oxynitride, silicon oxide or spin-on glass, and the material layer 22 can also be other materials whose thermal expansion coefficient is greater than the thermal expansion coefficient of silicon and less than the thermal expansion coefficient of copper. A silicon oxide layer 14 and a buffer layer 16 are disposed between the copper layer 18 and the through hole 24, wherein the silicon oxide layer 14 contacts the sidewall of the through hole 24, and the buffer layer 16 contacts the silicon oxide layer 14 and the copper layer 18. The top surface 22a of the material layer 22, the top surface 18a of the copper layer 18 and the front surface 10a of the substrate 10 are cut flush. A first direction Y is perpendicular to the front surface 10a of the substrate 10, and a second direction X is parallel to the front surface 10a of the substrate 10. Along the first direction Y, the depth D1 of the trench 20 is 0.5 to 5% of the depth D of the through hole 24. According to a preferred embodiment, the depth D1 of the trench 20 is preferably between 0.25 micrometers and 2 micrometers. Since the channel region of the subsequent transistor is disposed close to the front surface 10a of the substrate 10, the depth D1 of the trench 20 does not need to be as deep as the through hole 24. The depth D1 of the trench 20 only needs to be sufficient to overlap the channel region of the transistor, so the depth D1 of the trench 20 is smaller than the depth D of the through hole 24. Along the second direction X, the width W1 of the trench 20 is between 0.05 micrometers and 2 micrometers. In addition, along the second direction X, the shortest distance D2 between the through hole 24 and the trench 20 is between 0.5 micrometers and 2 micrometers.
[0059] Please also see Figure 2 and Figure 3 According to different requirements, the groove 20 can form different patterns 26a / 26b / 26c / 26d / 26e. For example, from the top view, pattern 26a is a closed circular ring, pattern 26b is a closed hexagonal ring, pattern 26c is a closed octagonal ring, pattern 26d is a closed decagonal ring, and pattern 26e is a closed dodecagonal ring. According to different requirements, the pattern can be a closed polygonal ring of other shapes, but the number of angles of the polygonal ring must be greater than 6 and be an even number.
[0060] Figures 4 to 5 A method for manufacturing a through silicon via structure is shown in accordance with a second preferred embodiment of the present invention. Figure 6The top view of the TSV structure in the second preferred embodiment is shown, wherein the components with the same functions will use the component numbers in the first preferred embodiment.
[0061] Please also see Figure 4 and Figure 6 The difference between the first preferred embodiment and the second preferred embodiment is that in the second preferred embodiment, after the silicon oxide layer 14, the buffer layer 16 and the copper layer 18 outside the groove 12 are removed by a grinding process, instead of forming a groove, a plurality of holes 28 are formed around the groove 12, and then a plurality of material layers 22 are formed to fill each hole 28 respectively. The material layer 22 includes tungsten (W), chromium (Cr), iridium (Ir), rhenium (Re), zirconium (Zr), carbon oxide glass, hydrogenated silicon oxynitride, silicon oxide or spin-on glass. The material layer 22 fills the holes 28 by flow chemical vapor deposition, physical vapor deposition, chemical vapor deposition or atomic layer deposition. For example, when the material layer 22 is hydrogenated silicon oxynitride, the material layer 22 fills the holes 28 by flow chemical vapor deposition. The operating conditions of flow chemical vapor deposition are to input precursor trisilylamine (TSA), ammonia (NH3) and oxygen at a temperature of 65°C to deposit the material layer 22, and then solidify the material layer 22 at 105°C. The advantage of flow chemical vapor deposition is that the precursor at the beginning of deposition is a fluid, and the fluid can fill the holes 28 more completely.
[0062] Then, a grinding process is performed to remove the material layer 22 outside the hole 28, so that the top surface 22a of the remaining material layer 22 is aligned with the front surface 10a of the substrate 10. Figure 5 As shown, the reverse side 10b of the substrate 10 is ground until the copper layer 18 is exposed. At this time, the groove 12 is transformed into a through hole 24, and the bottom surface 18b of the copper layer 18 is flush with the reverse side 10b of the substrate 10. At this point, the through silicon via structure 200 of the present invention has been completed.
[0063] like Figure 5As shown, a silicon through-hole structure 200 of the present invention comprises a substrate 10, a through-hole 24 penetrating the substrate 10, a copper layer 18 filling the through-hole 24, a silicon oxide layer 14 and a buffer layer 16 disposed between the copper layer 18 and the through-hole 24, wherein the silicon oxide layer 14 contacts the sidewall of the through-hole 24, and the buffer layer 16 contacts the silicon oxide layer 14 and the copper layer 18. A plurality of holes 28 are embedded in the substrate 10, and a plurality of material layers 22 fill each hole 28 respectively, and each material layer 22 comprises W, Cr, Ir, Re, Zr, carbon oxide glass, hydrogen-containing silicon oxynitride, silicon oxide or spin-on glass, and the material layer 22 may also be other materials whose thermal expansion coefficient is greater than that of silicon and less than that of copper. The top surface 22a of the material layer 22, the top surface 18a of the copper layer 18 and the front surface 10a of the substrate 10 are cut flush. A first direction Y is perpendicular to the front surface 10a of the substrate 10, and a second direction X is parallel to the front surface 10a of the substrate 10. Along the first direction Y, the depth D3 of each hole 28 is 0.5 to 5% of the depth of the through hole D. According to a preferred embodiment, the depth D3 of each hole 28 is preferably between 0.25 micrometers and 2 micrometers. Since the channel region of the subsequent transistor is set close to the front surface 10a of the substrate 10, the depth D3 of the hole 28 does not need to be as deep as the through hole 24. The depth D3 of the hole 28 only needs to be enough to overlap the channel region of the transistor. Therefore, the depth D3 of the hole 28 is smaller than the depth D of the through hole 24. Along the second direction X, the diameter W2 of each hole 28 is between 0.05 micrometers and 2 micrometers. In addition, along the second direction X, the shortest distance D4 between the through hole 24 and each hole 28 is between 0.5 micrometers and 2 micrometers.
[0064] like Figure 6 As shown, all holes 28 are arranged together to form a pattern 30a / 30b / 30c / 30d / 30e / 30f. The pattern 30a / 30b / 30c / 30d / 30e / 30f surrounds the copper layer 18. The number of holes 28 can be changed according to different needs, but the number of holes 28 is preferably greater than 6 and is an even number. For example, the pattern 30a is a closed ring composed of 6 holes 28, and the pattern 30b is a closed ring composed of 12 holes 28. The pattern 30c / 30d / 30e / 30f can be a closed polygonal ring. The number of corners of the polygonal ring can be changed according to different needs, but the number of corners is preferably greater than 6 and is an even number. For example, the pattern 30c is a closed hexagonal ring, the pattern 30d is a closed octagonal ring, the pattern 30e is a closed decagonal ring, and the pattern 30f is a closed dodecagonal ring. Each hole 28 is located at the corner of the polygonal ring. The polygonal ring is formed by connecting each hole with a dotted line. Figure 6The dotted lines in the figure are only for illustrating the shape of the closed polygonal ring, and do not actually exist on the substrate 10. The number of holes 28 in the pattern 30c / 30d / 30e / 30f can also be changed and is not limited to the number shown in the figure. Similarly, the number of holes 28 is preferably more than 6 and an even number.
[0065] Figure 7 and Figure 8 A method for manufacturing a through silicon via structure according to a third preferred embodiment of the present invention is shown, wherein components having the same functions will use the component numbers of the first preferred embodiment.
[0066] like Figure 7 As shown, a substrate 10 is provided, and the substrate 10 includes a front surface 10a and a back surface 10b. Then, the substrate 10 is etched from the front surface 10a of the substrate 10 to form a trench 12 in the substrate 10, and then a silicon oxide layer 14, a buffer layer 16 and a material layer 22 are formed in sequence to conform to the sidewall and bottom of the trench 12 and the front surface 10a of the substrate 10. Then, a copper layer 18 is formed to fill the trench 12. The material layer 22 includes tungsten (W), chromium (Cr), iridium (Ir), rhenium (Re), zirconium (Zr), carbon oxide glass, hydrogen-containing silicon oxynitride, silicon oxide or spin-on glass. The material layer 22 fills the trench by using flow chemical vapor deposition, physical vapor deposition, chemical vapor deposition or atomic layer deposition. Then, the silicon oxide layer 12, the buffer layer 14, the material layer 22 and the copper layer 18 outside the trench 12 are removed by a grinding process.
[0067] like Figure 8 As shown, the reverse side 10b of the substrate 10 is ground until the copper layer 18 is exposed, and the groove a is transformed into a through hole 24. Thus, the through silicon via structure 300 of the present invention is completed. The difference between the first preferred embodiment and the second preferred embodiment is that in the third preferred embodiment, no groove or hole surrounding the copper layer 18 is formed, because in the third preferred embodiment, the material layer 22 is directly disposed in the groove 12 and the material layer 22 contacts the copper layer 18.
[0068] Therefore, the silicon via structure 300 includes a substrate 10, a through hole 24 penetrating the substrate 10, a silicon oxide layer 14 covering and contacting the side wall of the through hole 24, a copper layer 18 filling the through hole 24, a buffer layer 16 and a material layer 22 located between the copper layer 18 and the silicon oxide layer 14, the buffer layer 16 contacting the silicon oxide layer 14, and the material layer 22 contacting the copper layer 18. Therefore, the silicon oxide layer 14, the buffer layer 16, the material layer 22 and the copper layer 18 are arranged in sequence from the side wall close to the through hole 24 to the side wall far away from the through hole 24. Because the material layer 22 is disposed in the through hole 24, the aforementioned shortest distance D2 / D4 is reduced, so the size of the device can be further reduced.
[0069] Fig. 9 A through silicon via structure is shown according to a fourth preferred embodiment of the present invention.
[0070] The difference between the TSV structure 400 in the fourth preferred embodiment and the TSV structure 300 in the third preferred embodiment is that the material layer 22 in the TSV structure 400 contacts the sidewall of the through-hole 24, that is, the material layer 22, the silicon oxide layer 14, the buffer layer 16 and the copper layer 18 are arranged in sequence from close to the sidewall of the through-hole 24 to far away from the sidewall of the through-hole 24.
[0071] Since the thermal expansion coefficients of the copper in the silicon via structure and the silicon substrate are greatly different, the volumes of the two expand differently under temperature changes, which will cause stress changes in the substrate around the silicon via structure. In order to avoid affecting the performance of the transistor, the transistor needs to be more than 20 microns away from the silicon via structure, which will increase the volume of the chip. Therefore, the present invention sets a material layer around the silicon via structure, and specially selects a material with a thermal expansion coefficient between copper and silicon as the material layer, so as to reduce the difference in volume expansion between copper and silicon, thereby reducing the range of stress change. Therefore, after adding the material layer, the distance between the transistor and the silicon via structure can be reduced, and the volume of the chip is also reduced.
[0072] The above descriptions are only preferred embodiments of the present invention. All equivalent changes and modifications made according to the claims of the present invention should fall within the scope of the present invention.
Claims
1. A through silicon via structure, comprising: substrate; Perforating the substrate; The copper layer fills the through hole; A trench is buried in the substrate and surrounds the copper layer; as well as The trench is filled with a material layer, wherein the material layer includes tungsten (W), chromium (Cr), iridium (Ir), rhenium (Re), zirconium (Zr), carbide oxide glass (SiOC glass), silicon oxynitride containing hydrogen (SiONH), silicon oxide or spin-on glass. 2 . The TSV structure as claimed in claim 1 , wherein the groove forms a pattern, and the pattern comprises a closed circular ring, a closed hexagonal ring, a closed octagonal ring, a closed decagonal ring or a closed dodecagonal ring.
3. The through silicon via structure as claimed in claim 1, wherein a first direction is perpendicular to the front surface of the substrate, a second direction is parallel to the front surface of the substrate, along the first direction, the depth of the groove is between 0.25 micrometers and 2 micrometers, and along the second direction, the width of the groove is between 0.05 micrometers and 2 micrometers.
4. The TSV structure as claimed in claim 1, wherein the first direction is perpendicular to the front surface of the substrate, the second direction is parallel to the front surface of the substrate, and along the second direction, the shortest distance between the through hole and the groove is between 0.5 microns and 2 microns. 5 . The through silicon via structure as claimed in claim 1 , wherein a first direction is perpendicular to the front surface of the substrate, and along the first direction, a depth of the trench is 0.5 to 5% of a depth of the through hole. 6 . The through silicon via structure as claimed in claim 1 , further comprising a silicon oxide layer and a buffer layer disposed between the copper layer and the through hole. 7 . The through silicon via structure as claimed in claim 1 , wherein a top surface of the material layer, a top surface of the copper layer, and a front surface of the substrate are aligned. 8 . The through silicon via structure as claimed in claim 1 , wherein a bottom surface of the copper layer is flush with a reverse surface of the substrate.
9. A through silicon via structure, comprising: substrate; Perforating the substrate; The copper layer fills the through hole; A plurality of holes are embedded in the substrate and the holes are collectively arranged in a pattern, the pattern surrounding the copper layer; and The holes are filled with a plurality of material layers, respectively, and the material layers respectively include tungsten (W), chromium (Cr), iridium (Ir), rhenium (Re), zirconium (Zr), carbide oxide glass (SiOC glass), silicon oxynitride containing hydrogen (SiONH), silicon oxide or spin-on glass. 10 . The TSV structure as claimed in claim 9 , wherein the pattern comprises a closed circular ring, a closed hexagonal ring, a closed octagonal ring, a closed decagonal ring or a closed dodecagonal ring.
11. The through silicon via structure as claimed in claim 9, wherein a first direction is perpendicular to the front surface of the substrate, a second direction is parallel to the front surface of the substrate, along the first direction, the depth of each of the holes is between 0.25 micrometers and 2 micrometers, and along the second direction, the diameter of each of the holes is between 0.05 micrometers and 2 micrometers.
12. The TSV structure as claimed in claim 9, wherein a first direction is perpendicular to the front surface of the substrate, a second direction is parallel to the front surface of the substrate, and along the second direction, the shortest distance between the through hole and each of the holes is between 0.5 microns and 2 microns. 13 . The TSV structure as claimed in claim 9 , wherein a first direction is perpendicular to the front surface of the substrate, and along the first direction, a depth of each of the holes is 0.5 to 5% of a depth of the through hole. 14 . The through silicon via structure as claimed in claim 9 , further comprising a silicon oxide layer and a buffer layer disposed between the copper layer and the through hole. 15 . The through silicon via structure as claimed in claim 9 , wherein top surfaces of the material layers, the top surface of the copper layer, and the front surface of the substrate are aligned. 16 . The through silicon via structure as claimed in claim 9 , wherein a bottom surface of the copper layer is flush with a reverse surface of the substrate.
17. A method for manufacturing a through silicon via structure, comprising: providing a substrate; forming a trench to bury the substrate; forming a copper layer to fill the trench; forming a plurality of holes embedded in the substrate and arranged together in a pattern, the pattern surrounding the copper layer; and A material layer is formed to fill each of the holes respectively, wherein the material layer is silicon oxynitride containing hydrogen (SiONH), and the material layer is formed by using flow chemical vapor deposition.
18. The method for manufacturing a through silicon via structure as claimed in claim 17, wherein the flow chemical vapor deposition comprises: Inputting precursor trisilylamine (TSA), ammonia (NH 3 ) and oxygen at a temperature of 65° C. to deposit the material layer; and The material layer was cured at 105°C.