Switched capacitor amplifier

Abstract

The invention discloses a switched capacitor amplifier, and relates to the technical field of analog or digital-analog hybrid integrated circuits, the switched capacitor amplifier comprises a biasing circuit, a first-stage transconductance amplifier and a second-stage transconductance amplifier, when the amplifier works in an amplification state, a large current is needed, so that the amplifier can be quickly established, and the reliability of the amplifier is improved. Through the technology provided by the invention, relatively large current can be provided; when the amplifier works in a reset state, only a correct working point needs to be provided, large current is not needed, the technology provided by the invention can reduce the current to a set value, and the power consumption of the amplifier can be reduced to the maximum extent. The defect that in a traditional structure, the power consumption of the amplifier is large due to the fact that the current of the amplifier working in the reset state and the amplification state is not adjusted is overcome. According to the technology provided by the invention, the gain of the amplifier can be switched according to different working modes of the amplifier, and the defect that the gain cannot be changed in a traditional structure is overcome.

Description

Technical Field

[0001] The present application relates to the technical field of analog or mixed analog and digital integrated circuits, and in particular to a switched capacitor amplifier. Background Art

[0002] As an important module of analog circuits, amplifiers are widely used in various analog integrated circuits and mixed analog and digital integrated circuits. Among them, amplifiers with switched capacitor structures are an important type of amplifier application.

[0003] The two-stage switched capacitor amplifier conventionally used in switched capacitor circuits includes a bias circuit, a first-stage transconductance amplifier, and a second-stage transconductance amplifier. Figure 1 The bias circuit of the conventional two-stage switched capacitor amplifier is shown in FIG. 1 . The constant current source IB is injected into the drain of the NMOS tube M0. The NMOS tube M0 is in the form of a diode connection. The gate of the NMOS tube M0 is connected to the gate of the NMOS tube M1. The sources of the NMOS tube M0 and the NMOS tube M1 are both grounded. The drain of the NMOS tube M1 is connected to the drain of the PMOS tube M3. The source of the PMOS tube M3 is connected to the drain of the PMOS tube M4. The PMOS tube M3 and the PMOS tube M4 are both in the form of a diode connection. The source of the PMOS tube M4 is connected to the power supply vdd. The gate of the PMOS tube M5 is connected to the gate of the PMOS tube M4. The source of the PMOS tube M5 is connected to the power supply vdd. The drain of the PMOS tube M5 is connected to the source of the PMOS tube M6. The gate of the PMOS tube M6 is connected to the gate of the PMOS tube M3. The drain of the PMOS tube M6 is connected to the drain of the NMOS tube M2, the NMOS tube M2 is in the form of a diode connection, the source of the NMOS tube M2 is grounded, and the gate and drain bias voltages of the NMOS tube M2 are vn1. The gate of the PMOS tube M7 is connected to the gate of the PMOS tube M6, the source of the PMOS tube M7 is connected to the drain of the PMOS tube M8, the source of the PMOS tube M8 is connected to the power supply vdd, the gate of the PMOS tube M8 is connected to the drain of the PMOS tube M7, the gate bias voltage of the PMOS tube M8 is vb1, the drain of the PMOS tube M7 is connected to the drain of the NMOS tube M9, the source of the NMOS tube M9 is grounded, and the gate of the NMOS tube M9 is connected to the gate of the NMOS tube M1. vn1, vb and vb1 provide fixed bias voltages for the gain stage of the switched capacitor amplifier. Figure 2It is a first-stage transconductance amplifier of a traditional two-stage switched capacitor amplifier, wherein PMOS tubes M10, M11, M12, M13, M14, and M15 constitute the input stage of the first-stage transconductance amplifier, wherein PMOS tubes M10 and M11 are the input differential pair tubes of the first-stage transconductance amplifier, and the gates of PMOS tubes M10 and M11 are connected to input signals VP and VM respectively. PMOS tubes M12, M13, M14, and M15 constitute a common source and common gate structure. Among them, the gates of PMOS tubes M12 and M13 are connected to a fixed bias vb, and the drains are connected at the same time. The gates of PMOS tubes M14 and M15 are connected to a fixed bias vb1, and the bias voltages vb and vb1 are fixed bias voltages. NMOS tubes M16, M17, M18, M19, M20, M21, M22, M23, M24, M25 and M39 and PMOS tubes M26, M27, M28, M29, M30 and M31 constitute a first gain stage of a first transconductance amplifier, wherein the PMOS tubes M26, M27, M28, M29, M30 and M31 constitute a gain bootstrap structure, and the NMOS tubes M16, M17, M18, M19, M20, M21, M22, M23, M24, M25 and M39 constitute a negative resistance structure, and the functions of the above structures are to increase the output impedance of the first gain stage. Figure 3 It is the second-stage transconductance amplifier of the traditional two-stage switched capacitor amplifier. NMOS tubes M32 and M33 are the input differential pair tubes of the second-stage transconductance amplifier. The gates of NMOS tubes M32 and M33 are connected to the output signals vo1 and vo2 of the first-stage transconductance amplifier respectively. PMOS tubes M34, M35, M36 and M37 are load tubes, providing the first-stage gain stage of the first-stage transconductance amplifier, wherein vb1 and vb are fixed bias voltages.

[0004] The disadvantages of the above-mentioned traditional amplifier structure are: 1. Each bias voltage of the amplifier is a fixed bias voltage, so that the bias current of the amplifier remains unchanged regardless of whether the amplifier is working in the reset state or the amplification state, and thus the power consumption does not change. In practical applications, when the amplifier is working in the amplification state, it is often necessary to establish a large signal, which requires a large current; when the amplifier is working in the reset state, it only needs to provide the correct operating point, and does not need to provide a large current. In the traditional structure, there is no distinction between the current when the amplifier is working in the reset state and the amplification state. Therefore, in order to meet the establishment time of the amplifier in the amplification state, a large power consumption will also be consumed in the reset state, resulting in a large power consumption of the amplifier. 2. Under the traditional amplifier structure, the gain of the amplifier in the reset phase and the amplification phase is the same. Since the amplifier has an offset voltage, the offset voltage needs to be eliminated, and the high gain will cause the amplifier to exit the saturation region during the offset storage phase, affecting the accuracy of the amplifier.

[0005] In view of this, a switched capacitor amplifier is urgently needed. Summary of the invention

[0006] In view of the shortcomings of the prior art described above, the present application proposes a switched capacitor amplifier, which solves the problem in the prior art that the current of the amplifier is not regulated when it is working in the reset state and the amplification state, resulting in high power consumption of the amplifier and the gain of the amplifier cannot be changed in the reset and amplification states.

[0007] In order to achieve the above-mentioned purpose, this application specifically adopts the following technical solutions:

[0008] A switched capacitor amplifier comprises a bias circuit, a first-stage transconductance amplifier and a second-stage transconductance amplifier, wherein:

[0009] The bias circuit includes a constant current source IB, which is injected into the drain of the NMOS tube M0. The NMOS tube M0 is in a diode connection form. The gate of the NMOS tube M0 is connected to the gate of the NMOS tube M1, and the sources of the NMOS tubes M0 and M1 are both grounded; the drain of the NMOS tube M1 is connected to the drain of the PMOS tube M3, the source of the PMOS tube M3 is connected to the drain of the PMOS tube M4, the PMOS tubes M3 and M4 are both in a diode connection form, and the source of the PMOS tube M4 is connected to the power supply vdd; the gate of the PMOS tube M5 is connected to the gate of the PMOS tube M4, the source of the PMOS tube M5 is connected to the power supply vdd, and the drain of the PMOS tube M5 is connected to the gate of the PMOS tube M4. The source of the PMOS tube M6 is connected, and the gate of the PMOS tube M6 is connected to the gate of the PMOS tube M3; the drain of the PMOS tube M6 is connected to the drain of the NMOS tube M2, the NMOS tube M2 is in the form of a diode connection, the source of the NMOS tube M2 is grounded, and the gate and drain bias voltages of the NMOS tube M2 are vn1; the gate of the NMOS tube M2 is connected to one end of the capacitor C4 through the switch k3, one end of the capacitor C3, and the switch k3n in sequence, and the other end of C3 is connected to the power supply vdd; the other end of the capacitor C4 is connected to one end of the switch k4 and the switch k4n at the same time, the other end of the switch k4n is connected to the power supply vdd, and the other end of the switch k4 is connected to the fixed bias voltage vn;

[0010] The invention also includes a PMOS tube M7, wherein the gate of the PMOS tube M7 is connected to the gate of the PMOS tube M6, the source of the PMOS tube M7 is connected to the drain of the PMOS tube M8, the source of the PMOS tube M8 is connected to the power supply vdd, the gate of the PMOS tube M8 is connected to the drain of the PMOS tube M7, the gate bias voltage of the PMOS tube M8 is vb1, the drain of the PMOS tube M7 is connected to the drain of the NMOS tube M47, the source of the NMOS tube M47 is grounded, and the gate of the NMOS tube M47 is connected to the gate of the NMOS tube M1; the gate of the PMOS tube M8 is connected to one end of the capacitor C2 through the switch k1, one end of the capacitor C1, and the switch k1n in sequence, and the other end of C1 is connected to the power supply vdd; the other end of the capacitor C2 is simultaneously connected to one end of the switch k2 and the switch k2n, the other end of the switch k2n is grounded, and the other end of the switch k2 is connected to the fixed bias voltage vb.

[0011] As an optional technical solution, when the switched capacitor amplifier is in a reset phase, switches k1, k2, k3 and k4 are turned on, and switches k1n, k2n, k3n and k4n are turned off;

[0012] One end of capacitor C3 is charged to bias voltage vn1, and the other end is power supply voltage vdd. The other end of capacitor C4 is charged to bias voltage vn through turned-on switch k4, and one end is adjustable bias voltage vn2 of reset phase. Since vn2 is equal to vn1 in the previous state, vn2 is equal to vn1 at this time.

[0013] One end of capacitor C1 is charged to bias voltage vb1, and the other end is power supply voltage vdd. The other end of capacitor C2 is charged to bias voltage vb through the turned-on switch k2. Since vb2 is equal to vb1 in the previous state, at this time, the upper plate bias voltage vb2 is equal to vb1.

[0014] As an optional technical solution, when the switched capacitor amplifier is in the amplification phase, switches k1n, k2n, k3n and k4n are turned on, and switches k1, k2, k3 and k4 are turned off;

[0015] The other end of the capacitor C4 is charged to the power supply voltage vdd through the turned-on switch k4n. According to the charge conservation theorem, at this time vn2 = vn1 + C4 (vdd-vn) / (C3 + C4). Therefore, vn2 in the amplification phase is increased by C4 (vdd-vn) / (C3 + C4) compared with vn2 in the reset phase.

[0016] The other end of capacitor C2 is discharged to 0 through the turned-on switch k2n. According to the law of conservation of charge, at this time vb2=vb1-C2(vb2-vb) / (C1+C2). Therefore, vb2 in the amplification phase is lower than vb2 in the reset phase by C2(vb2-vb) / (C1+C2).

[0017] As an optional technical solution, the first-stage transconductance amplifier includes an input stage of a first-stage transconductance amplifier composed of PMOS tubes M9, M10, M11, M12, M13, M14, M15 and M16, and a first-stage gain stage of a first-stage transconductance amplifier composed of NMOS tubes M17, M18, M19, M20, M21, M22, M31, M32, M33, M34, M35, M36, M37, M38, M48, M49, M50 and PMOS tubes M23, M24, M25, M26, M27, M28, M29, M30; wherein:

[0018] The PMOS tubes M9 and M10 are input differential pair tubes, and the gates of the PMOS tubes M9 and M10 are connected to the input signals VP and VM respectively; the PMOS tubes M11, M12, M13, M14, M15 and M16 are of common source and common gate structure; the gates of the PMOS tubes M11 and M12 are connected and connected to the fixed bias voltage vb, and the drains are connected and connected to the sources of the PMOS tubes M9 and M10; the gates of the PMOS tubes M13 and M15 are connected and connected to the fixed bias voltage vb1, and the drains of the PMOS tubes M13 and M14 are connected and connected to the source of the PMOS tube M12; the gates of the PMOS tubes M14 and M16 are connected and connected to the variable bias voltage vb2, and the drains of the PMOS tubes M15 and M16 are connected and connected to the source of the PMOS tube M11; the sources of the PMOS tubes M13, M14, M15 and M16 are all connected to the power supply voltage vdd;

[0019] The PMOS tubes M23, M24, M25, M26, M27, M28, M29 and M30 constitute a gain bootstrap structure in the first gain stage, and the NMOS tubes M17, M18, M19, M20, M21, M22, M31, M32, M33, M34, M35, M36, M37, M38, M48, M49 and M50 constitute a negative resistance structure in the first gain stage.

[0020] It should be noted that the PMOS tubes M21 and M22 are part of the gain bootstrap structure and are also included in the negative resistance structure, which are collectively described as negative resistance structures here.

[0021] As an optional technical solution, the gain bootstrap structure is: the PMOS tubes M29 and M23 form a common source and common gate structure, and the gate is connected to a fixed bias voltage vb1; the gate of the PMOS tube M24 is connected to a variable bias voltage vb2;

[0022] The drain of the PMOS tube M29 is simultaneously connected to the gate of the NMOS tube M21, the source of the NMOS tube M48, the common drain of the NMOS tubes M17 and M18, and the gate of the NMOS tube M35; the gate is simultaneously connected to the drain of the NMOS tube M21 and the drain of the PMOS tube M27; the source is simultaneously connected to the drain of the PMOS tube M23, the drain of the PMOS tube M24, and the gate of the PMOS tube M27; the sources of the PMOS tubes M23, M24, and M27 are all connected to the power supply voltage vdd; the source of the NMOS tube M21 is grounded;

[0023] The PMOS tubes M30 and M25 form a common source and common gate structure, and the gate is connected to a fixed bias voltage vb1; the gate of the PMOS tube M26 is connected to a variable bias voltage vb2;

[0024] The drain of the PMOS tube M30 is simultaneously connected to the gate of the NMOS tube M22, the drain of the NMOS tube M48, the common drain of the NMOS tubes M19 and M20, and the gate of the NMOS tube M34; the gate is simultaneously connected to the drain of the NMOS tube M22 and the drain of the PMOS tube M28; the source is simultaneously connected to the drain of the PMOS tube M25, the drain of the PMOS tube M26, and the gate of the PMOS tube M28; the sources of the PMOS tubes M25, M26, and M28 are all connected to the power supply voltage vdd; the source of the NMOS tube M22 is grounded.

[0025] As an optional technical solution, the negative resistance structure is: the NMOS tubes M17, M31, M32 and M33 form a common source and common gate structure, the gate is connected to a fixed bias voltage vn, the gate of the NMOS tube M32 is connected to a fixed bias voltage vn1, and the gate of the NMOS tube M33 is connected to a variable bias voltage vn2;

[0026] The source of the NMOS tube M17 is simultaneously connected to the source of the NMOS tube M18 and the drains of the NMOS tubes M31, M32, M33 and M34; the gate of the NMOS tube M18 is simultaneously connected to the gates of the NMOS tubes M48 and M19; the gate of the NMOS tube M31 is connected to the drain of the NMOS tube M49; the source of the NMOS tube M49 is connected to the gate of the NMOS tube M35, and the gate is connected to the switch K5n; the sources of the NMOS tubes M31, M32, M33 and M34 are all grounded;

[0027] The NMOS tubes M20, M36, M37 and M38 form a common source and common gate structure, the gates are connected to a fixed bias voltage vn, the gate of the NMOS tube M37 is connected to a fixed bias voltage vn1, and the gate of the NMOS M36 is connected to a variable bias voltage vn2;

[0028] The source of the NMOS tube M20 is simultaneously connected to the source of the NMOS tube M19, the drains of the NMOS tubes M35, M36, M37 and M38, the gate of the NMOS tube M38 is connected to the source of the NMOS tube M50, the drain of the NMOS tube M50 is connected to the gate of the NMOS tube M34, and the gate is connected to the switch K6n, and the sources of the NMOS tubes M35, M36, M37 and M38 are all grounded;

[0029] The common end of the NMOS tube M35 and the PMOS tube M29 serves as the first differential signal output end of the first stage transconductance amplifier, outputting the signal vo1; the common end of the NMOS tube M34 and the PMOS tube M30 serves as the second differential signal output end of the first stage transconductance amplifier, outputting the signal vo2.

[0030] As an optional technical solution, the second-stage transconductance amplifier includes a differential input pair of NMOS tubes M39 and M40, the sources of the NMOS tubes M39 and M40 are connected and connected to one end of the resistor R at the same time, the other end of the resistor R is grounded, and the gates of the NMOS tubes M39 and M40 are connected to the signal vo1 and the signal vo2 respectively;

[0031] The drains of the NMOS tubes M39 and M40 are connected to the drains of the PMOS tubes M42 and M43 respectively, the sources of the PMOS tubes M42 and M43 are connected to the drains of the PMOS tubes M44 and M45 respectively, the sources of the PMOS tubes M44 and M45 are connected to the power supply voltage vdd; the gates of the PMOS tubes M44 and M45 are connected to the fixed bias voltage vb1, and the gates of the PMOS tubes M42 and M43 are connected to the adjustable bias voltage vb2;

[0032] It also includes an NMOS tube M41, the drain of which is connected to the drain of the NMOS tube M39 and the drain of the PMOS tube M42 at the same time, and the common end is used as the first differential signal output end of the second-stage transconductance amplifier to output the signal vop; the source of the NMOS tube M41 is connected to the drain of the NMOS tube M40 and the drain of the PMOS tube M43 at the same time, and the common end is used as the second differential signal output end of the second-stage transconductance amplifier to output the signal vom.

[0033] The beneficial effects of this application include:

[0034] When the amplifier is working in the amplification state, a larger current is required so that the amplifier can be quickly established. The technology proposed in the present invention can provide a larger current. When the amplifier is working in the reset state, only the correct operating point needs to be provided, and a large current is not required. The technology proposed in the present invention can reduce the current to a set value, which can minimize the power consumption of the amplifier. This changes the disadvantage of the traditional structure that the current of the amplifier working in the reset state and the amplification state is not adjusted, resulting in a larger power consumption of the amplifier.

[0035] When the amplifier is working in the reset state, the amplifier stores the offset voltage, and the first-stage amplifier switches to a small output impedance mode and works in a small gain state, so that the transistor of the amplifier does not exit the saturation region while storing the offset voltage; when the amplifier is working in the amplification state, the output impedance of the first-stage amplifier switches to a large impedance mode and works in a large gain state to achieve the signal amplification function. The technology proposed in the present invention can switch the gain of the amplifier according to different working modes of the amplifier, changing the disadvantage of the traditional structure that the gain of the amplifier cannot be changed in the reset and amplification states;

[0036] Other beneficial effects or advantages of the present application will be described in detail in conjunction with the specific structure in the specific implementation manner. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings required for use in the embodiments or the prior art descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative labor. In addition, it should be understood that the proportional relationship of the various components in the drawings of this specification does not represent the proportional relationship in the actual material selection and design, which is only a schematic diagram of the structure or position, where:

[0038] Figure 1 is a schematic diagram of the bias circuit of a conventional two-stage switched capacitor amplifier;

[0039] Figure 2 It is the schematic diagram of the first-stage transconductance amplifier of a conventional two-stage switched capacitor amplifier;

[0040] Figure 3 It is the schematic diagram of the second-stage transconductance amplifier of the traditional two-stage switched capacitor amplifier;

[0041] Figure 4 The schematic diagram of the bias circuit of the switched capacitor amplifier proposed by the present invention;

[0042] Figure 5This is a schematic diagram of the first-stage transconductance amplifier of the switched capacitor amplifier proposed by the present invention;

[0043] Figure 6 This is a schematic diagram of the second-stage transconductance amplifier of the switched capacitor amplifier proposed by the present invention;

[0044] Figure 7 This is an equivalent schematic diagram of the bias circuit of the switched capacitor amplifier in the reset state proposed by the present invention;

[0045] Figure 8 This is an equivalent schematic diagram of the first-stage transconductance amplifier in the reset state of the switched capacitor amplifier proposed by the present invention;

[0046] Fig. 9 This is an equivalent schematic diagram of the second-stage transconductance amplifier in the reset state of the switched capacitor amplifier proposed by the present invention;

[0047] Fig.10 This is an equivalent schematic diagram of the bias circuit of the switched capacitor amplifier in the amplification state proposed by the present invention;

[0048] Fig.11 This is an equivalent schematic diagram of the first-stage transconductance amplifier in the amplification state of the switched capacitor amplifier proposed by the present invention;

[0049] Fig.12 This is an equivalent schematic diagram of the second-stage transconductance amplifier in the amplification state of the switched capacitor amplifier proposed by the present invention;

[0050] Fig.13 This is a comparison diagram of the current changes of the reset and amplification phase amplifiers of the switched capacitor amplifier proposed by the present invention. DETAILED DESCRIPTION

[0051] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various different configurations.

[0052] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for which protection is sought, but merely represents selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.

[0053] In the description of this application, it should be noted that the terms used, such as "top" and "bottom", refer to the part of this application that is close to the top when in use as the top, and the part that is close to the bottom as the bottom; the terms used, such as "first" and "second", are only used to distinguish expressions, and do not indicate or imply that they have a difference in importance or order; the terms used, such as "inside" and "outside", refer to the inside and outside of a specific contour. The use of the above terms is only to facilitate a clear and simple description of the technical solution of this application, and cannot be understood as a limitation on this application.

[0054] Embodiment 1:

[0055] The present invention discloses a switched capacitor amplifier, comprising a bias circuit, a first-stage transconductance amplifier and a second-stage transconductance amplifier, wherein:

[0056] like Figure 4 As shown, the bias circuit includes a constant current source IB, the constant current source IB is injected into the drain of the NMOS tube M0, the NMOS tube M0 is in a diode connection form, the gate of the NMOS tube M0 is connected to the gate of the NMOS tube M1, and the sources of the NMOS tubes M0 and M1 are both grounded; the drain of the NMOS tube M1 is connected to the drain of the PMOS tube M3, the source of the PMOS tube M3 is connected to the drain of the PMOS tube M4, the PMOS tubes M3 and M4 are both in a diode connection form, the source of the PMOS tube M4 is connected to the power supply vdd; the gate of the PMOS tube M5 is connected to the gate of the PMOS tube M4, the source of the PMOS tube M5 is connected to the power supply vdd, and the drain of the PMOS tube M5 is connected to the gate of the PMOS tube M4. The gate of the PMOS tube M6 is connected to the source of the PMOS tube M6, and the gate of the PMOS tube M6 is connected to the gate of the PMOS tube M3; the drain of the PMOS tube M6 is connected to the drain of the NMOS tube M2, the NMOS tube M2 is in the form of a diode connection, the source of the NMOS tube M2 is grounded, and the gate and drain bias voltages of the NMOS tube M2 are vn1; the gate of the NMOS tube M2 is connected to one end of the capacitor C4 through the switch k3, one end of the capacitor C3, and the switch k3n in sequence, and the other end of C3 is connected to the power supply vdd; the other end of the capacitor C4 is connected to one end of the switch k4 and the switch k4n at the same time, the other end of the switch k4n is connected to the power supply vdd, and the other end of the switch k4 is connected to the fixed bias voltage vn;

[0057] The invention also includes a PMOS tube M7, wherein the gate of the PMOS tube M7 is connected to the gate of the PMOS tube M6, the source of the PMOS tube M7 is connected to the drain of the PMOS tube M8, the source of the PMOS tube M8 is connected to the power supply vdd, the gate of the PMOS tube M8 is connected to the drain of the PMOS tube M7, the gate bias voltage of the PMOS tube M8 is vb1, the drain of the PMOS tube M7 is connected to the drain of the NMOS tube M47, the source of the NMOS tube M47 is grounded, and the gate of the NMOS tube M47 is connected to the gate of the NMOS tube M1; the gate of the PMOS tube M8 is connected to one end of the capacitor C2 through the switch k1, one end of the capacitor C1, and the switch k1n in sequence, and the other end of C1 is connected to the power supply vdd; the other end of the capacitor C2 is simultaneously connected to one end of the switch k2 and the switch k2n, the other end of the switch k2n is grounded, and the other end of the switch k2 is connected to the fixed bias voltage vb.

[0058] As an implementable solution:

[0059] like Figure 7 As shown, when the switched capacitor amplifier is in the reset phase, switches k1, k2, k3 and k4 are turned on, and switches k1n, k2n, k3n and k4n are turned off;

[0060] One end of capacitor C3 is charged to bias voltage vn1, and the other end is power supply voltage vdd. The other end of capacitor C4 is charged to bias voltage vn through turned-on switch k4, and one end is adjustable bias voltage vn2 of reset phase. Since vn2 is equal to vn1 in the previous state, vn2 is equal to vn1 at this time.

[0061] One end of capacitor C1 is charged to bias voltage vb1, and the other end is power supply voltage vdd. The other end of capacitor C2 is charged to bias voltage vb through the turned-on switch k2. Since vb2 is equal to vb1 in the previous state, at this time, the upper plate bias voltage vb2 is equal to vb1.

[0062] On the contrary, if Fig.10 As shown, when the switched capacitor amplifier is in the amplification phase, switches k1n, k2n, k3n and k4n are turned on, and switches k1, k2, k3 and k4 are turned off;

[0063] The other end of the capacitor C4 is charged to the power supply voltage vdd through the turned-on switch k4n. According to the charge conservation theorem, at this time vn2 = vn1 + C4 (vdd-vn) / (C3 + C4). Therefore, vn2 in the amplification phase is increased by C4 (vdd-vn) / (C3 + C4) compared with vn2 in the reset phase.

[0064] The other end of capacitor C2 is discharged to 0 through the turned-on switch k2n. According to the law of conservation of charge, at this time vb2=vb1-C2(vb2-vb) / (C1+C2). Therefore, vb2 in the amplification phase is lower than vb2 in the reset phase by C2(vb2-vb) / (C1+C2).

[0065] Furthermore, if Figure 5 The first-stage transconductance amplifier of the switched capacitor amplifier proposed in the present invention comprises an input stage of a first-stage transconductance amplifier composed of PMOS tubes M9, M10, M11, M12, M13, M14, M15 and M16, and a first-stage gain stage of a first-stage transconductance amplifier composed of NMOS tubes M17, M18, M19, M20, M21, M22, M31, M32, M33, M34, M35, M36, M37, M38, M48, M49, M50 and PMOS tubes M23, M24, M25, M26, M27, M28, M29, M30; wherein:

[0066] The PMOS tubes M9 and M10 are input differential pair tubes, and the gates of the PMOS tubes M9 and M10 are connected to the input signals VP and VM respectively; the PMOS tubes M11, M12, M13, M14, M15 and M16 are of common source and common gate structure; the gates of the PMOS tubes M11 and M12 are connected and connected to the fixed bias voltage vb, and the drains are connected and connected to the sources of the PMOS tubes M9 and M10; the gates of the PMOS tubes M13 and M15 are connected and connected to the fixed bias voltage vb1, and the drains of the PMOS tubes M13 and M14 are connected and connected to the source of the PMOS tube M12; the gates of the PMOS tubes M14 and M16 are connected and connected to the variable bias voltage vb2, and the drains of the PMOS tubes M15 and M16 are connected and connected to the source of the PMOS tube M11; the sources of the PMOS tubes M13, M14, M15 and M16 are all connected to the power supply voltage vdd;

[0067] The PMOS tubes M23, M24, M25, M26, M27, M28, M29 and M30 constitute a gain bootstrap structure in the first gain stage, and the NMOS tubes M17, M18, M19, M20, M21, M22, M31, M32, M33, M34, M35, M36, M37, M38, M48, M49 and M50 constitute a negative resistance structure in the first gain stage.

[0068] As an implementable solution:

[0069] The gain bootstrap structure is as follows: the PMOS tubes M29 and M23 form a common source and common gate structure, and the gate is connected to a fixed bias voltage vb1; the gate of the PMOS tube M24 is connected to a variable bias voltage vb2;

[0070] The drain of the PMOS tube M29 is simultaneously connected to the gate of the NMOS tube M21, the source of the NMOS tube M48, the common drain of the NMOS tubes M17 and M18, and the gate of the NMOS tube M35; the gate is simultaneously connected to the drain of the NMOS tube M21 and the drain of the PMOS tube M27; the source is simultaneously connected to the drain of the PMOS tube M23, the drain of the PMOS tube M24, and the gate of the PMOS tube M27; the sources of the PMOS tubes M23, M24, and M27 are all connected to the power supply voltage vdd; the source of the NMOS tube M21 is grounded;

[0071] The PMOS tubes M30 and M25 form a common source and common gate structure, and the gate is connected to a fixed bias voltage vb1; the gate of the PMOS tube M26 is connected to a variable bias voltage vb2;

[0072] The drain of the PMOS tube M30 is simultaneously connected to the gate of the NMOS tube M22, the drain of the NMOS tube M48, the common drain of the NMOS tubes M19 and M20, and the gate of the NMOS tube M34; the gate is simultaneously connected to the drain of the NMOS tube M22 and the drain of the PMOS tube M28; the source is simultaneously connected to the drain of the PMOS tube M25, the drain of the PMOS tube M26, and the gate of the PMOS tube M28; the sources of the PMOS tubes M25, M26, and M28 are all connected to the power supply voltage vdd; the source of the NMOS tube M22 is grounded.

[0073] The negative resistance structure is as follows: the NMOS tubes M17, M31, M32 and M33 form a common source and common gate structure, the gates are connected to a fixed bias voltage vn, the gate of the NMOS tube M32 is connected to a fixed bias voltage vn1, and the gate of the NMOS tube M33 is connected to a variable bias voltage vn2;

[0074] The source of the NMOS tube M17 is simultaneously connected to the source of the NMOS tube M18 and the drains of the NMOS tubes M31, M32, M33 and M34; the gate of the NMOS tube M18 is simultaneously connected to the gates of the NMOS tubes M48 and M19; the gate of the NMOS tube M31 is connected to the drain of the NMOS tube M49; the source of the NMOS tube M49 is connected to the gate of the NMOS tube M35, and the gate is connected to the switch K5n; the sources of the NMOS tubes M31, M32, M33 and M34 are all grounded;

[0075] The NMOS tubes M20, M36, M37 and M38 form a common source and common gate structure, the gates are connected to a fixed bias voltage vn, the gate of the NMOS tube M37 is connected to a fixed bias voltage vn1, and the gate of the NMOS M36 is connected to a variable bias voltage vn2;

[0076] The source of the NMOS tube M20 is simultaneously connected to the source of the NMOS tube M19, the drains of the NMOS tubes M35, M36, M37 and M38, the gate of the NMOS tube M38 is connected to the source of the NMOS tube M50, the drain of the NMOS tube M50 is connected to the gate of the NMOS tube M34, and the gate is connected to the switch K6n, and the sources of the NMOS tubes M35, M36, M37 and M38 are all grounded;

[0077] The common end of the NMOS tube M35 and the PMOS tube M29 serves as the first differential signal output end of the first stage transconductance amplifier, outputting the signal vo1; the common end of the NMOS tube M34 and the PMOS tube M30 serves as the second differential signal output end of the first stage transconductance amplifier, outputting the signal vo2.

[0078] Further explanation:

[0079] The first gain stage of the first switched capacitor amplifier is a fully differential structure, the bias voltages vn and vn1 are fixed bias voltages of the NMOS tube, the bias voltage vn2 is a variable bias voltage of the NMOS tube. The bias voltage vb1 is a fixed bias voltage of the PMOS tube, and the bias voltage vb2 is an adjustable bias voltage of the PMOS tube.

[0080] Taking a single side as an example, the PMOS tubes M29 and M23 form a common source and common gate structure, and the NMOS tubes M17, M31, M32 and M33 also form a common source and common gate structure to provide high gain for the first gain stage. M34 and M35 form a negative resistance structure to further improve the gain of the first gain stage.

[0081] The NMOS tubes M18, M19, M48, M49 and M50 are switch tubes. When the amplifier is in a reset state, the signals controlling switches k1, k2, k3 and k4 are high level, the switches are in an on state, and the signals controlling switches k1n, k2n, k3n, k4n, k5n and k6n are low level, the switches are in an off state; when the amplifier is in an amplifying state, the signals controlling switches k1n, k2n, k3n, k4n, k5n and k6n are high level, the switches are in an on state, and the signals controlling switches k1, k2, k3 and k4 are low level, the switches are in an off state;

[0082] It is further explained that switches k1n, k2n, k3n, k4n, k5n and k6n may be one or more switches in an actual circuit and need to be controlled by the same set of signals and turned on or off at the same time, and the same is true for switches k1, k2, k3 and k4.

[0083] The working principle of the first-stage transconductance amplifier of the switched capacitor amplifier proposed by the present invention is further described in different states:

[0084] like Figure 8 As shown, the first-stage transconductance amplifier of the switched capacitor amplifier proposed by the present invention is in the reset state. At this time, since vb2=vb1, vn2=vn1, if the sizes of the four PMOS tubes M13, M14, M15 and M16 are the same, the current flowing through them is also the same, which can be set to I1. Since the reset state has a lower requirement on the amplifier establishment time and the required bias current is small, the working state of the amplifier only needs to provide a bias voltage that meets the requirements. Therefore, by controlling the bias circuit, vb2 and vn2 can be set to vb1 and vn1 respectively, so that the amplifier works in a smaller bias current state in the reset state, saving the power consumption of the amplifier. At the same time, since the NMOS tubes M31 and M38 are in a diode connection state, the output impedance of the amplifier is small, and the offset storage of the first-stage gain stage can be realized, so that the first-stage gain stage of the amplifier will not exit the saturation region while storing the offset voltage. When the amplifier is in the amplification state, since the amplifier needs to be established quickly, the control signal k1 is low and k1 n is high;

[0085] like Fig.11 As shown, in the first stage transconductance amplifier of the switch capacitor amplifier proposed by the present invention, at this time, since vb2 = vb1-C2 (vb2-vb) / (C1+C2), vn2 = vn1+C4 (vdd-vn) / (C3+C4), vb2 decreases and vn2 increases. Fig.10 It can be seen that the current flowing through the PMOS tubes M14 and M15 increases by ΔI1, and the current flowing through the PMOS tubes M24 and M26 increases by ΔI2. By increasing the current, the first-stage gain stage of the amplifier is quickly established in the amplification phase. At the same time, since the first-stage gain stage is connected to the NMOS tubes M17 and M20 in this state, the output impedance of the gain stage is increased, thereby improving the amplification factor of the first-stage gain stage and suppressing the influence of the offset voltage on the amplifier gain stage.

[0086] like Figure 6 As shown, the second-stage transconductance amplifier of the switched capacitor amplifier proposed in the present invention includes a differential input pair of NMOS tubes M39 and M40, the sources of the NMOS tubes M39 and M40 are connected and connected to one end of the resistor R at the same time, the other end of the resistor R is grounded, and the gates of the NMOS tubes M39 and M40 are connected to the signal vo1 and the signal vo2 respectively;

[0087] The drains of the NMOS tubes M39 and M40 are connected to the drains of the PMOS tubes M42 and M43 respectively, the sources of the PMOS tubes M42 and M43 are connected to the drains of the PMOS tubes M44 and M45 respectively, the sources of the PMOS tubes M44 and M45 are connected to the power supply voltage vdd; the gates of the PMOS tubes M44 and M45 are connected to the fixed bias voltage vb1, and the gates of the PMOS tubes M42 and M43 are connected to the adjustable bias voltage vb2;

[0088] It also includes an NMOS tube M41, the drain of which is connected to the drain of the NMOS tube M39 and the drain of the PMOS tube M42 at the same time, and the common end is used as the first differential signal output end of the second-stage transconductance amplifier to output a signal vop; the source of the NMOS tube M41 is connected to the drain of the NMOS tube M40 and the drain of the PMOS tube M43 at the same time, and the common end is used as the second differential signal output end of the second-stage transconductance amplifier to output a signal vom, and the gate of the NMOS tube M41 is connected to a switch K5, and the switch K5 and switches k1, k2, k3 and k4 are all controlled by the same signal.

[0089] The working principle of the second-stage transconductance amplifier of the switched capacitor amplifier proposed by the present invention is further described in different states:

[0090] like Fig. 9 As shown, the second-stage transconductance amplifier of the switched capacitor amplifier proposed in the present invention in the reset state:

[0091] When the amplifier is in the reset state, since the amplifier needs to quickly establish, at this time, since vb2=vb1, the current flowing through the PMOS tubes M44 and M45 is set to I3. Since the reset state has a lower requirement on the amplifier establishment time, the required bias current is small, and the working state of the amplifier only needs to provide a bias voltage that meets the requirements, so that the second gain stage of the amplifier operates in a smaller bias current state in the reset state, saving the power consumption of the amplifier.

[0092] like Fig.12 As shown, the second-stage transconductance amplifier in the amplifying state of the switched capacitor amplifier proposed by the present invention is:

[0093] When the amplifier is in the amplification state, since the amplifier needs to quickly establish, in the amplification state, vb2=vb1-C2(vb2-vb) / (C1+C2), thereby vb2 is reduced, and the current flowing through the PMOS tubes M44 and M45 increases by ΔI3. By increasing the current, the second stage of the amplifier can be quickly established in the amplification phase.

[0094] As an implementable solution, the amplifier proposed in the present invention is designed using 180nm CMOS technology. When the amplifier operates at 125MHz, ΔI1 / I1=5, ΔI2 / I2=8, ΔI3 / I3=4. The comparison of the current changes of the switched capacitor amplifier reset and amplification phase amplifier proposed in the present invention is shown in the figure below. Fig.13 As shown. From the above current change ratio, it can be seen that the current of the amplifier working in the reset phase is only 1 / 6 of the current of the amplifier working in the amplification phase. Compared with the traditional structure, the current of the amplifier working in the reset phase is different from the current of the amplification phase. The present invention reduces the power consumption of the amplifier by about 40%. At the same time, since the amplifier proposed in the present invention can provide a smaller gain in the reset phase to achieve offset storage, and provide a larger gain in the amplification phase to amplify the signal. Therefore, compared with the traditional structure, the amplifier proposed in the present invention can effectively suppress the offset voltage and improve the accuracy of the amplifier.

[0095] Finally, it should be understood that the embodiments described in this specification are only used to illustrate the principles of the embodiments of this specification. Other variations may also fall within the scope of this specification. Therefore, as an example and not a limitation, alternative configurations of the embodiments of this specification may be considered consistent with the teachings of this specification. Accordingly, the embodiments of this specification are not limited to the embodiments explicitly introduced and described in this specification.

Claims

1. A switched capacitor amplifier, characterized in that: The invention comprises a bias circuit, a first-stage transconductance amplifier and a second-stage transconductance amplifier, wherein: The bias circuit includes a constant current source IB, which is injected into the drain of the NMOS tube M0. The NMOS tube M0 is in a diode connection form. The gate of the NMOS tube M0 is connected to the gate of the NMOS tube M1, and the sources of the NMOS tubes M0 and M1 are both grounded; the drain of the NMOS tube M1 is connected to the drain of the PMOS tube M3, the source of the PMOS tube M3 is connected to the drain of the PMOS tube M4, the PMOS tubes M3 and M4 are both in a diode connection form, and the source of the PMOS tube M4 is connected to the power supply vdd; the gate of the PMOS tube M5 is connected to the gate of the PMOS tube M4, the source of the PMOS tube M5 is connected to the power supply vdd, and the drain of the PMOS tube M5 is connected to the gate of the PMOS tube M4. The source of the PMOS tube M6 is connected, and the gate of the PMOS tube M6 is connected to the gate of the PMOS tube M3; the drain of the PMOS tube M6 is connected to the drain of the NMOS tube M2, the NMOS tube M2 is in the form of a diode connection, the source of the NMOS tube M2 is grounded, and the gate and drain bias voltages of the NMOS tube M2 are vn1; the gate of the NMOS tube M2 is connected to one end of the capacitor C4 through the switch k3, one end of the capacitor C3, and the switch k3n in sequence, and the other end of C3 is connected to the power supply vdd; the other end of the capacitor C4 is connected to one end of the switch k4 and the switch k4n at the same time, the other end of the switch k4n is connected to the power supply vdd, and the other end of the switch k4 is connected to the fixed bias voltage vn; The invention also includes a PMOS tube M7, wherein the gate of the PMOS tube M7 is connected to the gate of the PMOS tube M6, the source of the PMOS tube M7 is connected to the drain of the PMOS tube M8, the source of the PMOS tube M8 is connected to the power supply vdd, the gate of the PMOS tube M8 is connected to the drain of the PMOS tube M7, the gate bias voltage of the PMOS tube M8 is vb1, the drain of the PMOS tube M7 is connected to the drain of the NMOS tube M47, the source of the NMOS tube M47 is grounded, and the gate of the NMOS tube M47 is connected to the gate of the NMOS tube M1; the gate of the PMOS tube M8 is connected to one end of the capacitor C2 through the switch k1, one end of the capacitor C1, and the switch k1n in sequence, and the other end of C1 is connected to the power supply vdd; the other end of the capacitor C2 is simultaneously connected to one end of the switch k2 and the switch k2n, the other end of the switch k2n is grounded, and the other end of the switch k2 is connected to the fixed bias voltage vb.

2. A switched capacitor amplifier as claimed in claim 1, characterized in that: When the switched capacitor amplifier is in the reset phase, switches k1, k2, k3 and k4 are turned on, and switches k1n, k2n, k3n and k4n are turned off; One end of capacitor C3 is charged to bias voltage vn1, and the other end is power supply voltage vdd. The other end of capacitor C4 is charged to bias voltage vn through turned-on switch k4, and one end is adjustable bias voltage vn2 of reset phase. Since vn2 is equal to vn1 in the previous state, vn2 is equal to vn1 at this time. One end of capacitor C1 is charged to bias voltage vb1, and the other end is power supply voltage vdd. The other end of capacitor C2 is charged to bias voltage vb through the turned-on switch k2. Since vb2 is equal to vb1 in the previous state, at this time, the upper plate bias voltage vb2 is equal to vb1.

3. A switched capacitor amplifier as claimed in claim 1, characterized in that: When the switched capacitor amplifier is in the amplification phase, switches k1n, k2n, k3n and k4n are turned on, and switches k1, k2, k3 and k4 are turned off; The other end of the capacitor C4 is charged to the power supply voltage vdd through the turned-on switch k4n. According to the charge conservation theorem, at this time vn2 = vn1 + C4 (vdd-vn) / (C3 + C4). Therefore, vn2 in the amplification phase is increased by C4 (vdd-vn) / (C3 + C4) compared with vn2 in the reset phase. The other end of capacitor C2 is discharged to 0 through the turned-on switch k2n. According to the law of conservation of charge, at this time vb2=vb1-C2(vb2-vb) / (C1+C2). Therefore, vb2 in the amplification phase is lower than vb2 in the reset phase by C2(vb2-vb) / (C1+C2).

4. A switched capacitor amplifier as claimed in claim 1, characterized in that: The first-stage transconductance amplifier comprises an input stage of the first-stage transconductance amplifier composed of PMOS tubes M9, M10, M11, M12, M13, M14, M15 and M16, and a first-stage gain stage of the first-stage transconductance amplifier composed of NMOS tubes M17, M18, M19, M20, M21, M22, M31, M32, M33, M34, M35, M36, M37, M38, M48, M49, M50 and PMOS tubes M23, M24, M25, M26, M27, M28, M29, M30; wherein: The PMOS tubes M9 and M10 are input differential pair tubes, and the gates of the PMOS tubes M9 and M10 are connected to the input signals VP and VM respectively; the PMOS tubes M11, M12, M13, M14, M15 and M16 are of common source and common gate structure; the gates of the PMOS tubes M11 and M12 are connected and connected to the fixed bias voltage vb, and the drains are connected and connected to the sources of the PMOS tubes M9 and M10; the gates of the PMOS tubes M13 and M15 are connected and connected to the fixed bias voltage vb1, and the drains of the PMOS tubes M13 and M14 are connected and connected to the source of the PMOS tube M12; the gates of the PMOS tubes M14 and M16 are connected and connected to the variable bias voltage vb2, and the drains of the PMOS tubes M15 and M16 are connected and connected to the source of the PMOS tube M11; the sources of the PMOS tubes M13, M14, M15 and M16 are all connected to the power supply voltage vdd; The PMOS tubes M23, M24, M25, M26, M27, M28, M29 and M30 constitute a gain bootstrap structure in the first gain stage, and the NMOS tubes M17, M18, M19, M20, M21, M22, M31, M32, M33, M34, M35, M36, M37, M38, M48, M49 and M50 constitute a negative resistance structure in the first gain stage.

5. A switched capacitor amplifier as claimed in claim 4, characterized in that: The gain bootstrap structure is as follows: the PMOS tubes M29 and M23 form a common source and common gate structure, and the gate is connected to a fixed bias voltage vb1; the gate of the PMOS tube M24 is connected to a variable bias voltage vb2; The drain of the PMOS tube M29 is simultaneously connected to the gate of the NMOS tube M21, the source of the NMOS tube M48, the common drain of the NMOS tubes M17 and M18, and the gate of the NMOS tube M35; the gate is simultaneously connected to the drain of the NMOS tube M21 and the drain of the PMOS tube M27; the source is simultaneously connected to the drain of the PMOS tube M23, the drain of the PMOS tube M24, and the gate of the PMOS tube M27; the sources of the PMOS tubes M23, M24, and M27 are all connected to the power supply voltage vdd; the source of the NMOS tube M21 is grounded; The PMOS tubes M30 and M25 form a common source and common gate structure, and the gate is connected to a fixed bias voltage vb1; the gate of the PMOS tube M26 is connected to a variable bias voltage vb2; The drain of the PMOS tube M30 is simultaneously connected to the gate of the NMOS tube M22, the drain of the NMOS tube M48, the common drain of the NMOS tubes M19 and M20, and the gate of the NMOS tube M34; the gate is simultaneously connected to the drain of the NMOS tube M22 and the drain of the PMOS tube M28; the source is simultaneously connected to the drain of the PMOS tube M25, the drain of the PMOS tube M26, and the gate of the PMOS tube M28; the sources of the PMOS tubes M25, M26, and M28 are all connected to the power supply voltage vdd; the source of the NMOS tube M22 is grounded.

6. A switched capacitor amplifier as claimed in claim 4, characterized in that: The negative resistance structure is as follows: the NMOS tubes M17, M31, M32 and M33 form a common source and common gate structure, the gates are connected to a fixed bias voltage vn, the gate of the NMOS tube M32 is connected to a fixed bias voltage vn1, and the gate of the NMOS tube M33 is connected to a variable bias voltage vn2; The source of the NMOS tube M17 is simultaneously connected to the source of the NMOS tube M18 and the drains of the NMOS tubes M31, M32, M33 and M34; the gate of the NMOS tube M18 is simultaneously connected to the gates of the NMOS tubes M48 and M19; the gate of the NMOS tube M31 is connected to the drain of the NMOS tube M49; the source of the NMOS tube M49 is connected to the gate of the NMOS tube M35, and the gate is connected to the switch K5n; the sources of the NMOS tubes M31, M32, M33 and M34 are all grounded; The NMOS tubes M20, M36, M37 and M38 form a common source and common gate structure, the gates are connected to a fixed bias voltage vn, the gate of the NMOS tube M37 is connected to a fixed bias voltage vn1, and the gate of the NMOS M36 is connected to a variable bias voltage vn2; The source of the NMOS tube M20 is simultaneously connected to the source of the NMOS tube M19, the drains of the NMOS tubes M35, M36, M37 and M38, the gate of the NMOS tube M38 is connected to the source of the NMOS tube M50, the drain of the NMOS tube M50 is connected to the gate of the NMOS tube M34, and the gate is connected to the switch K6n, and the sources of the NMOS tubes M35, M36, M37 and M38 are all grounded; The common end of the NMOS tube M35 and the PMOS tube M29 serves as the first differential signal output end of the first stage transconductance amplifier, outputting the signal vo1; the common end of the NMOS tube M34 and the PMOS tube M30 serves as the second differential signal output end of the first stage transconductance amplifier, outputting the signal vo2.

7. A switched capacitor amplifier as claimed in claim 1, characterized in that: The second-stage transconductance amplifier includes a differential input pair of NMOS tubes M39 and M40, wherein the sources of the NMOS tubes M39 and M40 are connected to each other and are simultaneously connected to one end of a resistor R, the other end of the resistor R is grounded, and the gates of the NMOS tubes M39 and M40 are respectively connected to a signal vo1 and a signal vo2; The drains of the NMOS tubes M39 and M40 are connected to the drains of the PMOS tubes M42 and M43 respectively, the sources of the PMOS tubes M42 and M43 are connected to the drains of the PMOS tubes M44 and M45 respectively, the sources of the PMOS tubes M44 and M45 are connected to the power supply voltage vdd; the gates of the PMOS tubes M44 and M45 are connected to the fixed bias voltage vb1, and the gates of the PMOS tubes M42 and M43 are connected to the adjustable bias voltage vb2; It also includes an NMOS tube M41, the drain of which is connected to the drain of the NMOS tube M39 and the drain of the PMOS tube M42 at the same time, and the common end is used as the first differential signal output end of the second-stage transconductance amplifier to output the signal vop; the source of the NMOS tube M41 is connected to the drain of the NMOS tube M40 and the drain of the PMOS tube M43 at the same time, and the common end is used as the second differential signal output end of the second-stage transconductance amplifier to output the signal vom.

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