Dual-frequency driving device for pulse high-frequency ionization device

Abstract

The invention discloses a double-frequency driving device for a pulse high-frequency ionization device, the double-frequency driving device is used for providing a to-be-amplified double-frequency signal for a third-party adjustable double-frequency vector impedance matching device, and the to-be-amplified double-frequency signal endowes double-frequency frequency, amplitude and time delay characteristics; a dual-frequency frequency control signal, a dual-frequency amplitude control signal, a sine / cosine signal and a modulated signal of the dual-frequency driving device are digital signals with a certain bit width; according to the invention, the dual-frequency driving device is combined with the third-party power amplifier and the adjustable dual-frequency vector impedance matching device, and one frequency of the dual-frequency driving device is used for realizing high-yield plasma at a load end; and the other frequency of the double-frequency driving device is used for realizing a cold start ignition function of a load end and a plasma continuation maintaining function, so that the problem that a single-frequency pulse high-frequency ionization method cannot simultaneously consider the specific frequency power requirement and the cold start ignition and ignition maintaining stage power requirement of the pulse high-frequency ionization device is solved.

Description

Technical Field

[0001] The invention belongs to the technical field of high-frequency plasma and high-frequency power transmission, and in particular relates to a dual-frequency driving device for a pulse high-frequency ionization device. Background Art

[0002] High-frequency plasma ionization devices are widely used in the fields of semiconductor industry, material science research, charged particle accelerators and controlled nuclear fusion neutral beam injection. Among them, pulsed high-frequency ionization devices are particularly suitable for scenarios where high-intensity pulse beams need to be generated, and can provide instantaneous extraction currents far exceeding those of continuous ionization devices.

[0003] However, since a pulse high-frequency ionization method with a single frequency is usually used when the pulse high-frequency ionization device is in operation, the problem with the pulse high-frequency ionization with a single frequency is that the plasma required by the user is often a plasma generated at a specific frequency, and the plasma generated at a specific frequency requires power at a specific frequency. However, the power at this specific frequency does not meet the power required for the cold start ignition stage and the cold start ignition maintenance stage of the pulse high-frequency ionization device. On the contrary, if the power required for the cold start ignition stage and the cold start ignition maintenance stage of the pulse high-frequency ionization device is met, it is definitely not the power at the specific frequency required by the user. In order to meet the user's demand for specific frequency plasma, the pulse high-frequency ionization device must find additional ways to add devices for cold start ignition and cold start ignition maintenance, but this will lead to a complex structure and complex debugging of the pulse high-frequency ionization device. Summary of the invention

[0004] In order to solve the problems existing in the prior art, the present invention proposes a dual-frequency driving device for a pulse high-frequency ionization device, aiming to solve the problem that a single-frequency pulse high-frequency ionization method cannot simultaneously take into account the power demand of a specific frequency and the power demand of the cold start ignition and ignition maintenance stages of the pulse high-frequency ionization device.

[0005] The present invention proposes the following technical solutions to solve the technical problems:

[0006] A dual-frequency driving device for a pulsed high-frequency ionization device, the dual-frequency driving device is used to provide a dual-frequency signal to be amplified for a third-party low-power high-frequency power source and a high-power high-frequency power source, the third-party low-power high-frequency power source generates high-frequency low power for load cold start ignition and load maintenance plasma state, and feeds the high-frequency low-power pulse to the load through a third-party impedance matching device to ionize and generate plasma material in a cold start ignition state, and ionize and generate plasma material to maintain the plasma state; the third-party high-power high-frequency power source generates low-frequency high power for high-yield plasma, and feeds the low-frequency high-power pulse to the load through a third-party impedance matching device to ionize and generate a large amount of plasma material that can be drawn out;

[0007] The dual-frequency signal to be amplified has inherent dual-frequency frequency, amplitude and time delay characteristics; the dual-frequency driving device is provided with, from one side to the other side, a dual-frequency signal controller (10), a dual-frequency sine / cosine digital waveform generator (20), a high-frequency and high-frequency digital carrier modulation path (30) and a low-frequency and high-frequency digital carrier modulation path (31), and a dual-high-frequency digital-to-analog conversion output driving module (40);

[0008] The dual-frequency signal controller (10) is used to generate a dual-frequency frequency control signal and a dual-frequency amplitude control signal with an intrinsic dual-frequency delay control characteristic, and send the dual-frequency frequency control signal to a dual-frequency sine / cosine digital waveform generator (20), and send the dual-frequency amplitude control signal with an intrinsic delay characteristic to a high-frequency high-frequency digital carrier modulation path (30) and a low-frequency high-frequency digital carrier modulation path (31).

[0009] The dual-frequency sine / cosine digital waveform generator (20) is used to convert the received dual-frequency frequency control signal into a sine / cosine signal and send it to a high-frequency high-frequency digital carrier modulation path (30) and a low-frequency high-frequency digital carrier modulation path (31) respectively;

[0010] The high-frequency and high-frequency digital carrier modulation path (30) is used to multiply the received sine / cosine signal by the received dual-frequency amplitude control signal with an intrinsic dual-frequency delay control characteristic, thereby realizing modulation of the high-frequency and high-frequency digital carrier signal;

[0011] The low-frequency and high-frequency digital carrier modulation path (31) is used to multiply the received sine / cosine signal by the received dual-frequency amplitude control signal with an intrinsic dual-frequency delay control characteristic, thereby realizing modulation of the low-frequency and high-frequency digital carrier signal;

[0012] The dual high-frequency digital-analog conversion output drive module (40) is used to perform digital-analog conversion on a modulated high-frequency high-frequency digital carrier signal and a modulated low-frequency high-frequency digital carrier signal, and send the continuously output high-frequency drive signal after digital-analog conversion to a third-party low-power high-frequency power source; send the pulse output high-frequency drive signal after digital-analog conversion to a third-party low-power high-frequency power source; send the pulse output low-frequency drive signal after digital-analog conversion to a third-party high-power high-frequency power source;

[0013] Features:

[0014] The frequency signal sent by the dual-frequency signal controller (10) to the dual-frequency sine / cosine digital waveform generator (20) and the dual-frequency amplitude control signal with an intrinsic dual-frequency delay control feature sent to the high-frequency and high-frequency digital carrier modulation path (30) and the low-frequency and high-frequency digital carrier modulation path (31) are both digital signals with a certain bit width;

[0015] The sine / cosine signals sent by the dual-frequency sine / cosine digital waveform generator (20) to the high-frequency and high-frequency digital carrier modulation path (30) and to the low-frequency and high-frequency digital carrier modulation path (31) are both digital signals with a certain bit width;

[0016] The modulated signal sent by the high-frequency high-frequency digital carrier modulation path (30) to the dual high-frequency digital-analog conversion output drive module (40) and the modulated signal sent by the low-frequency high-frequency digital carrier modulation path (31) to the dual high-frequency digital-analog conversion output drive module (40) are both digital signals with a certain bit width;

[0017] The digital signal with a certain bit width means that the bit width cannot be too wide or too narrow. The bit width cannot be too wide means that the memory resources and register resources are occupied as little as possible under the premise of meeting the design requirements. The bit width cannot be too narrow means that the signal strength cannot be reduced in order to save memory resources and register resources. This is a basic design requirement.

[0018] The continuously output high-frequency driving signal contains frequency and amplitude characteristics for a cold start state;

[0019] The high-frequency driving signal output by the pulse contains frequency, amplitude and time delay characteristics for maintaining the plasma state;

[0020] The low-frequency driving signal of the pulse output contains frequency, amplitude and time delay characteristics for generating high-yield plasma pulses.

[0021] Furthermore, the frequency signal sent by the dual-frequency signal controller (10) to the dual-frequency sine / cosine digital waveform generator (20) is a digital signal with a certain bit width, and the frequency signal is: a high-frequency high-frequency control signal (FREQ10) and a low-frequency high-frequency control signal (FREQ11); the digital signal with a certain bit width means that: their bit width distribution should be higher than:

[0022] FREQ10 bit width lower limit = [log2 (DWAV20 frequency ÷ DWAV20 frequency tolerance)] (1);

[0023] FREQ11 bit width lower limit = [log2 (DWAV21 frequency ÷ DWAV21 frequency tolerance)] (2).

[0024] Furthermore, for the digital high-frequency high-frequency sine / cosine waveform signal (DWAV20) to be set, the frequency f DWAV20 and the digital clock frequency f required for the operation of the dual-frequency sine / cosine digital waveform generator (20) clk , the high frequency high frequency control signal (FREQ10) should satisfy:

[0025] FREQ10=[f DWAV20 ÷f clk ×2^FREQ10 bit width] (3);

[0026] Similarly, for the digital low-frequency high-frequency sine / cosine waveform signal (DWAV21) to be set, the frequency f DWAV21 , the low-frequency and high-frequency control signal (FREQ11) should satisfy:

[0027] FREQ11=[f DWAV21 ÷f clk ×2^FREQ11 bit width] (4);

[0028] The FREQ10 bit width of the above formula (3) and the FREQ11 bit width of the above formula (4) are bit widths determined according to the FREQ10 bit width lower limit of the above formula (1) and the FREQ11 bit width lower limit of the above formula (2).

[0029] Furthermore, the amplitude signals sent by the dual-frequency signal controller (10) to the high-frequency and high-frequency digital carrier modulation path (30) and the low-frequency and high-frequency digital carrier modulation path (31) are both digital signals with a certain bit width, and the amplitude signals are: the high-frequency and high-frequency path modulation signal (AMPL12) and the low-frequency and high-frequency path modulation signal (AMPL13). The digital signals with a certain bit width mean that their bit widths should be higher than:

[0030] AMPL12 bit width lower limit = [log2(AMPL12 amplitude ÷AMPL12 amplitude tolerance)] (5);

[0031] AMPL13 bit width lower limit = [log2 (AMPL13 amplitude ÷ AMPL13 amplitude tolerance)] (6).

[0032] Furthermore, the modulated signal sent by the high-frequency and high-frequency digital carrier modulation path (30) to the dual high-frequency digital-to-analog conversion output driving module (40) and the modulated signal sent by the low-frequency and high-frequency digital carrier modulation path (31) to the dual high-frequency digital-to-analog conversion output driving module (40) are both digital signals with a certain bit width; the modulated signals are digital high-frequency and high-frequency modulated signals (DMOD30) and digital low-frequency and high-frequency modulated signals (DMOD31), and the digital signals with a certain bit width refer to digital signals whose bit widths satisfy:

[0033] DMOD30 bit width = DWAV20 bit width + AMPL12 bit width (7);

[0034] DMOD31 bit width = DWAV21 bit width + AMPL13 bit width (8);

[0035] The AMPL12 bit width of the above formula (7) and the AMPL13 bit width of the above formula (8) are bit widths determined according to the lower limit of the AMPL12 bit width of the above formula (5) and the lower limit of the AMPL13 bit width of the above formula (6).

[0036] Furthermore, the continuously output high-frequency driving signal contains frequency and amplitude characteristics for the cold start state, specifically:

[0037] The frequency is preferably a frequency with the highest plasma ignition success rate or the shortest ignition time within the working bandwidth of the low-power high-frequency power source, and any frequency within the working bandwidth of the low-power high-frequency power source that can achieve a cold start ignition function can also be selected;

[0038] The amplitude is preferably sufficient to drive the low-power high-frequency power source to output the high-frequency cold-start ignition power, and to achieve the driving signal amplitude corresponding to the minimum power of the plasma cold-start ignition function plus a sufficient margin through a third-party matching device; or preferably, the driving signal amplitude corresponding to the maximum output power that the low-power high-frequency power source can tolerate under instantaneous total reflection; or any value in between.

[0039] Furthermore, the high-frequency driving signal of the pulse output contains frequency, amplitude, and time delay characteristics for maintaining the plasma state, and its frequency, amplitude, and time delay characteristics are specifically:

[0040] The frequency is preferably a frequency consistent with the cold start state, or a frequency that can maintain the plasma state within the working bandwidth of the low-power high-frequency power source and can minimize the high-frequency standing wave ratio;

[0041] This amplitude forms a counter pulse complementary to the high-yield plasma pulse amplitude in each repetition cycle, and has a high duty cycle; the peak-to-peak value of the amplitude corresponds to the peak-to-peak value of the driving signal when the low-power high-frequency power source outputs full power; the low-power high-frequency power source is driven by the high-frequency driving signal output by the pulse.

[0042] The delay feature is 0 delay;

[0043] The plasma-maintaining state refers to the plasma-maintaining state generated by the cold start state, or the plasma-maintaining state remaining after the high-yield plasma pulse generation state ends.

[0044] Furthermore, the low-frequency driving signal of the pulse output contains frequency, amplitude, and delay characteristics for generating high-yield plasma pulses, specifically:

[0045] The frequency is optimized and adjusted according to the user's requirements for the specific working gas and plasma temperature, electron temperature, electron density and other properties of the pulsed high-frequency ionization device;

[0046] The amplitude is a short pulse with the same repetition period as the amplitude characteristic of maintaining the plasma existence state, and has a low duty cycle; the peak-to-peak value of the amplitude corresponds to the peak-to-peak value of the driving signal when the high-power high-frequency power source outputs full power; the high-power high-frequency power source is driven by the high-frequency driving signal output by the pulse.

[0047] The time delay is preferably the pulse width of the plasma-sustaining state, so as to achieve alternating appearance of short pulses of the high-yield plasma state and wide pulses of the plasma-sustaining state.

[0048] Advantages and effects of the present invention

[0049] 1. By combining a dual-frequency driving device with a third-party power amplifier + adjustable dual-frequency vector impedance matching device, one frequency of the dual-frequency driving device is used to match the impedance of the load end in the pulse state, thereby providing the load with high-frequency, low-power pulses and realizing high-yield plasma at the load end; and the other frequency of the dual-frequency driving device is used to match the impedance under the pulse gap at the load end, thereby providing the load with low-frequency, high-power pulses and realizing the cold start ignition function and plasma maintenance function at the load end, thereby solving the problem that a single-frequency pulse high-frequency ionization method cannot simultaneously take into account the power requirements of a specific frequency and the power requirements of the cold start ignition and ignition maintenance stages of the pulse high-frequency ionization device.

[0050] 2. By setting the dual-frequency frequency control signal, dual-frequency amplitude control signal, sine / cosine signal, and modulated signal to digital signals with a certain bit width, the occupation of storage resources of the FPGA chip by the dual-frequency signal controller 10, the dual-frequency sine / cosine digital waveform generator 20, the high-frequency high-frequency digital carrier modulation path 30, and the low-frequency high-frequency digital carrier modulation path 31 is limited to the greatest extent, thereby reducing the cost of the dual-frequency driving device for a pulsed high-frequency ionization device proposed in the present invention.

[0051] 3. The problem of consistency of the two sets of pulse steps is solved by making the continuous output high-frequency drive signal contain the frequency and amplitude characteristics for the cold start state; the pulse output high-frequency drive signal contain the frequency, amplitude, and delay characteristics for maintaining the plasma state; and the pulse output low-frequency drive signal contain the frequency, amplitude, and delay characteristics for high-yield plasma pulse generation. When the pulse high-frequency ionization device needs to generate plasma with high yield, the power received by the load is the power of the pulse stage, and when the pulse high-frequency ionization device needs cold start ignition or maintain the plasma state, the load receives the power of the pulse interval stage. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] Figure 1 This is an application effect diagram of the driving device of the present invention;

[0053] Figure 2 This is a structural diagram of a dual-frequency driving device for a pulse high-frequency ionization device according to the present invention; DETAILED DESCRIPTION

[0054] The present invention will be further explained below in conjunction with the accompanying drawings.

[0055] 1. Innovation of the present invention: The innovation is to use a dual-frequency driving device to replace the single-frequency driving device of the prior art, and then use a dual-frequency pulse high-frequency ionization device to replace the single-frequency pulse high-frequency ionization device (pulse high-frequency ionization device = driving device + power amplifier + matching device + load). The advantage of the dual-frequency driving device of the present invention is that by combining the driving device of the present invention with a third-party power amplifier + matching device, one frequency is used to match the impedance of the load end in the pulse state, thereby providing a high-frequency low-power pulse to the load, and another frequency is used to match the impedance of the load end in the pulse gap, thereby providing a low-frequency high-power pulse to the load, thereby solving the problem that the single-frequency pulse high-frequency ionization method cannot simultaneously take into account the power requirements of a specific frequency and the power requirements of the pulse high-frequency ionization device in the cold start ignition and ignition maintenance stages.

[0056] 2. Difficulties in the design of the present invention: One of the difficulties is how to ensure the consistency of the pace of the two groups of pulses. The two groups of pulses are high-frequency low-power pulses and low-frequency high-power pulses output from a low-power high-frequency power source and a high-power high-frequency power source. The consistency of the pace means that when the pulse high-frequency ionization device needs to produce plasma with a high yield, the power received by the load is the power of the pulse stage. When the pulse high-frequency ionization device needs to maintain the existence of plasma, the load receives the power of the pulse interval stage. The second difficulty is to save hardware resources to the maximum extent. After changing from a single-frequency drive to a dual-frequency drive, the number of registers and memories has doubled, and the resources of an FPGA are limited. When the resources of an FPGA are not enough, multiple FPGAs need to be used, and the communication between multiple FPGAs needs to be increased. This greatly increases the workload of design and debugging.

[0057] 3. Solution of the present invention: Solution to the first difficulty: The dual-frequency signal (RFOUT40 and RFOUT41) to be amplified by the present invention has inherent dual-frequency frequency, amplitude and delay characteristics, wherein the role of the delay characteristic is to adjust the early and late arrival of the pulse, the early means the delay time is short or 0, and the late means the delay time is long, thereby ensuring that the high-frequency low-power pulse and the low-frequency high-power pulse are in step with each other. Solution to the second difficulty: limit the bit width of the dual-frequency frequency control signal, the dual-frequency amplitude control signal, the sine / cosine signal, and the modulated signal. If the bit width is too wide, the number of memories and registers occupied will be large. The present invention sets the bit width to the minimum under the condition of ensuring the signal strength, which is just enough. Thereby saving the resources of FPGA.

[0058] A dual-frequency driving device for a pulse high-frequency ionization device Figure 1 , Figure 2 As shown, the dual-frequency driving device is used to provide dual-frequency signals to be amplified for the low-power high-frequency power source and the high-power high-frequency power source of the third party. The low-power high-frequency power source of the third party generates high-frequency low power for load cold start ignition and load maintenance of plasma state, and feeds the high-frequency low-power pulse to the load through the third-party impedance matching device to ionize and generate plasma materials in the cold start ignition state, and ionize and generate plasma materials to maintain the plasma state; the high-power high-frequency power source of the third party generates low-frequency high power for high-yield plasma, and feeds the low-frequency high-power pulse to the load through the third-party impedance matching device to ionize and generate a large amount of plasma materials that can be drawn out;

[0059] The dual-frequency signal to be amplified has inherent dual-frequency frequency, amplitude and time delay characteristics; the dual-frequency driving device is provided with, from one side to the other side, a dual-frequency signal controller (10), a dual-frequency sine / cosine digital waveform generator (20), a high-frequency and high-frequency digital carrier modulation path (30) and a low-frequency and high-frequency digital carrier modulation path (31), and a dual-high-frequency digital-to-analog conversion output driving module (40);

[0060] Supplementary Note 1:

[0061] 1) Figure 1 The left dotted line box is the driving device of the present invention, and the middle and right dotted line boxes are third-party power amplifiers and third-party adjustable vector impedance matching devices;

[0062] 2) The driving device of the present invention outputs a dual-frequency driving signal to be amplified to the third-party power amplifier, and outputs a power signal from the third-party power amplifier; the third-party power amplifier is a high-frequency high-power source and a low-frequency high-power source.

[0063] The dual-frequency signal controller (10) is used to generate a dual-frequency frequency control signal and a dual-frequency amplitude control signal with an intrinsic dual-frequency delay control characteristic, and send the dual-frequency frequency control signal to a dual-frequency sine / cosine digital waveform generator (20), and send the dual-frequency amplitude control signal with an intrinsic delay characteristic to a high-frequency high-frequency digital carrier modulation path (30) and a low-frequency high-frequency digital carrier modulation path (31).

[0064] Supplementary Note 2:

[0065] 1) The low-frequency high-frequency power source is usually set to a high-power narrow pulse, which is used to promote the violent ionization of the plasma in a short time and produce a large amount of plasma material that can be extracted;

[0066] 2) The high-frequency high-frequency power source is usually set to the reverse pulse of the high-frequency high-frequency power, that is, the wide pulse from the falling edge of the high-frequency high-frequency power pulse to the rising edge of the next high-frequency high-frequency power pulse, which is used to maintain the continuous generation and existence of plasma materials with a certain density and temperature inside the pulse high-frequency ionization device;

[0067] 3) The third party's high-frequency high-frequency power source can also be set to a continuous wave mode to ionize the working fluid in the device and generate plasma material when the external conditions of the pulse high-frequency ionization device are ready and the device itself is in a standby state.

[0068] The dual-frequency sine / cosine digital waveform generator (20) is used to convert the received dual-frequency frequency control signal into a sine / cosine signal and send it to a high-frequency high-frequency digital carrier modulation path (30) and a low-frequency high-frequency digital carrier modulation path (31) respectively;

[0069] The high-frequency and high-frequency digital carrier modulation path (30) is used to multiply the received sine / cosine signal by the received dual-frequency amplitude control signal with an intrinsic dual-frequency delay control characteristic, thereby realizing modulation of the high-frequency and high-frequency digital carrier signal;

[0070] The low-frequency and high-frequency digital carrier modulation path (31) is used to multiply the received sine / cosine signal by the received dual-frequency amplitude control signal with an intrinsic dual-frequency delay control characteristic, thereby realizing modulation of the low-frequency and high-frequency digital carrier signal;

[0071] The dual high-frequency digital-analog conversion output drive module (40) is used to perform digital-analog conversion on a modulated high-frequency high-frequency digital carrier signal and a modulated low-frequency high-frequency digital carrier signal, and send the continuously output high-frequency drive signal after digital-analog conversion to a third-party low-power high-frequency power source; send the pulse output high-frequency drive signal after digital-analog conversion to a third-party low-power high-frequency power source; send the pulse output low-frequency drive signal after digital-analog conversion to a third-party high-power high-frequency power source;

[0072] Features:

[0073] The frequency signal sent by the dual-frequency signal controller (10) to the dual-frequency sine / cosine digital waveform generator (20) and the dual-frequency amplitude control signal with an intrinsic dual-frequency delay control feature sent to the high-frequency and high-frequency digital carrier modulation path (30) and the low-frequency and high-frequency digital carrier modulation path (31) are both digital signals with a certain bit width;

[0074] The sine / cosine signals sent by the dual-frequency sine / cosine digital waveform generator (20) to the high-frequency and high-frequency digital carrier modulation path (30) and to the low-frequency and high-frequency digital carrier modulation path (31) are both digital signals with a certain bit width;

[0075] The modulated signal sent by the high-frequency high-frequency digital carrier modulation path (30) to the dual high-frequency digital-analog conversion output drive module (40) and the modulated signal sent by the low-frequency high-frequency digital carrier modulation path (31) to the dual high-frequency digital-analog conversion output drive module (40) are both digital signals with a certain bit width;

[0076] The digital signal with a certain bit width means that the bit width cannot be too wide or too narrow. The bit width cannot be too wide means that the memory resources and register resources are occupied as little as possible under the premise of meeting the design requirements. The bit width cannot be too narrow means that the signal strength cannot be reduced in order to save memory resources and register resources. This is a basic design requirement.

[0077] The continuously output high-frequency driving signal contains frequency and amplitude characteristics for a cold start state;

[0078] The high-frequency driving signal output by the pulse contains frequency, amplitude and time delay characteristics for maintaining the plasma state;

[0079] The low-frequency driving signal of the pulse output contains frequency, amplitude and time delay characteristics for generating high-yield plasma pulses.

[0080] Furthermore, the frequency signal sent by the dual-frequency signal controller (10) to the dual-frequency sine / cosine digital waveform generator (20) is a digital signal with a certain bit width, and the frequency signal is: a high-frequency high-frequency control signal (FREQ10) and a low-frequency high-frequency control signal (FREQ11); the digital signal with a certain bit width means that: their bit width distribution should be higher than:

[0081] FREQ10 bit width lower limit = [log2 (DWAV20 frequency ÷ DWAV20 frequency tolerance)] (1);

[0082] FREQ11 bit width lower limit = [log2 (DWAV21 frequency ÷ DWAV21 frequency tolerance)] (2).

[0083] Furthermore, for the digital high-frequency high-frequency sine / cosine waveform signal (DWAV20) to be set, the frequency f DWAV20 and the digital clock frequency f required for the operation of the dual-frequency sine / cosine digital waveform generator (20) clk , the high frequency high frequency control signal (FREQ10) should satisfy:

[0084] FREQ10=[f DWAV20 ÷f clk ×2^FREQ10 bit width] (3);

[0085] Similarly, for the digital low-frequency high-frequency sine / cosine waveform signal (DWAV21) to be set, the frequency f DWAV21 , the low-frequency and high-frequency control signal (FREQ11) should satisfy:

[0086] FREQ11=[f DWAV21 ÷f clk ×2^FREQ11 bit width] (4);

[0087] The FREQ10 bit width of the above formula (3) and the FREQ11 bit width of the above formula (4) are bit widths determined according to the FREQ10 bit width lower limit of the above formula (1) and the FREQ11 bit width lower limit of the above formula (2).

[0088] Furthermore, the amplitude signals sent by the dual-frequency signal controller (10) to the high-frequency and high-frequency digital carrier modulation path (30) and the low-frequency and high-frequency digital carrier modulation path (31) are both digital signals with a certain bit width, and the amplitude signals are: the high-frequency and high-frequency path modulation signal (AMPL12) and the low-frequency and high-frequency path modulation signal (AMPL13). The digital signals with a certain bit width mean that their bit widths should be higher than:

[0089] AMPL12 bit width lower limit = [log2(AMPL12 amplitude ÷AMPL12 amplitude tolerance)] (5);

[0090] AMPL13 bit width lower limit = [log2 (AMPL13 amplitude ÷ AMPL13 amplitude tolerance)] (6).

[0091] Furthermore, the modulated signal sent by the high-frequency and high-frequency digital carrier modulation path (30) to the dual high-frequency digital-to-analog conversion output driving module (40) and the modulated signal sent by the low-frequency and high-frequency digital carrier modulation path (31) to the dual high-frequency digital-to-analog conversion output driving module (40) are both digital signals with a certain bit width; the modulated signals are digital high-frequency and high-frequency modulated signals (DMOD30) and digital low-frequency and high-frequency modulated signals (DMOD31), and the digital signals with a certain bit width refer to digital signals whose bit widths satisfy:

[0092] DMOD30 bit width = DWAV20 bit width + AMPL12 bit width (7);

[0093] DMOD31 bit width = DWAV21 bit width + AMPL13 bit width (8);

[0094] The AMPL12 bit width of the above formula (7) and the AMPL13 bit width of the above formula (8) are bit widths determined according to the lower limit of the AMPL12 bit width of the above formula (5) and the lower limit of the AMPL13 bit width of the above formula (6).

[0095] Furthermore, the continuously output high-frequency driving signal contains frequency and amplitude characteristics for the cold start state, specifically:

[0096] The frequency is preferably a frequency with the highest plasma ignition success rate or the shortest ignition time within the working bandwidth of the low-power high-frequency power source, and any frequency within the working bandwidth of the low-power high-frequency power source that can achieve a cold start ignition function can also be selected;

[0097] The amplitude is preferably sufficient to drive the low-power high-frequency power source to output the high-frequency cold-start ignition power, and to achieve the driving signal amplitude corresponding to the minimum power of the plasma cold-start ignition function plus a sufficient margin through a third-party matching device; or preferably, the driving signal amplitude corresponding to the maximum output power that the low-power high-frequency power source can tolerate under instantaneous total reflection; or any value in between.

[0098] Furthermore, the high-frequency driving signal of the pulse output contains frequency, amplitude, and time delay characteristics for maintaining the plasma state, and its frequency, amplitude, and time delay characteristics are specifically:

[0099] The frequency is preferably a frequency consistent with the cold start state, or a frequency that can maintain the plasma state within the working bandwidth of the low-power high-frequency power source and can minimize the high-frequency standing wave ratio;

[0100] This amplitude forms a counter pulse complementary to the high-yield plasma pulse amplitude in each repetition cycle, and has a high duty cycle; the peak-to-peak value of the amplitude corresponds to the peak-to-peak value of the driving signal when the low-power high-frequency power source outputs full power; the low-power high-frequency power source is driven by the high-frequency driving signal output by the pulse.

[0101] The delay feature is 0 delay;

[0102] The plasma-maintaining state refers to the plasma-maintaining state generated by the cold start state, or the plasma-maintaining state remaining after the high-yield plasma pulse generation state ends.

[0103] Furthermore, the low-frequency driving signal of the pulse output contains frequency, amplitude, and delay characteristics for generating high-yield plasma pulses, specifically:

[0104] The frequency is optimized and adjusted according to the user's requirements for the specific working gas and plasma temperature, electron temperature, electron density and other properties of the pulsed high-frequency ionization device;

[0105] The amplitude is a short pulse with the same repetition period as the amplitude characteristic of maintaining the plasma existence state, and has a low duty cycle; the peak-to-peak value of the amplitude corresponds to the peak-to-peak value of the driving signal when the high-power high-frequency power source outputs full power; the high-power high-frequency power source is driven by the high-frequency driving signal output by the pulse.

[0106] The time delay is preferably the pulse width of the plasma-sustaining state, so as to achieve alternating appearance of short pulses of the high-yield plasma state and wide pulses of the plasma-sustaining state.

[0107] Embodiment 1

[0108] 1. In the preferred embodiment, the dual-frequency signal controller 10, the dual-frequency sine / cosine digital waveform generator 20, the high-frequency high-frequency digital carrier modulation path 30 and the low-frequency high-frequency digital carrier modulation path 31 adopt an integrated all-digital design and are implemented by a field programmable gate array (FPGA) chip and ancillary circuits. The programmable system (PS) part of the FPGA chip acts as the dual-frequency signal controller (10) and implements a dual-frequency driving method for a pulse high-frequency ionization device proposed in the present invention. The high-frequency high-frequency control signal (FREQ10), the low-frequency high-frequency control signal (FREQ11), the high-frequency high-frequency path modulation signal (AMPL12) and the high-frequency high-frequency path modulation signal (AMPL13) are set according to the control signal (IN00 and / or IN01) from the host computer (00) and / or the control board (01) and / or the feedback signal (IN02) from the feedback board (02); the programmable logic (PS) part of the FPGA chip acts as the dual-frequency signal controller (10). The Logic (PL) part coordinately allocates its hardware resources, such as memory and gate circuits, to realize the dual-frequency sine / cosine digital waveform generator (20), the high-frequency and high-frequency digital carrier modulation path (30) and the low-frequency and high-frequency digital carrier modulation path (31).

[0109] 2. In the preferred embodiment, the dual-frequency sine / cosine digital waveform generator (20) can adopt direct digital synthesis (DDS) technology, with the help of the phase accumulator designed in the embodiment, through the addressing mode, the digital high-frequency high-frequency sine / cosine waveform signal (DWAV20) and the digital low-frequency high-frequency sine / cosine waveform signal (DWAV21) are generated according to the high-frequency high-frequency frequency control signal (FREQ10) and the low-frequency high-frequency frequency control signal (FREQ11), and the bit width of the phase accumulator is consistent with the bit width of the high-frequency high-frequency frequency control signal (FREQ10) and the low-frequency high-frequency frequency control signal (FREQ11), and meets the following conditions:

[0110] FREQ10 bit width lower limit = [log2 (DWAV20 frequency ÷ DWAV20 frequency tolerance)]

[0111] FREQ11 bit width lower limit = [log2 (DWAV21 frequency ÷ DWAV21 frequency tolerance)]

[0112] For the digital high-frequency and high-frequency sine / cosine waveform signal (DWAV20) frequency fDWAV20 to be set and the digital clock frequency fclk required for the operation of the dual-frequency sine / cosine digital waveform generator (20), the high-frequency and high-frequency frequency control signal (FREQ10) should satisfy:

[0113] FREQ10 = [fDWAV20÷fclk×2^FREQ10 bit width]

[0114] Similarly, for the digital low-frequency high-frequency sine / cosine waveform signal (DWAV21) frequency fDWAV21 to be set, the low-frequency high-frequency frequency control signal (FREQ11) should satisfy:

[0115] FREQ11 = [fDWAV21÷fclk×2^FREQ11 bit width]

[0116] 3. The low-frequency high-frequency power described in the present invention can be set to a 2MHz high-power high-frequency power pulse with a duty cycle set to 2.5%, that is, the frequency of the digital low-frequency high-frequency sine / cosine waveform signal (DWAV21) to be set to fDWAV21=2MHz; the high-frequency high-frequency power described in the present invention can be set to a 13.56MHz high-frequency power reverse pulse with a duty cycle set to 97.5% or a continuous wave 13.56MHz high-frequency power, that is, the frequency of the digital high-frequency high-frequency sine / cosine waveform signal (DWAV20) to be set to fDWAV20=13.56MHz.

[0117] 4. In the embodiment of the present invention where the digital clock frequency fclk=50MHz used in the above embodiment, preferably, the bit width of the DDS phase accumulator of the dual-frequency sine / cosine digital waveform generator (20) is consistent with the bit width of the high-frequency high-frequency control signal (FREQ10) and the low-frequency high-frequency control signal (FREQ11), and both are designed according to 16 bits (two bytes), so that the frequency tolerance of the digital high-frequency high-frequency sine / cosine waveform signal (DWAV20) and the digital low-frequency high-frequency sine / cosine waveform signal (DWAV21) introduced by the dual-frequency sine / cosine digital waveform generator (20) is better than 1kHz.

[0118] 5. In the above embodiment, the high-frequency and high-frequency frequency control signal (FREQ10) is normally set to 16'b0100010101101101 (corresponding to the decimal number 17,773), so the actual output frequency of the digital high-frequency and high-frequency sine / cosine waveform signal (DWAV20) is approximately 13.559723 MHz; the low-frequency and high-frequency frequency control signal (FREQ11) is normally set to 16'b0000101000111101 (corresponding to the decimal number 2,621), so the actual output frequency of the digital low-frequency and high-frequency sine / cosine waveform signal (DWAV21) is approximately 1.999664 MHz.

[0119] 6. By setting the bit width of the DDS phase accumulator of the dual-frequency sine / cosine digital waveform generator (20) to 16 bits in accordance with the bit width of the high-frequency and high-frequency control signal (FREQ10) and the low-frequency and high-frequency control signal (FREQ11), the occupation of the storage resources of the FPGA chip described in the embodiment by the dual-frequency sine / cosine digital waveform generator (20) is limited to the maximum extent, while ensuring that the frequency tolerance of the digital high-frequency and high-frequency sine / cosine waveform signal (DWAV20) and the digital low-frequency and high-frequency sine / cosine waveform signal (DWAV21) are both better than 1kHz, thereby reducing the cost of the dual-frequency driving device for a pulsed high-frequency ionization device proposed by the present invention.

[0120] 7. The high-frequency high-frequency control signal (FREQ10) and the low-frequency high-frequency control signal (FREQ11) can be changed by the dual-frequency signal controller (10) in and outside the corresponding pulse width through a write register operation, and a digital high-frequency high-frequency sine / cosine waveform signal (DWAV20) and a digital low-frequency high-frequency sine / cosine waveform signal (DWAV21) that are naturally continuous and smoother in phase are obtained, which is beneficial to reducing the instantaneous high-frequency standing wave caused by phase mutation in the high-frequency ionization device, reducing the protection frequency of the high-frequency power source, reducing its failure rate, and improving the reliability of the device.

[0121] 8. The high-frequency high-frequency path modulation signal (AMPL12) sent by the dual-frequency signal controller (10) to the high-frequency high-frequency digital carrier modulation path (30) and the low-frequency high-frequency path modulation signal (AMPL13) sent to the low-frequency high-frequency digital carrier modulation path (31) are both digital signals with a certain bit width, and their bit widths should be higher than:

[0122] AMPL12 bit width lower limit = [log2 (AMPL12 amplitude ÷ AMPL12 amplitude tolerance)]

[0123] AMPL13 bit width lower limit = [log2 (AMPL13 amplitude ÷ AMPL13 amplitude tolerance)]

[0124] The digital high-frequency and high-frequency sine / cosine waveform signal (DWAV20) sent by the dual-frequency sine / cosine digital waveform generator (20) to the high-frequency and high-frequency digital carrier modulation path (30) and the digital low-frequency and high-frequency sine / cosine waveform signal (DWAV21) sent to the low-frequency and high-frequency digital carrier modulation path (31) are both digital signals with a certain bit width, and the digital high-frequency and high-frequency modulated signal (DMOD30) sent by the high-frequency and high-frequency digital carrier modulation path (30) to the dual-frequency digital-to-analog conversion output driving module (40) and the digital low-frequency and high-frequency modulated signal (DMOD31) sent by the low-frequency and high-frequency digital carrier modulation path (31) to the dual-frequency digital-to-analog conversion output driving module (40) are both digital signals with a certain bit width, and the bit width satisfies:

[0125] DMOD30 bit width = DWAV20 bit width + AMPL12 bit width

[0126] DMOD31 bit width = DWAV21 bit width + AMPL13 bit width

[0127] 9. The bit widths of the digital high-frequency high-frequency modulated signal (DMOD30) and the digital low-frequency high-frequency modulated signal (DMOD31) are limited by the dual high-frequency digital-to-analog conversion output drive module (40).

[0128] Embodiment 2

[0129] 1. A dual-frequency driving method for a pulse high-frequency ionization device, characterized in that: the dual-frequency driving method comprises the following steps:

[0130] Step 1: When the pulse high-frequency ionization device enters the cold start ignition state, a high-frequency driving signal for driving a low-power high-frequency power source generated by a dual-frequency driving device is continuously output to generate high-frequency low power for cold start ignition, and the high-frequency low-power pulse is fed into the pulse high-frequency ionization device through a third-party impedance matching device to ionize and generate plasma material; the continuously output high-frequency driving signal contains frequency and amplitude characteristics for the cold start state;

[0131] The specific process is as follows:

[0132] 1) When the pulse high-frequency ionization device performs cold start ignition, the continuously output high-frequency driving signal generated by the dual-frequency driving device is sent to the low-power high-frequency power source;

[0133] 2) The low-power high-frequency power source outputs a high-frequency low power of a certain frequency and amplitude corresponding to the continuously output high-frequency driving signal;

[0134] 3) The high frequency and low power are transmitted to the pulse high frequency ionization device through the adjustable vector impedance matching device connected later;

[0135] 4) Use the high frequency and low power to ignite the plasma of the pulse high frequency ionization device.

[0136] Step 2: When the pulse high-frequency ionization device enters the plasma ignition state maintenance state, the pulse output high-frequency driving signal generated by the dual-frequency driving device for driving the low-power high-frequency power source generates a high-frequency low-power for maintaining cold start ignition, and the high-frequency low-power pulse is fed into the pulse high-frequency ionization device through a third-party impedance matching device to maintain the continuous generation and existence of plasma materials with a certain density and temperature inside the pulse high-frequency ionization device; the high-frequency driving signal output by the pulse contains the frequency, amplitude, and delay characteristics for maintaining the plasma existence state; the specific process is as follows:

[0137] 1) When the pulse high-frequency ionization device is maintaining the cold start ignition state, the high-frequency driving signal generated by the pulse output of the dual-frequency driving device is sent to the low-power high-frequency power source amplifier;

[0138] 2) The low-power high-frequency power source outputs a high-frequency low power of a certain frequency and amplitude corresponding to the high-frequency driving signal output by the pulse;

[0139] 3) The high frequency and low power are transmitted to the pulse high frequency ionization device through the adjustable vector impedance matching device connected later;

[0140] 4) Use this high frequency and low power to maintain the plasma state.

[0141] Step 3: When the pulse high-frequency ionization device enters the high-yield plasma pulse generation state, the pulse output low-frequency driving signal generated by the dual-frequency driving device for driving the high-power high-frequency power source generates a low-frequency high-power for high-yield plasma generation, and the low-frequency high-power pulse is fed into the pulse high-frequency ionization device through a third-party impedance matching device, which promotes the plasma to be violently ionized in a short time and generates a large amount of plasma material that can be drawn out; the pulse output low-frequency driving signal contains the frequency, amplitude, and delay characteristics for high-yield plasma pulse generation. The specific process is as follows:

[0142] 1) When the pulse high-frequency ionization device enters the high-yield plasma pulse generation (S3) state, the low-frequency high-power driving signal generated by the dual-frequency driving device is sent to the high-power high-frequency power source amplifier;

[0143] 2) The high-power high-frequency power source amplifier outputs high-low-frequency high-power of a certain frequency and amplitude corresponding to the low-frequency high-power drive signal;

[0144] 3) The high-frequency and low-frequency high-power are delivered to the load through the adjustable vector impedance matching device connected later;

[0145] 4) Use the high and low frequencies and high powers to generate a large amount of plasma material that can be drawn out.

[0146] The above contents are merely examples and explanations of the concept of the present invention. The technicians in this technical field may make various modifications or additions to the specific embodiments described or replace them in a similar manner. As long as they do not deviate from the concept of the invention or exceed the scope defined by the claims, they should all fall within the protection scope of the present invention.

[0147] It should be emphasized that the above specific embodiments are merely explanations of the present invention, and they are not limitations of the present invention. After reading this specification, those skilled in the art can make modifications to the above embodiments without any creative contribution as needed, but as long as they are within the scope of the claims of the present invention, they are protected by patent law.

Claims

1. A dual-frequency driving device for a pulsed high-frequency ionization device, the dual-frequency driving device is used to provide a dual-frequency signal to be amplified for a low-power high-frequency power source and a high-power high-frequency power source of a third party, the low-power high-frequency power source of the third party generates a high-frequency low power for load cold start ignition and load maintenance of plasma state, and feeds the high-frequency low-power pulse to the load through a third-party impedance matching device, ionizes and generates plasma material in a cold start ignition state, and ionizes and generates plasma material to maintain the plasma state; the high-power high-frequency power source of the third party generates a low-frequency high power for high-yield plasma, and feeds the low-frequency high-power pulse to the load through a third-party impedance matching device, ionizes and generates a large amount of plasma material that can be drawn out; The dual-frequency signal to be amplified has inherent dual-frequency frequency, amplitude and time delay characteristics; the dual-frequency driving device is provided with, from one side to the other side, a dual-frequency signal controller (10), a dual-frequency sine / cosine digital waveform generator (20), a high-frequency and high-frequency digital carrier modulation path (30) and a low-frequency and high-frequency digital carrier modulation path (31), and a dual-high-frequency digital-to-analog conversion output driving module (40); The dual-frequency signal controller (10) is used to generate a dual-frequency frequency control signal and a dual-frequency amplitude control signal with an intrinsic dual-frequency delay control characteristic, and send the dual-frequency frequency control signal to a dual-frequency sine / cosine digital waveform generator (20), and send the dual-frequency amplitude control signal with an intrinsic delay characteristic to a high-frequency high-frequency digital carrier modulation path (30) and a low-frequency high-frequency digital carrier modulation path (31). The dual-frequency sine / cosine digital waveform generator (20) is used to convert the received dual-frequency frequency control signal into a sine / cosine signal and send it to a high-frequency high-frequency digital carrier modulation path (30) and a low-frequency high-frequency digital carrier modulation path (31) respectively; The high-frequency and high-frequency digital carrier modulation path (30) is used to multiply the received sine / cosine signal by the received dual-frequency amplitude control signal with an intrinsic dual-frequency delay control characteristic, thereby realizing modulation of the high-frequency and high-frequency digital carrier signal; The low-frequency and high-frequency digital carrier modulation path (31) is used to multiply the received sine / cosine signal by the received dual-frequency amplitude control signal with an intrinsic dual-frequency delay control characteristic, thereby realizing modulation of the low-frequency and high-frequency digital carrier signal; The dual high-frequency digital-analog conversion output drive module (40) is used to perform digital-analog conversion on a modulated high-frequency high-frequency digital carrier signal and a modulated low-frequency high-frequency digital carrier signal, and send the continuously output high-frequency drive signal after digital-analog conversion to a third-party low-power high-frequency power source; send the pulse output high-frequency drive signal after digital-analog conversion to a third-party low-power high-frequency power source; send the pulse output low-frequency drive signal after digital-analog conversion to a third-party high-power high-frequency power source; Features: The frequency signal sent by the dual-frequency signal controller (10) to the dual-frequency sine / cosine digital waveform generator (20) and the dual-frequency amplitude control signal with an intrinsic dual-frequency delay control feature sent to the high-frequency and high-frequency digital carrier modulation path (30) and the low-frequency and high-frequency digital carrier modulation path (31) are both digital signals with a certain bit width; The sine / cosine signals sent by the dual-frequency sine / cosine digital waveform generator (20) to the high-frequency and high-frequency digital carrier modulation path (30) and to the low-frequency and high-frequency digital carrier modulation path (31) are both digital signals with a certain bit width; The modulated signal sent by the high-frequency high-frequency digital carrier modulation path (30) to the dual high-frequency digital-analog conversion output drive module (40) and the modulated signal sent by the low-frequency high-frequency digital carrier modulation path (31) to the dual high-frequency digital-analog conversion output drive module (40) are both digital signals with a certain bit width; The digital signal with a certain bit width means that the bit width cannot be too wide or too narrow. The bit width cannot be too wide means that the memory resources and register resources are occupied as little as possible under the premise of meeting the design requirements. The bit width cannot be too narrow means that the signal strength cannot be reduced in order to save memory resources and register resources. This is a basic design requirement. The continuously output high-frequency driving signal contains frequency and amplitude characteristics for a cold start state; The high-frequency driving signal output by the pulse contains frequency, amplitude and time delay characteristics for maintaining the plasma state; The low-frequency driving signal of the pulse output contains frequency, amplitude and time delay characteristics for generating high-yield plasma pulses.

2. A dual-frequency driving device for a pulse high-frequency ionization device according to claim 1, characterized in that: The frequency signal sent by the dual-frequency signal controller (10) to the dual-frequency sine / cosine digital waveform generator (20) is a digital signal with a certain bit width, and the frequency signal is: a high-frequency high-frequency control signal (FREQ10) and a low-frequency high-frequency control signal (FREQ11); the digital signal with a certain bit width means that: their bit width distribution should be higher than: FREQ10 bit width lower limit = [log2 (DWAV20 frequency ÷ DWAV20 frequency tolerance)] (1); FREQ11 bit width lower limit = [log2 (DWAV21 frequency ÷ DWAV21 frequency tolerance)] (2).

3. A dual-frequency driving device for a pulse high-frequency ionization device according to claim 2, characterized in that: For the digital high-frequency high-frequency sine / cosine waveform signal (DWAV20) to be set, the frequency f DWAV20 and the digital clock frequency f required for the operation of the dual-frequency sine / cosine digital waveform generator (20) clk , the high frequency high frequency control signal (FREQ10) should satisfy: FREQ10=[f DWAV20 ÷f clk ×2^FREQ10 bit width] (3); Similarly, for the digital low-frequency high-frequency sine / cosine waveform signal (DWAV21) to be set, the frequency f DWAV21 , the low-frequency and high-frequency control signal (FREQ11) should satisfy: FREQ11=[f DWAV21 ÷f clk ×2^FREQ11 bit width] (4); The FREQ10 bit width of the above formula (3) and the FREQ11 bit width of the above formula (4) are bit widths determined according to the FREQ10 bit width lower limit of the above formula (1) and the FREQ11 bit width lower limit of the above formula (2).

4. A dual-frequency driving device for a pulse high-frequency ionization device according to claim 1, characterized in that: The amplitude signals sent by the dual-frequency signal controller (10) to the high-frequency and high-frequency digital carrier modulation path (30) and the low-frequency and high-frequency digital carrier modulation path (31) are both digital signals with a certain bit width. The amplitude signals are: a high-frequency and high-frequency path modulation signal (AMPL12) and a low-frequency and high-frequency path modulation signal (AMPL13). The digital signals with a certain bit width refer to that their bit widths should be higher than: AMPL12 bit width lower limit = [log2(AMPL12 amplitude ÷AMPL12 amplitude tolerance)] (5); AMPL13 bit width lower limit = [log2 (AMPL13 amplitude ÷ AMPL13 amplitude tolerance)] (6).

5. The dual-frequency driving device for a pulse high-frequency ionization device according to claim 1, characterized in that: The modulated signal sent by the high-frequency and high-frequency digital carrier modulation path (30) to the dual-high-frequency digital-to-analog conversion output driving module (40) and the modulated signal sent by the low-frequency and high-frequency digital carrier modulation path (31) to the dual-high-frequency digital-to-analog conversion output driving module (40) are both digital signals with a certain bit width; the modulated signals are digital high-frequency and high-frequency modulated signals (DMOD30) and digital low-frequency and high-frequency modulated signals (DMOD31), and the digital signals with a certain bit width refer to digital signals whose bit widths satisfy: DMOD30 bit width = DWAV20 bit width + AMPL12 bit width (7); DMOD31 bit width = DWAV21 bit width + AMPL13 bit width (8); The AMPL12 bit width of the above formula (7) and the AMPL13 bit width of the above formula (8) are bit widths determined according to the lower limit of the AMPL12 bit width of the above formula (5) and the lower limit of the AMPL13 bit width of the above formula (6).

6. A dual-frequency driving device for a pulse high-frequency ionization device according to claim 1, characterized in that: The continuously output high-frequency driving signal contains frequency and amplitude characteristics for the cold start state, specifically: The frequency is preferably a frequency with the highest plasma ignition success rate or the shortest ignition time within the working bandwidth of the low-power high-frequency power source, and any frequency within the working bandwidth of the low-power high-frequency power source that can achieve a cold start ignition function can also be selected; The amplitude is preferably sufficient to drive the low-power high-frequency power source to output the high-frequency cold-start ignition power, and to achieve the minimum power corresponding to the driving signal amplitude of the plasma cold-start ignition function plus a sufficient margin through the third-party matching device; or preferably, the driving signal amplitude corresponding to the maximum output power that the low-power high-frequency power source can tolerate under instantaneous total reflection; Or any value in between.

7. A dual-frequency driving device for a pulse high-frequency ionization device according to claim 1, characterized in that: The high-frequency driving signal output by the pulse contains frequency, amplitude, and time delay characteristics for maintaining the plasma state. The frequency, amplitude, and time delay characteristics are specifically as follows: The frequency is preferably a frequency consistent with the cold start state, or a frequency that can maintain the plasma state within the working bandwidth of the low-power high-frequency power source and can minimize the high-frequency standing wave ratio; This amplitude forms a counter pulse complementary to the high-yield plasma pulse amplitude in each repetition cycle, and has a high duty cycle; the peak-to-peak value of the amplitude corresponds to the peak-to-peak value of the driving signal when the low-power high-frequency power source outputs full power; the low-power high-frequency power source is driven by the high-frequency driving signal output by the pulse. The delay feature is 0 delay; The plasma-maintaining state refers to the plasma-maintaining state generated by the cold start state, or the plasma-maintaining state remaining after the high-yield plasma pulse generation state ends.

8. A dual-frequency driving device for a pulse high-frequency ionization device according to claim 1, characterized in that: The low-frequency driving signal of the pulse output contains the frequency, amplitude, and delay characteristics for generating high-yield plasma pulses, specifically: The frequency is optimized and adjusted according to the user's requirements for the specific working gas and plasma temperature, electron temperature, electron density and other properties of the pulsed high-frequency ionization device; The amplitude is a short pulse with the same repetition period as the amplitude characteristic of maintaining the plasma existence state, and has a low duty cycle; the peak-to-peak value of the amplitude corresponds to the peak-to-peak value of the driving signal when the high-power high-frequency power source outputs full power; the high-power high-frequency power source is driven by the high-frequency driving signal output by the pulse. The time delay is preferably the pulse width of the plasma-sustaining state, so as to achieve alternating appearance of short pulses of the high-yield plasma state and wide pulses of the plasma-sustaining state.

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