Memory and forming method thereof

Abstract

The invention discloses a memory and a forming method thereof. A first charge storage layer on the substrate; the second charge storage layer is located on the substrate on one side of the first charge storage layer and is electrically isolated from the first charge storage layer, and the charge storage mechanisms of the second charge storage layer and the first charge storage layer are different; a first tunneling oxide layer between the first charge storage layer and the substrate; a second tunneling oxide layer between the second charge storage layer and the substrate; a first barrier layer on the first charge storage layer and the second charge storage layer; a control gate on the first barrier layer over the first charge storage layer and the second charge storage layer; and the source-drain doped region is located in the substrate at two sides of the first barrier layer. According to the invention, the first charge storage layer and the second charge storage layer with different charge storage mechanisms are integrated in the same memory, so that the memory with multi-bit storage capability is obtained.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular to a memory and a method for forming the same. Background Art

[0002] With the continuous development of information technology, various electronic products are used in daily life, and memory is one of the important components of electronic products. In current memory, information is stored in binary form, that is, it can only distinguish between the two states of "1" and "0". In other words, a single memory can only achieve a storage capacity of 2 bits. Therefore, the storage capacity of current memory is relatively low.

[0003] As the demand for high-density data storage capacity of memories increases, the improvement of the data storage capacity of memories has received more and more attention. Summary of the invention

[0004] The problem solved by the embodiments of the present invention is to provide a memory and a method for forming the same, so as to improve the storage capacity of the memory.

[0005] To solve the above problems, an embodiment of the present invention provides a memory, comprising: a substrate; a first charge storage layer, located on the substrate; a second charge storage layer, located on the substrate on one side of the first charge storage layer and electrically isolated from the first charge storage layer, the second charge storage layer and the first charge storage layer having different charge storage mechanisms; a first tunneling oxide layer, located between the first charge storage layer and the substrate; a second tunneling oxide layer, located between the second charge storage layer and the substrate; a first blocking layer, located on the first charge storage layer and the second charge storage layer; a control gate, located on the first blocking layer above the first charge storage layer and the second charge storage layer; and a source-drain doped region, located in the substrate on both sides of the first blocking layer.

[0006] Correspondingly, an embodiment of the present invention also provides a method for forming a memory, comprising: providing a substrate; forming a first tunneling oxide layer and a second tunneling oxide layer on the substrate, wherein the second tunneling oxide layer is located on one side of the first tunneling oxide layer; forming a first charge storage layer on the first tunneling oxide layer, and forming a second charge storage layer on the second tunneling oxide layer, wherein the second charge storage layer is electrically isolated from the first charge storage layer, and the charge storage mechanisms of the second charge storage layer and the first charge storage layer are different; forming a first blocking layer on the first charge storage layer and the second charge storage layer; forming a control gate on the first blocking layer above the first charge storage layer and the second charge storage layer; and forming source and drain doped regions in the substrate on both sides of the first blocking layer.

[0007] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0008] The memory provided by the embodiment of the present invention includes a first charge storage layer and a second charge storage layer. Therefore, two storage units respectively consisting of the first charge storage layer and the second charge storage layer are integrated in the same memory. Moreover, the charge storage mechanisms of the second charge storage layer and the first charge storage layer are different. The two storage units can work independently, thereby realizing multi-potential operation of the memory, obtaining a memory with multi-bit storage capacity, and correspondingly improving the storage capacity of the memory.

[0009] In the method for forming a memory provided by an embodiment of the present invention, a first charge storage layer is formed on a first tunneling oxide layer, and a second charge storage layer is formed on a second tunneling oxide layer. The charge storage mechanisms of the second charge storage layer and the first charge storage layer are different. Therefore, two storage units respectively consisting of the first charge storage layer and the second charge storage layer are integrated in the same memory. Moreover, since the charge storage mechanisms of the second charge storage layer and the first charge storage layer are different, the two storage units can work independently, thereby realizing multi-potential operation of the memory, obtaining a memory with multi-bit storage capacity, and correspondingly improving the storage capacity of the memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 It is a schematic diagram of the structure of a memory;

[0011] Figure 2 It is a structural schematic diagram of an embodiment of a memory of the present invention;

[0012] Figure 3 yes Figure 2 A schematic diagram of a "programming" operation of a first charge storage layer in a memory device according to an embodiment of the present invention;

[0013] Figure 4 yes Figure 2 A schematic diagram of a "programming" operation of the second charge storage layer in a memory device according to an embodiment of the present invention;

[0014] Figure 5 yes Figure 2 A schematic diagram showing a first charge storage layer performing an "erase" operation in a memory device according to an embodiment of the present invention;

[0015] Figure 6 yes Figure 2 A schematic diagram showing a second charge storage layer performing an "erase" operation in a memory device according to an embodiment of the present invention;

[0016] Figure 7 is a schematic structural diagram of another embodiment of the memory of the present invention;

[0017] Figures 8 to 15 It is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a memory of the present invention;

[0018] Figures 16 to 19 It is a schematic structural diagram corresponding to each step in another embodiment of the method for forming a memory of the present invention. DETAILED DESCRIPTION

[0019] As can be seen from the background technology, it is currently difficult to improve the data storage capacity of a memory. Now, in conjunction with a memory, the reasons why it is difficult to improve the data storage capacity of the memory are analyzed.

[0020] refer to Figure 1 , Figure 1 It is a schematic diagram of the structure of a memory.

[0021] A memory includes: a substrate 10; a tunneling oxide layer 20 located on the substrate 10; a floating gate 30 located on the tunneling oxide layer 20; a blocking layer 40 located on the floating gate 30; a control gate 50 located on the blocking layer 40; and source-drain doped regions 60 located in the substrate 10 on both sides of the control gate 50.

[0022] The memory includes only one storage unit. In order to improve the storage capacity of the memory, one way is to reduce the area of ​​the storage unit so that more storage units can be integrated per unit area to meet the needs of high-density storage. However, reducing the area of ​​the storage unit will bring great challenges to the interconnection structure. For example, for NOR Flash, its parallel structure requires more contact holes, so reducing the area occupied by the storage unit will increase the difficulty of the interconnection process.

[0023] In order to solve the technical problem, an embodiment of the present invention provides a memory, including: a substrate; a first charge storage layer, located on the substrate; a second charge storage layer, located on the substrate on one side of the first charge storage layer and electrically isolated from the first charge storage layer, the second charge storage layer and the first charge storage layer having different charge storage mechanisms; a first tunneling oxide layer, located between the first charge storage layer and the substrate; a second tunneling oxide layer, located between the second charge storage layer and the substrate; a first blocking layer, located on the first charge storage layer and the second charge storage layer; a control gate, located on the first blocking layer above the first charge storage layer and the second charge storage layer; and a source-drain doped region, located in the substrate on both sides of the first blocking layer.

[0024] The memory provided by the embodiment of the present invention includes a first charge storage layer and a second charge storage layer. Therefore, two storage units respectively consisting of the first charge storage layer and the second charge storage layer are integrated in the same memory. Moreover, the charge storage mechanisms of the second charge storage layer and the first charge storage layer are different. The two storage units can work independently, thereby realizing multi-potential operation of the memory, obtaining a memory with multi-bit storage capacity, and correspondingly improving the storage capacity of the memory.

[0025] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0026] refer to Figure 2 , Figure 2 It is a schematic diagram of the structure of a memory device according to an embodiment of the present invention.

[0027] The memory of the embodiment of the present invention includes: a substrate 100; a first charge storage layer 130, located on the substrate 100; a second charge storage layer 140, located on the substrate 100 on one side of the first charge storage layer 130 and electrically isolated from the first charge storage layer 130, and the charge storage mechanism of the second charge storage layer 140 is different from that of the first charge storage layer 130; a first tunneling oxide layer 110, located between the first charge storage layer 130 and the substrate 100; a second tunneling oxide layer 120, located between the second charge storage layer 140 and the substrate 100; a first blocking layer 170, located on the first charge storage layer 130 and the second charge storage layer 140; a control gate 180, located on the first blocking layer 170 above the first charge storage layer 130 and the second charge storage layer 140; and a source-drain doped region 195, located in the substrate 100 on both sides of the first blocking layer 170.

[0028] The substrate 100 provides a process operation platform for the formation process of the memory.

[0029] In this embodiment, the memory is a non-volatile memory. As an example, the memory is a flash memory, such as NOR Flash.

[0030] As an example, the memory is a planar device, and the base 100 is a substrate. In other embodiments, the base may also include a substrate and a channel protrusion protruding from the substrate.

[0031] In this embodiment, the material of the substrate is silicon. In other embodiments, the material of the substrate may also be other materials such as germanium, silicon germanium, silicon carbide, gallium nitride, gallium arsenide or indium gallium, and the substrate may also be other types of substrates such as silicon on insulator substrate or germanium on insulator substrate.

[0032] It should be noted that the substrate 100 may also have a well region and a shallow trench isolation (STI) structure.

[0033] The area between the shallow trench isolation structures is an active area. Accordingly, the first charge storage layer 130 and the second charge storage layer 140 are both located on the substrate 100 in the active area.

[0034] In this embodiment, the substrate 100 includes a channel region 100c, and the channel region 100c is used to provide a conductive channel, that is, a region between a source region and a drain region of the device. When performing a "program" operation, carriers enter the first charge storage layer 130 or the second charge storage layer 140 through the conductive channel, or, when performing an "erase" operation, carriers enter the conductive channel from the first charge storage layer 130 or the second charge storage layer 140.

[0035] The first charge storage layer 130 and the second charge storage layer 140 are separately disposed on the substrate 100 and are adjacent to each other. The second charge storage layer 140 is electrically isolated from the first charge storage layer 130, and the second charge storage layer 140 and the first charge storage layer 130 have different charge storage mechanisms.

[0036] The first charge storage layer 130 and the second charge storage layer 140 are separately arranged on the substrate 100. Therefore, two storage units respectively composed of the first charge storage layer 130 and the second charge storage layer 140 are integrated in the same memory. The first charge storage layer 130 is used to provide one storage unit, and the second charge storage layer 140 is used to provide another storage unit. Therefore, a memory with multi-bit storage capacity can be obtained, and the storage capacity of the memory is correspondingly improved. For example, taking a single memory that can only distinguish between the two states of "1" and "0" as an example, a memory with 4-bit storage capacity can be obtained.

[0037] Moreover, since the charge storage mechanisms of the second charge storage layer 140 and the first charge storage layer 130 are different, the electrical signals required to be loaded when the two storage units are working are different, so that the two storage units can work independently, and the charge storage amounts of the two charge storage layers are different, thereby realizing multi-potential operation of the memory.

[0038] The second charge storage layer 140 is electrically isolated from the first charge storage layer 130 so that the operation of the two storage units can be independently controlled. In addition, the first charge storage layer 130 and the second charge storage layer 140 are disposed adjacent to each other, thereby facilitating the reduction of the occupied area of ​​the memory.

[0039] In this embodiment, the programming voltage values ​​of the first charge storage layer 130 and the second charge storage layer 140 are different, so that the electrical signals required to be loaded when the two storage units work are different, thereby enabling the two storage units to work independently.

[0040] As an example, a programming voltage value of the second charge storage layer is smaller than a programming voltage value of the first charge storage layer.

[0041] Specifically, the first charge storage layer 130 is a floating gate, and the second charge storage layer 140 is a charge trapping layer. The first charge storage layer 130 is a conductive floating gate, and the second charge storage layer 140 is an insulating charge trapping layer.

[0042] Correspondingly, based on the working mechanism of the charge trapping layer, a portion of the top of the source / drain doped region 195 close to one side of the second charge storage layer 140 is covered by the second charge storage layer 140 .

[0043] The floating gate is used to form a memory of a floating gate structure, and the charge trapping layer is used to form a memory of a charge trapping structure. The memory of the floating gate structure is programmed by hot electron injection, while the memory of the charge trapping structure is programmed by capturing charges at the interface and capturing charges in the charge trapping layer. Therefore, by making the first charge storage layer 130 a floating gate and the second charge storage layer 140 a charge trapping layer, two memory cells with different charge storage mechanisms are obtained.

[0044] It should be noted that, since the charge trapping layer is non-conductive, the memory of the charge trapping structure has a local storage characteristic. Moreover, since the charge trapping layer has an insulating property, it is also convenient to realize the electrical isolation between the first charge storage layer 130 and the second charge storage layer 140 .

[0045] The material of the floating gate includes one or more of polysilicon, single crystal silicon and high-K dielectric material, and the material of the charge trapping layer includes one or more of silicon nitride and silicon oxynitride. The high-K dielectric material refers to a dielectric material having a relative dielectric constant greater than that of silicon oxide, for example, hafnium oxide, iridium oxide or ruthenium oxide.

[0046] As an example, the material of the floating gate is polysilicon, and the material of the charge trapping layer is silicon nitride.

[0047] Specifically, the source-drain doping region 195 close to the first charge storage layer 130 is used as the first source-drain doping region 195s, and the source-drain doping region 195 close to the second charge storage layer 140 is used as the second source-drain doping region 195d, and the Figures 3 to 6 , the working method of the memory is described in detail.

[0048] like Figure 3 As shown, Figure 3 1 is a schematic diagram of the "programming" operation of the first charge storage layer 130. When the "programming" operation is performed on the first charge storage layer 130, a positive voltage is applied to the control gate 180 corresponding to the first charge storage layer 130, a negative voltage is applied to the second source-drain doped region 195d, and the first source-drain doped region 195s and the substrate 100 are grounded (i.e., a voltage of 0V). Accordingly, the electrons e in the conductive channel tunnel into the first charge storage layer 130 by hot carrier tunneling, thereby achieving storage.

[0049] As an example, a positive voltage of 7V to 12V is applied to the control gate 180 , and a negative voltage of −2V to −5V is applied to the second source / drain doping region 195 d .

[0050] like Figure 4 As shown, Figure 4 1 is a schematic diagram of the "programming" operation of the second charge storage layer 140. When the "programming" operation is performed on the second charge storage layer 140, a positive voltage is applied to the control gate 180 corresponding to the second charge storage layer 140, a positive voltage is applied to the second source-drain doped region 195d, and the first source-drain doped region 195s and the substrate 100 are grounded (i.e., a voltage of 0V). 。 Correspondingly, the electrons e in the conductive channel tunnel through hot carrier tunneling and are captured by the interface between the second tunneling oxide layer 120 and the second charge storage layer 140 , thereby realizing the storage function of the second charge storage layer 140 .

[0051] As an example, the positive voltage applied to the control gate 180 is 2V to 4V, and the positive voltage applied to the second source-drain doped region 195d is 1.5V to 3V.

[0052] It should be noted that the programming voltage value of the second charge storage layer 140 is less than the programming voltage value of the first charge storage layer 130. The programming voltage value refers to the voltage value applied to the control gate 180 when performing a "programming" operation (i.e., a "writing" operation), that is, the voltage value applied to the control gate 180 when performing a "programming" operation on the second charge storage layer 140 is less than the voltage value applied to the control gate 180 when performing a "programming" operation on the first charge storage layer 130.

[0053] like Figure 5 As shown, Figure 5 1 is a schematic diagram of the "erasing" operation of the first charge storage layer 130. When the "erasing" operation is performed on the first charge storage layer 130, a negative voltage is applied to the control gate 180 corresponding to the first charge storage layer 130, a positive voltage is applied to the first source-drain doped region 195s, a positive voltage is applied to the substrate 100, and the second source-drain doped region 195d is made floating, thereby forming a longitudinal electric field (such as Figure 5 ) and trigger the FN (Fowler-Nordheim) tunneling effect, the electrons e stored in the first charge storage layer 130 enter the conductive channel by FN tunneling, thereby realizing the erase operation.

[0054] As an example, the negative voltage applied to the control gate 180 is -7V to -10V, the positive voltage applied to the first source-drain doping region 195s is 6V to 8V, and the positive voltage applied to the substrate 100 is 6V to 8V.

[0055] like Figure 6 As shown, Figure 6 1 is a schematic diagram of the "erasing" operation of the second charge storage layer 140. When the "erasing" operation is performed on the second charge storage layer 140, a negative voltage is applied to the control gate 180 corresponding to the second charge storage layer 140, a positive voltage is applied to the first source-drain doping region 195s, a positive voltage is applied to the second source-drain doping region 195d, and the substrate 100 is grounded, so that the electrons stored in the second charge storage layer 140 are emitted to the first source-drain doping region 195s (i.e., the source) through the second tunneling oxide layer 120 under the action of the electric field formed by the gate-source coupling voltage to achieve leakage. At the same time, in the deep depletion region close to the second source-drain doping region 195d (i.e., the drain) on one side of the conductive channel, hot holes + generated by band-to-band tunneling are formed. The hot holes + are in the longitudinal electric field (such as Figure 6 Under the action of the arrow in FIG. 1 ), the electrons are injected into the second charge storage layer 140 through tunneling and neutralized with the electrons stored in the second charge storage layer 140, thereby realizing the erasing operation.

[0056] As an example, the negative voltage applied to the control gate 180 is -3V to -5V, the positive voltage applied to the first source-drain doping region 195s is 3V to 5V, and the positive voltage applied to the second source-drain doping region 195d is 1V to 3V.

[0057] In addition, when a “read” operation is performed on the first charge storage layer 130 , a positive voltage is applied to the control gate 180 , a positive voltage is applied to the first source / drain doping region 195 s , and the second source / drain doping region 195 d and the substrate 100 are grounded.

[0058] As an example, the positive voltage applied to the control gate 180 is 3V to 6V, and the positive voltage applied to the first source-drain doping region 195s is 1V to 2V.

[0059] When a “reading” operation is performed on the second charge storage layer 140 , a positive voltage is applied to the control gate 180 , a positive voltage is applied to the second source / drain doping region 195 d , and the first source / drain doping region 195 s and the substrate 100 are grounded.

[0060] As an example, the positive voltage applied to the control gate 180 is 5V, and the positive voltage applied to the second source-drain doping region 195d is 1V-2V.

[0061] In summary, based on the local storage characteristics of the memory with charge trapping structure, the storage of electrons at different positions in the charge storage layer is realized through the "write" operation of hot electron tunneling and combined with the "erase" operation of hot hole injection and FN tunneling, thereby achieving a 4-bit storage capacity.

[0062] In this embodiment, the first charge storage layer 130 covers a portion of the channel region 100 c , and the second charge storage layer 140 covers the remaining channel region 100 c .

[0063] By making the second charge storage layer 140 cover a portion of the length of the channel region 100c, the second charge storage layer 140 has a sufficient length, thereby reducing the difficulty of forming the second charge storage layer 140 (for example, reducing the difficulty of etching when patterning the material layer of the second charge storage layer 140).

[0064] It should be noted that, along the direction perpendicular to the sidewall of the first charge storage layer 130, the lateral dimension of the channel region 100c is a first dimension L1 (eg Figure 2 ), the lateral size of the channel region 100c not covered by the first charge storage layer 130 is a second size L2 (as shown in Figure 2As shown in the figure, the ratio of the second dimension L2 to the first dimension L1 should not be too small or too large. If the ratio of the second dimension L2 to the first dimension L1 is too large, it is easy to cause the charge storage capacity of the first charge storage layer 130 to be poor; if the ratio of the second dimension L2 to the first dimension L1 is too small, it is easy to increase the difficulty of forming the second charge storage layer 140 (for example, increase the etching difficulty when patterning the material layer of the second charge storage layer 140). For this reason, in this embodiment, along the direction perpendicular to the side wall of the first charge storage layer 130, the ratio of the second dimension L2 to the first dimension L1 is 1 / 4 to 1 / 3.

[0065] In this embodiment, the second charge storage layer 140 is a charge capture layer, which has a non-conductive property. Therefore, the charge capture layer (i.e., the second charge storage layer 140) also covers the side walls of the floating gate (i.e., the first charge storage layer 130) facing the charge capture layer and the top of the floating gate, and the portion of the charge capture layer located on the floating gate serves as a second blocking layer 150.

[0066] It should be noted that in order to distinguish the second blocking layer 150 from the second charge storage layer 140 located on one side of the first charge storage layer 130, Figure 3 Horizontal dotted lines are used to indicate the boundary position between the second blocking layer 150 and the second charge storage layer 140 located on one side of the first charge storage layer 130 .

[0067] The second blocking layer 150 is located between the top of the first charge storage layer 130 and the control gate 180 , and the second blocking layer 150 is used to prevent the charges stored in the first charge storage layer 130 from flowing into the control gate 180 .

[0068] As an example, the material of the charge trapping layer is silicon nitride, and accordingly, the material of the second blocking layer 150 is silicon nitride.

[0069] The first tunneling oxide layer 110 is used to prevent the electrons stored in the first charge storage layer 130 from being lost to the substrate 100 . Meanwhile, when the memory is working, the electrons migrate between the conductive channel and the first charge storage layer 130 through the first tunneling oxide layer 110 .

[0070] Similarly, the second tunneling oxide layer 120 is used to prevent the electrons stored in the second charge storage layer 140 from being lost to the substrate 100 . Meanwhile, when the memory is working, the electrons migrate between the conductive channel and the second charge storage layer 140 through the second tunneling oxide layer 120 .

[0071] As an example, the materials of the first tunneling oxide layer 110 and the second tunneling oxide layer 120 are both silicon oxide. In other embodiments, the materials of the first tunneling oxide layer 110 and the second tunneling oxide layer 120 can also be other materials that can play the same role, such as hafnium oxide or zirconium oxide.

[0072] In this embodiment, the programming voltage value of the second charge storage layer 140 is smaller than the programming voltage value of the first charge storage layer 130 . Therefore, the thickness of the second tunneling oxide layer 120 is smaller than the thickness of the first tunneling oxide layer 110 .

[0073] Specifically, the first charge storage layer 130 is a floating gate, and the second charge storage layer 140 is a charge trapping layer. Compared with a memory having a floating gate structure, a memory having a charge trapping structure generally has a smaller programming voltage value.

[0074] As an example, the thickness of the first tunneling oxide layer 110 is 50 nanometers to 100 nanometers, and the thickness of the second tunneling oxide layer 120 is 7 nanometers to 15 nanometers.

[0075] In this embodiment, the first tunneling oxide layer 110 and the second tunneling oxide layer 120 are an integrated structure, which is beneficial to improving the reliability of the first tunneling oxide layer 110 and the second tunneling oxide layer 120, for example, reducing the probability of defects caused by the existence of an interface between the first tunneling oxide layer 110 and the second tunneling oxide layer 120.

[0076] Moreover, in the process of preparing the memory, the process of forming the tunneling oxide layer on the substrate 100 is usually an in-situ steam generation (ISSG) process, and the film layer formed by the ISSG process has fewer internal defects, so that the film layer quality of the tunneling oxide layer is higher. To this end, by making the first tunneling oxide layer 110 and the second tunneling oxide layer 120 an integrated structure, the first tunneling oxide layer 110 and the second tunneling oxide layer 120 can be formed in the same step, thereby improving the quality of the first tunneling oxide layer 110 and the second tunneling oxide layer 120.

[0077] Specifically, in the process of preparing the memory, the surface of the substrate 100 can be specifically treated so that the material of the tunneling oxide layer has different growth rates on the surface of the substrate 100 in the areas corresponding to the first tunneling oxide layer 110 and the second tunneling oxide layer 120, thereby forming the first tunneling oxide layer 110 and the second tunneling oxide layer 120 in the same step while making the thicknesses of the two different.

[0078] For example, growth inhibiting ions may be doped onto the surface of the substrate 100 at the location where the second charge storage layer 140 is to be formed to form an inhibiting ion doping region. Accordingly, in the same step, a first tunneling oxide layer 110 may be formed on the substrate 100 without the inhibiting ion doping region, and a second tunneling oxide layer 120 may be formed on the substrate 100 with the inhibiting ion doping region, and the thickness of the second tunneling oxide layer 120 may be less than the thickness of the first tunneling oxide layer 110.

[0079] As an example, the growth inhibiting ions may be nitrogen (N2+) ions. It should be noted that since the N2+ ions exist in an unstable state after being implanted into the substrate 100, as the growth time of the first tunneling oxide layer 110 and the second tunneling oxide layer 120 increases, the unstable nitride will overflow from the substrate 100, so the growth inhibiting ions located in the substrate 100 may not exist in the semiconductor structure.

[0080] It should be noted that in order to distinguish between the two, Figure 2 A vertical dotted line is used to indicate the boundary position between the first tunneling oxide layer 110 and the second tunneling oxide layer 120 .

[0081] It should also be noted that, in other embodiments, the first tunneling oxide layer and the second tunneling oxide layer may also be non-integrated structures.

[0082] The first blocking layer 170 is located between the first charge storage layer 130 and the control gate 180, and is also located between the second charge storage layer 140 and the control gate 180. The first blocking layer 170 is used to isolate the first charge storage layer 130 and the control gate 180, thereby preventing the charges stored in the first charge storage layer 130 from being lost to the control gate 180. Moreover, the first blocking layer 170 is also used to isolate the second charge storage layer 140 and the control gate 180, thereby preventing the charges stored in the second charge storage layer 140 from being lost to the control gate 180.

[0083] The material of the first barrier layer 170 includes one or more of silicon oxide, silicon nitride and silicon oxynitride.

[0084] As an example, the material of the first blocking layer 170 is silicon oxide, thereby improving the bonding ability between the first blocking layer 170 and the control gate 180, which is beneficial to improving the bonding stability between the control gate 180 and the first charge storage layer 130, and the bonding stability between the control gate 180 and the second charge storage layer 140, and correspondingly also helps to improve the isolation effect of the first blocking layer 170.

[0085] In this embodiment, the memory further includes: a third blocking layer 160 located on the top of the floating gate and between the second blocking layer 150 .

[0086] The programming voltage value of the first charge storage layer 130 is relatively large. Therefore, by arranging a stacked structure consisting of a third blocking layer 160, a second blocking layer 150 and a first blocking layer 170 on the floating gate, the thickness of the stacked structure is relatively large, so that the stacked structure has a stronger isolation capability.

[0087] The material of the third barrier layer 160 includes one or more of silicon oxide, silicon nitride and silicon oxynitride.

[0088] As an example, the material of the third blocking layer 160 is silicon oxide, so as to enhance the bonding ability between the second blocking layer 150 and the first charge storage layer 130 .

[0089] It can be seen that in this embodiment, the material of the first barrier layer 170 is silicon oxide, the material of the second barrier layer 150 is silicon nitride, and the material of the third barrier layer 160 is silicon oxide. That is to say, the first barrier layer 170, the second barrier layer 150 and the third barrier layer 160 constitute a silicon oxide-silicon nitride-silicon oxide (ONO) structure, and the ONO structure has a stronger isolation capability.

[0090] It should be noted that, in a conventional floating gate structure memory, an ONO structure is usually used as a barrier layer between a floating gate and a control gate. Therefore, the charge capture layer of this embodiment also covers the side wall of the floating gate facing the charge capture layer and the top of the floating gate, and the portion of the charge capture layer located on the floating gate is used as the second barrier layer 150. In other words, this embodiment, based on a conventional floating gate structure memory, uses the silicon nitride layer in the ONO barrier layer to form the second charge storage layer 140, without adding a new film layer to form the second charge storage layer 140, and the bottom silicon oxide layer (i.e., the third barrier layer 160) in the ONO barrier layer covers the first charge storage layer 130, and the top silicon oxide layer (i.e., the first barrier layer 170) in the ONO barrier layer covers the second barrier layer 150 and the second charge storage layer 140, thereby realizing multi-bit storage while improving the compatibility of the storage unit composed of the charge capture layer with the conventional process, which is also conducive to reducing the process complexity.

[0091] The control gate 180 is used to control the first charge storage layer 130 and the second charge storage layer 140 , thereby controlling the storage and release of electrons.

[0092] As an example, the material of the control gate 180 is polysilicon.

[0093] In this embodiment, the control gate 180 above the first charge storage layer 130 and the second charge storage layer 140 is an integrated structure, and the control gate 180 is shared by the first charge storage layer 130 and the second charge storage layer 140 .

[0094] The first charge storage layer 130 and the second charge storage layer 140 share the control gate 180 , which helps to omit the etching step of dividing the control gate 180 above the first charge storage layer 130 and the second charge storage layer 140 , thereby simplifying the process steps.

[0095] In other embodiments, according to actual needs (for example, the control gate above the first charge storage layer and the control gate above the second charge storage layer need to be controlled separately), the control gate above the first charge storage layer and the control gate above the second charge storage layer may also be separated from each other.

[0096] The source-drain doping region 195 is used to provide a source region and a drain region of the memory, thereby forming a memory.

[0097] In this embodiment, the second charge storage layer 140 and the first charge storage layer 130 share a source-drain doped region 195 .

[0098] Since the second charge storage layer 140 and the first charge storage layer 130 have different charge storage mechanisms and can be implemented in the same device, the second charge storage layer 140 and the first charge storage layer 130 can share the control gate 180 and the source-drain doping region 195 .

[0099] In this embodiment, the source-drain doping region 195 close to the first charge storage layer 130 is a first source-drain doping region 195s, and the source-drain doping region 195 close to the second charge storage layer 140 is a second source-drain doping region 195d.

[0100] Specifically, the first charge storage layer 130 is a floating gate, and the second charge storage layer 140 is a charge trapping layer. Therefore, the first source-drain doped region 195s is a source region, and the second source-drain doped region 195d is a drain region.

[0101] In this embodiment, the semiconductor structure also includes: side walls 190, which are located on the substrate 100 on both sides of the control gate 180 and cover the side walls of the first tunneling oxide layer 110, the side walls of the second tunneling oxide layer 120, the side walls of the first charge storage layer 130, the side walls of the second charge storage layer 140, the side walls of the first blocking layer 170 and the side walls of the control gate 180.

[0102] Specifically, the semiconductor structure further includes: a third barrier layer 160 and a second barrier layer 150 . Accordingly, the spacer 190 also covers the sidewalls of the third barrier layer 160 and the sidewalls of the second barrier layer 150 .

[0103] The spacer 190 is used to protect the sidewalls of the charge storage layer, the blocking layer and the tunneling oxide layer, and is also used to define the position of the source and drain doping regions 195 .

[0104] The sidewall spacer 190 may be a single-layer structure or a stacked-layer structure, and the material of the sidewall spacer 190 includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride oxide, silicon nitride oxide, boron nitride and boron carbonitride.

[0105] Figure 7 It is a schematic structural diagram of another embodiment of the memory of the present invention.

[0106] The similarities between this embodiment and the above-mentioned embodiment are not repeated here. The difference between this embodiment and the above-mentioned embodiment is that the third blocking layer 360 is also located between the sidewall of the floating gate (i.e., the first charge storage layer 330) and the second blocking layer 350, and the third blocking layer 360 and the second tunneling oxide layer 320 are an integrated structure.

[0107] That is to say, in this embodiment, the first tunneling oxide layer 310 and the second tunneling oxide layer 320 are separate from each other and are not an integrated structure.

[0108] In this embodiment, a barrier layer (ie, the third barrier layer 360 ) in a conventional floating gate structure memory is directly used to prepare the second tunneling oxide layer 320 , which not only has better process compatibility but also saves the process steps required to prepare the second tunneling oxide layer 320 .

[0109] In a specific embodiment, in a memory device with a conventional floating gate structure, an ONO structure is generally used as a blocking layer between a floating gate and a control gate, and a portion of the charge capture layer (i.e., the second charge storage layer 340) located on the floating gate (i.e., the first charge storage layer 330) serves as a second blocking layer 350. Therefore, two layers of the ONO blocking layer in the conventional process can be used to form a second tunneling oxide layer 320 and a charge capture layer, respectively, without the need for adding a mask and process steps.

[0110] It should also be noted that, in other embodiments, according to actual needs, it can also be that: the partial thickness material layer of the second tunneling oxide layer close to the substrate side is an integral structure with the first tunneling oxide layer, and the remaining thickness of the material layer is an integral structure with the third blocking layer, that is, the second tunneling oxide layer includes a first sub-tunneling oxide layer, and a second sub-tunneling oxide layer located on the first sub-tunneling oxide layer, the first sub-tunneling oxide layer and the first tunneling oxide layer are an integral structure, and the second sub-tunneling oxide layer and the third blocking layer are an integral structure.

[0111] For the specific description of the memory described in this embodiment, reference may be made to the relevant description of the aforementioned embodiment, which will not be repeated here.

[0112] Figures 8 to 15 It is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a memory of the present invention.

[0113] refer to Figure 8 , providing a substrate 200.

[0114] The substrate 200 provides a process operation platform for the formation process of the memory.

[0115] In this embodiment, the memory is a non-volatile memory. As an example, the memory is a flash memory, such as NOR Flash.

[0116] As an example, the memory is a planar device, and the base 200 is a substrate. In other embodiments, the base may also include a substrate and a channel protrusion protruding from the substrate.

[0117] In this embodiment, the material of the substrate is silicon. In other embodiments, the material of the substrate may also be other materials such as germanium, silicon germanium, silicon carbide, gallium nitride, gallium arsenide or indium gallium, and the substrate may also be other types of substrates such as silicon on insulator substrate or germanium on insulator substrate.

[0118] In this embodiment, the substrate 200 includes a channel region 200c, and the channel region 200c is used to provide a conductive channel, that is, a region between a source region and a drain region of a device. When performing a "programming" operation, carriers enter the first charge storage layer 130 or the second charge storage layer 140 through the conductive channel, or, when performing an "erasing" operation, carriers enter the conductive channel from the first charge storage layer 130 or the second charge storage layer 140.

[0119] It should be noted that, after providing the substrate 200 , the forming method may further include: forming a shallow trench isolation (STI) structure in the substrate 200 .

[0120] The area between the shallow trench isolation structures is an active area. Accordingly, a memory cell is subsequently formed on the substrate 100 in the active area.

[0121] After forming the shallow trench isolation structure, the forming method may further include: forming a well region in the substrate 200 .

[0122] The steps for forming the shallow trench isolation structure and the well region will not be described in detail here.

[0123] Combined with reference Fig. 9 Before subsequently forming the first tunneling oxide layer and the second tunneling oxide layer, it also includes: at the location where the second charge storage layer is to be formed, doping growth inhibition ions into the surface of the substrate 200 to form an inhibition ion doping region (not shown).

[0124] Subsequently, a first charge storage layer is formed on the first tunneling oxide layer, and a second charge storage layer is formed on the second tunneling oxide layer, and the thickness of the second tunneling oxide layer is less than the thickness of the first tunneling oxide layer. Accordingly, by doping the surface of the substrate 200 with growth inhibition ions, it is convenient to form the first tunneling oxide layer and the second tunneling oxide layer with different thicknesses in the same step.

[0125] For example, a programming voltage value of the second charge storage layer is smaller than a programming voltage value of the first charge storage layer, and therefore, a thickness of the second tunneling oxide layer is smaller than a thickness of the first tunneling oxide layer.

[0126] The growth inhibiting ions are used to reduce the formation rate of the tunneling oxide layer on the surface of the substrate 200, that is, the growth rate of the tunneling oxide layer on the surface of the substrate 200 with the growth inhibiting ions is slower. Therefore, when the first tunneling oxide layer and the second tunneling oxide layer are subsequently formed in the same step, the growth rate of the second tunneling oxide layer is lower than the growth rate of the first tunneling oxide layer, so that the thickness of the second tunneling oxide layer is lower than the thickness of the first tunneling oxide layer.

[0127] Compared with a conventional floating gate structure memory, this embodiment dopes growth inhibiting ions on the surface of the substrate 200 to set tunneling oxide layers of different thicknesses for different storage cells, thereby simplifying the process for preparing the memory described in this embodiment and achieving high process compatibility.

[0128] In this embodiment, the growth inhibiting ions include nitrogen (N2+) ions. Most of the implanted nitrogen atoms are embedded in the lattice defects (e.g., silicon lattice defects) of the substrate 200, and during the high-temperature oxidation process of forming the first tunneling oxide layer and the second tunneling oxide layer, recrystallization growth will be performed to form Si-N bands, thereby inhibiting the growth of the oxide layer (e.g., silicon oxide).

[0129] Specifically, the process of doping the surface of the substrate 200 with growth inhibiting ions includes an ion implantation process.

[0130] By adopting the ion implantation process, ion doping can be carried out in a targeted manner on a local area, and the process is simpler.

[0131] Specifically, the step of doping growth inhibition ions into the surface of the substrate 200 includes: forming a first mask layer 201 on a portion of the substrate 200, wherein the first mask layer 201 exposes the substrate 200 at a position where the second charge storage layer is to be formed; using the first mask layer 201 as a mask, performing ion implantation on the exposed substrate 200; and removing the first mask layer 201 after the ion implantation.

[0132] As an example, the material of the first mask layer 201 is photoresist.

[0133] It should be noted that, since the tunneling oxide layer is formed on the surface of the substrate 200, the injection energy of the ion implantation process should not be too small or too large. If the injection energy of the ion implantation process is too small, the injection depth is likely to be too shallow, and the ions are likely to escape from the surface of the substrate 100, resulting in poor effect of the injected ions in suppressing the growth of the tunneling oxide layer; if the injection energy of the ion implantation process is too large, the injection depth is likely to be too large, which will also result in poor effect of the injected ions in suppressing the growth of the tunneling oxide layer. For this reason, in this embodiment, the injection energy of the ion implantation process is 28KeV to 35KeV.

[0134] It should also be noted that the implantation dose of the ion implantation process should not be too small or too large. If the implantation dose of the ion implantation process is too small, it is easy to lead to poor effect of improving the thickness difference of the first tunneling oxide layer and the second tunneling oxide layer; if the implantation dose of the ion implantation process is too large, it is easy to increase the possibility of drift of typical parameters of the device. For this reason, in this embodiment, the implantation dose of the ion implantation process is 1E16 atoms per square centimeter to 1E14 atoms per square centimeter.

[0135] refer to Fig.10 , a first tunneling oxide layer 210 and a second tunneling oxide layer 220 are formed on the substrate 200 , and the second tunneling oxide layer 220 is located on one side of the first tunneling oxide layer 210 .

[0136] Subsequently, a first charge storage layer is formed on the first tunneling oxide layer 210, and a second charge storage layer is formed on the second tunneling oxide layer 220. The first tunneling oxide layer 210 is used to prevent the electrons stored in the first charge storage layer from being lost to the substrate 200. At the same time, when the memory is working, electrons migrate between the conductive channel and the first charge storage layer through the first tunneling oxide layer 210.

[0137] Similarly, the second tunneling oxide layer 220 is used to prevent the electrons stored in the second charge storage layer from being lost to the substrate 200 . Meanwhile, when the memory is working, the electrons migrate between the conductive channel and the second charge storage layer through the second tunneling oxide layer 220 .

[0138] As an example, the materials of the first tunneling oxide layer 210 and the second tunneling oxide layer 220 are both silicon oxide. In other embodiments, the materials of the first tunneling oxide layer 210 and the second tunneling oxide layer 220 can also be other materials that can play the same role, such as hafnium oxide or zirconium oxide.

[0139] In this embodiment, the thickness of the second tunneling oxide layer 220 is less than the thickness of the first tunneling oxide layer 210. Specifically, since the programming voltage value of the second charge storage layer formed subsequently is less than the programming voltage value of the first charge storage layer, the thickness of the second tunneling oxide layer 220 is less than the thickness of the first tunneling oxide layer 210.

[0140] As an example, the thickness of the first tunneling oxide layer 210 is 50 nanometers to 100 nanometers, and the thickness of the second tunneling oxide layer 220 is 7 nanometers to 15 nanometers.

[0141] In this embodiment, the first tunneling oxide layer 210 and the second tunneling oxide layer 220 are formed in the same step. Accordingly, the first tunneling oxide layer 210 and the second tunneling oxide layer 220 are an integrated structure.

[0142] By forming the integrated first tunneling oxide layer 210 and the second tunneling oxide layer 220 in the same step, it is beneficial to improve the reliability of the first tunneling oxide layer 110 and the second tunneling oxide layer 120, for example, reducing the probability of defects caused by the existence of an interface between the first tunneling oxide layer 210 and the second tunneling oxide layer 220.

[0143] In this embodiment, the first tunneling oxide layer 210 and the second tunneling oxide layer 220 are formed by an in-situ steam oxidation process. The film layer formed by the in-situ steam oxidation process has fewer internal defects, so that the film layer quality of the tunneling oxide layer is higher, thereby improving the quality of the first tunneling oxide layer 110 and the second tunneling oxide layer 120.

[0144] It should be noted that in order to distinguish between the two, Fig. 9 A vertical dotted line is used to indicate the boundary position between the first tunneling oxide layer 210 and the second tunneling oxide layer 220 .

[0145] Specifically, the step of forming a first tunneling oxide layer 210 and a second tunneling oxide layer 220 on the substrate 200 includes: in the same step, forming the first tunneling oxide layer 210 on the substrate 200 where the ion doping inhibition zone is not formed, and forming the second tunneling oxide layer 220 on the substrate 200 where the ion doping inhibition zone is formed, and the thickness of the second tunneling oxide layer 220 is less than the thickness of the first tunneling oxide layer 210.

[0146] In the present embodiment, in the step of forming the first tunneling oxide layer 210 and the second tunneling oxide layer 220 on the substrate 200, the first tunneling oxide layer 210 covers a portion of the channel region 200c, and the second tunneling oxide layer 220 covers the remaining channel region 200c, so as to facilitate the subsequent second charge storage layer to cover a partial length of the channel region 200c.

[0147] By making the second charge storage layer cover a portion of the length of the channel region 200c, it is beneficial to make the second charge storage layer have a sufficient length, thereby reducing the difficulty of forming the second charge storage layer (for example, reducing the difficulty of etching when patterning the material layer of the second charge storage layer).

[0148] It should be noted that, along the direction perpendicular to the sidewall of the first tunneling oxide layer 210, the lateral dimension of the channel region 200c is the first dimension L1, and the lateral dimension of the channel region not covered by the first tunneling oxide layer 210 is the second dimension L2, and the ratio of the second dimension L2 to the first dimension L1 should not be too small or too large. If the ratio of the second dimension L2 to the first dimension L1 is too large, it is easy to cause the charge storage capacity of the first charge storage layer 130 to be poor; if the ratio of the second dimension L2 to the first dimension L1 is too small, it is easy to increase the difficulty of forming the second charge storage layer (for example, increase the etching difficulty when patterning the material layer of the second charge storage layer). For this reason, in the present embodiment, along the direction perpendicular to the sidewall of the first tunneling oxide layer 210, the ratio of the second dimension L2 to the first dimension L1 is 1 / 4 to 1 / 3.

[0149] It should also be noted that, in other embodiments, the first tunneling oxide layer and the second tunneling oxide layer may be formed in different steps. Accordingly, the formation method may also omit the step of doping the substrate surface with growth inhibiting ions.

[0150] refer to Figures 11 to 15A first charge storage layer 230 is formed on the first tunneling oxide layer 210, and a second charge storage layer 240 is formed on the second tunneling oxide layer 220, wherein the second charge storage layer 240 is electrically isolated from the first charge storage layer 210, and the charge storage mechanisms of the second charge storage layer 240 and the first charge storage layer 210 are different; a first blocking layer 270 is formed on the first charge storage layer 230 and the second charge storage layer 240; and a control gate 280 is formed on the first blocking layer 270 above the first charge storage layer 230 and the second charge storage layer 240.

[0151] The first charge storage layer 230 and the second charge storage layer 240 are separately disposed on the substrate 200 and are adjacent to each other. The second charge storage layer 240 is electrically isolated from the first charge storage layer 230 , and the second charge storage layer 240 and the first charge storage layer 230 have different charge storage mechanisms.

[0152] The first charge storage layer 230 and the second charge storage layer 240 are separately disposed on the substrate 200. Therefore, two storage units respectively composed of the first charge storage layer 230 and the second charge storage layer 240 are integrated in the same memory. The first charge storage layer 230 is used to provide one storage unit, and the second charge storage layer 240 is used to provide another storage unit. Thus, a memory with multi-bit storage capacity can be obtained, and the storage capacity of the memory is correspondingly improved. For example, taking a single memory that can only distinguish between the two states of "1" and "0" as an example, a memory with 4-bit storage capacity can be obtained.

[0153] Moreover, since the charge storage mechanisms of the second charge storage layer 240 and the first charge storage layer 230 are different, the electrical signals required to be loaded when the two storage units are working are different, so that the two storage units can work independently, and the charge storage amounts of the two charge storage layers are different, thereby realizing multi-potential operation of the memory.

[0154] The second charge storage layer 240 is electrically isolated from the first charge storage layer 230 so that the operation of the two storage units can be independently controlled. In addition, the first charge storage layer 230 and the second charge storage layer 240 are disposed adjacent to each other, thereby facilitating the reduction of the occupied area of ​​the memory.

[0155] In this embodiment, the programming voltage values ​​of the first charge storage layer 230 and the second charge storage layer 240 are different, so that the electrical signals required to be loaded when the two storage units work are different, thereby enabling the two storage units to work independently.

[0156] As an example, a programming voltage value of the second charge storage layer is smaller than a programming voltage value of the first charge storage layer.

[0157] Specifically, the first charge storage layer 230 is a floating gate, and the second charge storage layer 240 is a charge trapping layer. The first charge storage layer 230 is a conductive floating gate, and the second charge storage layer 240 is an insulating charge trapping layer.

[0158] Compared with floating gate structure memories, charge trapping structure memories generally have a smaller programming voltage value.

[0159] The floating gate is used to form a memory of a floating gate structure, and the charge trapping layer is used to form a memory of a charge trapping structure. The memory of the floating gate structure is programmed by hot electron injection, while the memory of the charge trapping structure is to capture charges at the interface and capture the charges in the charge trapping layer. Therefore, by making the first charge storage layer 230 a floating gate and the second charge storage layer 240 a charge trapping layer, two memory cells with different charge storage mechanisms are obtained.

[0160] It should be noted that, since the charge trapping layer is non-conductive, the memory of the charge trapping structure has a local storage characteristic. Moreover, since the charge trapping layer has an insulating property, it is also convenient to realize the electrical isolation between the first charge storage layer 230 and the second charge storage layer 240.

[0161] The material of the floating gate includes one or more of polysilicon, single crystal silicon and high-K dielectric material, and the material of the charge trapping layer includes one or more of silicon nitride and silicon oxynitride. The high-K dielectric material refers to a dielectric material having a relative dielectric constant greater than that of silicon oxide, for example, hafnium oxide, iridium oxide or ruthenium oxide.

[0162] As an example, the material of the floating gate is polysilicon, and the material of the charge trapping layer is silicon nitride.

[0163] The first blocking layer 270 is located between the first charge storage layer 230 and the control gate 280, and is also located between the second charge storage layer 240 and the control gate 280. The first blocking layer 270 is used to isolate the first charge storage layer 230 and the control gate 280, thereby preventing the charges stored in the first charge storage layer 230 from being lost to the control gate 280. Moreover, the first blocking layer 270 is also used to isolate the second charge storage layer 240 and the control gate 280, thereby preventing the charges stored in the second charge storage layer 240 from being lost to the control gate 280.

[0164] The material of the first barrier layer 270 includes one or more of silicon oxide, silicon nitride and silicon oxynitride.

[0165] As an example, the material of the first blocking layer 270 is silicon oxide, thereby improving the bonding ability between the first blocking layer 270 and the control gate 280, which is beneficial to improving the bonding stability between the control gate 280 and the first charge storage layer 230, and the bonding stability between the control gate 280 and the second charge storage layer 240, which is correspondingly beneficial to improving the isolation effect of the first blocking layer 270.

[0166] The control gate 280 is used to control the first charge storage layer 230 and the second charge storage layer 240 , thereby controlling the storage and release of electrons.

[0167] As an example, the material of the control gate 280 is polysilicon.

[0168] In this embodiment, the control gate 280 above the first charge storage layer 230 and the second charge storage layer 240 is an integrated structure, and the control gate 280 is shared by the first charge storage layer 230 and the second charge storage layer 240 .

[0169] The first charge storage layer 230 and the second charge storage layer 240 share the control gate 280 , which helps to omit the etching step of dividing the control gate 280 above the first charge storage layer 230 and the second charge storage layer 240 , thereby simplifying the process steps.

[0170] like Fig.15 As shown, in this embodiment, in the step of forming the charge capture layer (i.e., the second charge storage layer 240), the charge capture layer also covers the floating gate (i.e., the first charge storage layer 230) facing the side wall of the charge capture layer and the top of the floating gate, and the portion of the charge capture layer located on the floating gate serves as a second blocking layer 250.

[0171] The second blocking layer 250 is located between the top of the first charge storage layer 230 and the control gate 280 , and the second blocking layer 250 is used to prevent the charges stored in the first charge storage layer 230 from flowing into the control gate 280 .

[0172] The second charge storage layer 140 is a charge trapping layer, which has a non-conductive property, and thus can extend to cover the floating gate and has little influence on the floating gate.

[0173] It should be noted that in order to distinguish the second blocking layer 250 from the second charge storage layer 240 located on one side of the first charge storage layer 230, Fig.15 Horizontal dotted lines are used to indicate the boundary position between the second blocking layer 250 and the second charge storage layer 240 located on one side of the first charge storage layer 230 .

[0174] As an example, the material of the charge trapping layer is silicon nitride, and accordingly, the material of the second blocking layer 250 is silicon nitride.

[0175] In this embodiment, before forming the charge trapping layer (i.e., the second charge storage layer 240), the forming method further includes: forming a third blocking layer 260 (i.e., the first charge storage layer 230) on the top of the floating gate (i.e., the first charge storage layer 230). Fig.12 shown).

[0176] The programming voltage value of the first charge storage layer 230 is relatively large. Therefore, by setting a stacked structure consisting of a third blocking layer 260, a second blocking layer 250 and a first blocking layer 270 on the floating gate, the thickness of the stacked structure is relatively large, so that the stacked structure has a stronger isolation capability.

[0177] The material of the third barrier layer 260 includes one or more of silicon oxide, silicon nitride and silicon oxynitride.

[0178] As an example, the material of the third blocking layer 260 is silicon oxide, so as to enhance the bonding ability between the second blocking layer 250 and the first charge storage layer 230 .

[0179] It can be seen that in this embodiment, the material of the first barrier layer 270 is silicon oxide, the material of the second barrier layer 250 is silicon nitride, and the material of the third barrier layer 260 is silicon oxide. That is to say, the first barrier layer 270, the second barrier layer 250 and the third barrier layer 260 constitute a silicon oxide-silicon nitride-silicon oxide (ONO) structure, and the ONO structure has a stronger isolation capability.

[0180] It should be noted that, in a conventional floating gate structure memory, an ONO structure is usually used as a barrier layer between a floating gate and a control gate. This embodiment, based on a conventional floating gate structure memory, utilizes a silicon nitride layer in an ONO barrier layer to form a second charge storage layer 240, without adding a new film layer to form the second charge storage layer 230, and the bottom silicon oxide layer (i.e., the third barrier layer 260) in the ONO barrier layer covers the first charge storage layer 230, and the top silicon oxide layer (i.e., the first barrier layer 270) in the ONO barrier layer covers the second barrier layer 250 and the second charge storage layer 240, thereby achieving multi-bit storage while improving the compatibility of the storage unit composed of a charge capture layer with conventional processes, which is also beneficial to reducing process complexity.

[0181] The following combination Figures 11 to 15, the steps of forming the first charge storage layer 230, the second charge storage layer 240, the first blocking layer 270, the third blocking layer 260 and the control gate 280 are described in detail.

[0182] refer to Fig.11 , forming a floating gate material layer 235.

[0183] Subsequently, the floating gate material layer 235 is patterned to form a floating gate for serving as a first charge storage layer.

[0184] Specifically, the floating gate is formed after the first tunneling oxide layer 210 and the second tunneling oxide layer 220 are formed. To this end, the floating gate material layer 235 is formed on the first tunneling oxide layer 210 and the second tunneling oxide layer 220 .

[0185] In this embodiment, the floating gate material layer 235 is made of polysilicon.

[0186] It should be noted that after forming the floating gate material layer 235 , the method further includes: forming a third barrier material layer 265 covering the floating gate material layer 235 .

[0187] The third barrier material layer 265 is then patterned to form a third barrier layer located on the top of the floating gate.

[0188] Specifically, the third barrier material layer 265 is made of silicon oxide.

[0189] Before forming the second charge storage layer, the third blocking material layer 265 is formed first. On the one hand, it is convenient to use the same mask to pattern the third blocking material layer 265 and the floating gate material layer 235 in sequence, thereby simplifying the process steps and reducing the process cost.

[0190] On the other hand, when forming the third barrier material layer 265, the floating gate material layer 235 has not yet been patterned, so the floating gate material layer 235 can provide a flat surface for the formation of the third barrier material layer 265, thereby reducing the difficulty of forming the third barrier material layer 265, which is correspondingly beneficial to improving the formation quality of the third barrier material layer 265.

[0191] In addition, it is convenient to pattern the third blocking material layer 265 before forming the second charge storage layer. Compared with the solution of forming the third blocking material layer and patterning the third blocking material layer after forming the second charge storage layer, the influence of the step of patterning the third blocking material layer on the second charge storage layer is avoided.

[0192] It should also be noted that after forming the floating gate material layer 235 , the process further includes: performing a planarization process on the surface of the floating gate material layer 235 .

[0193] By performing a planarization process on the surface of the floating gate material layer 235 , the surface planarity of the floating gate material layer 235 is improved, which is also helpful in providing a planar surface for the subsequent formation of other film layers.

[0194] In this embodiment, the process of planarizing the surface of the floating gate material layer 235 includes a chemical mechanical polishing process, so as to achieve global planarization.

[0195] refer to Fig.12 , patterning the third barrier material layer 265 and the floating gate material layer 235 to form a floating gate and a third barrier layer 260 located on the top of the floating gate.

[0196] It should be noted that the floating gate here is the first charge storage layer 230 .

[0197] In this embodiment, after forming the third barrier material layer 265, the third barrier material layer 265 and the floating gate material layer 235 are patterned, so that the floating gate material layer 235 can be patterned and the third barrier material layer 265 on the top of the second tunneling oxide layer 220 can be removed in the same patterning process.

[0198] Specifically, the step of patterning the third blocking material layer 265 and the floating gate material layer 235 includes: forming a second mask layer 202 covering the third blocking material layer 265, wherein the second mask layer 202 is located at least at a position where the first charge storage layer is to be formed, and exposes the third blocking material layer 265 at a position where the second charge storage layer is to be formed; using the second mask layer 202 as a mask, etching and removing the third blocking material layer 265 and the floating gate material layer 235 exposed by the second mask layer 202; and removing the second mask layer 202.

[0199] In this embodiment, a dry etching process is used to pattern the third barrier material layer 265 and the floating gate material layer 235 to improve the morphology quality of the floating gate and the third barrier layer 260 .

[0200] As an example, the material of the second mask layer 202 is photoresist.

[0201] refer to Fig.13 , forming a charge trapping material layer 245 , a first blocking material layer 275 covering the charge trapping material layer 245 , and a control gate material layer 285 covering the first blocking material layer 275 .

[0202] Subsequently, the charge trapping material layer 245 is patterned to form a charge trapping layer for use as a second charge storage layer. Accordingly, in this embodiment, the material of the charge trapping material layer 245 is silicon nitride.

[0203] Specifically, in the step of forming the charge trapping material layer 245 , the charge trapping material layer 245 is formed on the first tunneling oxide layer 210 , the second tunneling oxide layer 220 , the floating gate and the third blocking layer 260 .

[0204] As an example, the floating gate and the third blocking layer 260 protrude on the first tunneling oxide layer 210, so the charge capture material layer 245 securely covers the first tunneling oxide layer 210, the second tunneling oxide layer 220, the floating gate and the third blocking layer 260, thereby improving the thickness uniformity of the charge capture material layer 245.

[0205] Subsequently, the first barrier material layer 275 is patterned to form a first barrier layer. Accordingly, in this embodiment, the material of the first barrier material layer 275 is silicon oxide.

[0206] As an example, the first blocking material layer 275 protectively covers the charge trapping material layer 245 , thereby improving the thickness uniformity of the first blocking material layer 275 .

[0207] The control gate is then formed by patterning the control gate material layer 285. Accordingly, in this embodiment, the material of the control gate material layer 285 is polysilicon.

[0208] In this embodiment, the charge capture material layer 245 , the first blocking material layer 275 and the control gate material layer 285 are formed by a furnace tube process.

[0209] refer to Fig.14 , patterning the control gate material layer 285, the first blocking material layer 275, the charge capture material layer 245 and the second tunneling oxide layer 220 to form a charge capture layer located on the remaining second tunneling oxide layer 220, a first blocking layer 270 located on the charge capture layer and the floating gate, and a control gate 280 located on the first blocking layer 270.

[0210] In the present embodiment, since a control gate 280 needs to be formed on both the first charge storage layer 230 and the second charge storage layer 240, and the second charge storage layer 240 is a charge capture layer, the second charge storage layer 240 can extend to cover the first charge storage layer 230. Therefore, after forming a charge capture material layer 245, a first blocking material layer 275 and a control gate material layer 285 stacked in sequence from bottom to top, a photomask can be used to sequentially pattern the control gate material layer 285, the first blocking material layer 275, the charge capture material layer 245 and the second tunneling oxide layer 220, thereby simplifying the process steps and reducing the process cost.

[0211] Specifically, the step of patterning the control gate material layer 285, the first blocking material layer 275 and the charge capture material layer 245 includes: forming a patterned third mask layer 203 on the control gate material layer 285, the third mask layer 203 covering the control gate material layer 285 at the position where the control gate is to be formed; using the third mask layer 203 as a mask, removing the control gate material layer 285, the first blocking material layer 275, the charge capture material layer 245, the second tunneling oxide layer 220, the third blocking layer 260, the first charge storage layer 230 and the first tunneling oxide layer 210 exposed by the third mask layer 203; and removing the third mask layer 203.

[0212] It should be noted that in the process of patterning the control gate material layer 285, the first blocking material layer 275, the charge capture material layer 245 and the second tunneling oxide layer 220, the third blocking layer 260, the first charge storage layer 230 and the first tunneling oxide layer 210 are also patterned to enable the normal operation of the storage unit corresponding to the floating gate.

[0213] It should also be noted that after patterning the charge capture material layer 245 and the first charge storage layer 230, the first tunneling oxide layer 210 and the second tunneling oxide layer 220 are further patterned to remove the first tunneling oxide layer 210 and the second tunneling oxide layer 220 exposed by the remaining control gate material layer 285 (that is, the control gate 280), so that the remaining first tunneling oxide layer 210 is formed between the first charge storage layer 210 and the substrate 200, and the remaining second tunneling oxide layer 220 is formed between the second charge storage layer 240 and the substrate 200.

[0214] In this embodiment, a dry etching process is used to pattern the control gate material layer 285, the first blocking material layer 275, the charge capture material layer 245, the third blocking layer 260, the first charge storage layer 230, the first tunneling oxide layer 210 and the second tunneling oxide layer 220 to improve the morphology quality of the floating gate, the charge capture layer, the first blocking layer 270, the control gate 280, the first tunneling oxide layer 210 and the second tunneling oxide layer 220.

[0215] As an example, the material of the third mask layer 203 is photoresist.

[0216] In this embodiment, the control gate 280 above the first charge storage layer 230 and the second charge storage layer 240 is an integrated structure, and the control gate 280 is shared by the first charge storage layer 230 and the second charge storage layer 240 .

[0217] The control gate 280 is shared by the first charge storage layer 230 and the second charge storage layer 240 , thereby eliminating the etching step of dividing the control gate 180 above the first charge storage layer 230 and the second charge storage layer 240 , thereby simplifying the process steps.

[0218] In other embodiments, after forming a control gate spanning the first charge storage layer and the second charge storage layer, the control gate may be segmented so that the segmented control gates correspond to the first charge storage layer and the second charge storage layer one by one.

[0219] refer to Fig.15 After forming the control gate 280, the formation method further includes: forming a sidewall 290 covering the sidewalls of the first tunneling oxide layer 210, the sidewalls of the second tunneling oxide layer 220, the sidewalls of the first charge storage layer 230, the sidewalls of the second charge storage layer 240, the sidewalls of the first blocking layer 270 and the sidewalls of the control gate 280 on the substrate 200 on both sides of the control gate 280.

[0220] Specifically, the sidewall spacer 290 also covers the sidewall of the third barrier layer 260 and the sidewall of the second barrier layer 250 .

[0221] The spacer 290 is used to protect the sidewalls of the charge storage layer, the blocking layer and the tunneling oxide layer, and is also used to define the positions of the source and drain doping regions.

[0222] The sidewall spacer 290 may be a single-layer structure or a stacked-layer structure, and the material of the sidewall spacer 290 includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride oxide, silicon nitride oxide, boron nitride and boron carbonitride.

[0223] It should be noted that, in other embodiments, after forming the sidewall spacer, the first tunneling oxide layer and the second tunneling oxide layer may be patterned to remove the first tunneling oxide layer and the second tunneling oxide layer exposed by the control gate and the sidewall spacer.

[0224] Continue to refer Fig.15 , source-drain doped regions 295 are formed in the substrate 200 on both sides of the first barrier layer 270 .

[0225] The source-drain doping region 295 is used to provide a source region and a drain region of the memory, thereby forming a memory.

[0226] In this embodiment, the second charge storage layer 240 and the first charge storage layer 230 share a source-drain doped region 295 .

[0227] Since the second charge storage layer 240 and the first charge storage layer 230 have different charge storage mechanisms and can be implemented in the same device, the second charge storage layer 240 and the first charge storage layer 230 can share the control gate 280 and the source-drain doping region 295 .

[0228] In this embodiment, the source-drain doping region 295 close to the first charge storage layer 230 is a first source-drain doping region 295s, and the source-drain doping region 295 close to the second charge storage layer 240 is a second source-drain doping region 295d. Specifically, the first charge storage layer 230 is a floating gate, and the second charge storage layer 240 is a charge trapping layer. Therefore, the first source-drain doping region 295s is a source region, and the second source-drain doping region 295d is a drain region. The source-drain doping region 295 can be formed by ion implantation, or by epitaxial process. The steps of forming the source-drain doping region 295 are not described in detail here.

[0229] In this embodiment, based on the working mechanism of the charge trapping layer, a portion of the top of the source / drain doped region 295 close to one side of the second charge storage layer 240 is covered by the second charge storage layer 240 .

[0230] In addition, for the working method of the memory formed by the formation method described in this embodiment, please refer to the relevant description in the aforementioned embodiment, which will not be repeated here.

[0231] Figures 16 to 19 It is a schematic structural diagram corresponding to each step in another embodiment of the method for forming a memory of the present invention.

[0232] The similarities between this embodiment and the above-mentioned embodiment are not repeated here. The difference between this embodiment and the above-mentioned embodiment is that after forming the first charge storage layer 430 on the first tunneling oxide layer 410, the third blocking layer 460 and the second tunneling oxide layer 420 are formed in the same step, and the third blocking layer 460 also covers the sidewall of the floating gate.

[0233] That is to say, in this embodiment, the first tunneling oxide layer 410 and the second tunneling oxide layer 420 are formed in different steps, and the two are separate from each other and are not an integrated structure.

[0234] In this embodiment, a barrier layer (ie, the third barrier layer 460 ) in a conventional floating gate structure memory is directly used to prepare the second tunneling oxide layer 420 , which not only has better process compatibility but also saves the process steps required to prepare the second tunneling oxide layer 420 .

[0235] In a specific embodiment, in a conventional floating gate structure memory, an ONO structure is usually used as a barrier layer between the floating gate and the control gate, and the third barrier layer 460 and the second tunneling oxide layer 420 are formed in the same step. Then, two layers of the ONO barrier layer in the conventional process can be used to form the second tunneling oxide layer 320 and the charge capture layer, respectively, without the need for adding a mask and process steps.

[0236] refer to Fig.16 and Fig.17 , a first tunneling oxide layer 410 is formed on the substrate 400 , and a first charge storage layer 430 is formed on the first tunneling oxide layer 410 .

[0237] Specifically, the steps of forming the first tunneling oxide layer 410 and the first charge storage layer 430 include: Fig.16 As shown, a first tunneling oxide material layer 415 is formed covering the substrate 400; a floating gate material layer 435 is formed covering the first tunneling oxide material layer; the floating gate material layer 435 and the first tunneling oxide material layer 415 are sequentially patterned to form a first tunneling oxide layer 410 and a first charge storage layer 430 located on the first tunneling oxide layer 410.

[0238] In this embodiment, the floating gate material layer 435 and the first tunneling oxide material layer 415 are patterned in sequence using the same mask layer to remove the floating gate material layer 435 and the first tunneling oxide material layer 415 at the position where the second charge storage layer is to be formed. Specifically, the floating gate material layer 435 and the first tunneling oxide material layer 415 are patterned in sequence using a dry etching process.

[0239] It should be noted that, before sequentially patterning the floating gate material layer 435 and the first tunneling oxide material layer 415 , the formation method may further include: performing a planarization process on the surface of the floating gate material layer.

[0240] refer to Fig.18 , forming a second tunneling oxide material layer 425 covering the first charge storage layer 430, the first tunneling oxide layer 410 and the substrate 400; forming a charge capture material layer 445 covering the second tunneling oxide material layer 425; forming a first blocking material layer 475 covering the charge capture material layer 445, and a control gate material layer 485 covering the first blocking material layer 475.

[0241] In this embodiment, the second tunneling oxide material layer 425 protectively covers the first charge storage layer 430 , the first tunneling oxide layer 410 and the substrate 400 .

[0242] As an example, the second tunneling oxide material layer 425 is formed by a furnace process.

[0243] refer to Fig.19 , the control gate material layer 485, the first blocking material layer 475, the charge trapping material layer 445, the second tunneling oxide material layer 425, the first charge storage layer 430 and the first tunneling oxide layer 410 are patterned in sequence.

[0244] Specifically, the second tunneling oxide material layer 425 located on a portion of the substrate 400 on one side of the first tunneling oxide layer 410 is retained as the second tunneling oxide layer 420, the second tunneling oxide material layer 425 located on the top of the first charge storage layer 430 is retained as the third blocking layer 460, the charge capture material layer 445 located on the top of the second tunneling oxide layer 420 is retained as the charge capture layer 440, the charge capture material layer 445 located on the top of the third blocking layer 460 is retained as the second blocking layer 450, the first blocking material layer 475 located on the second blocking layer 450 and the charge capture layer 440 is retained as the first blocking layer 470, and the control gate material layer 485 located on the first blocking layer 470 is retained as the control gate layer 480.

[0245] In this embodiment, the control gate material layer 485, the first blocking material layer 475, the charge capture material layer 445, the second tunneling oxide material layer 425, the first charge storage layer 430 and the first tunneling oxide layer 410 are patterned in sequence using the same mask layer. Specifically, the control gate material layer 485, the first blocking material layer 475, the charge capture material layer 445 and the second tunneling oxide material layer 425 are patterned in sequence using a dry etching process.

[0246] It should be noted that in other embodiments, according to actual needs, it can also be: in the step of forming the first tunneling oxide layer, a first sub-tunneling oxide layer is formed, and in the step of forming the third blocking layer, a second sub-tunneling oxide layer is formed, and the second sub-tunneling oxide layer and the first sub-tunneling oxide layer constitute the first tunneling oxide layer.

[0247] For the specific description of the method for forming the memory described in this embodiment, reference may be made to the relevant description of the method for forming the memory described in the previous embodiment, which will not be repeated here.

[0248] The semiconductor structure provided by the embodiment of the present invention can be formed by the formation method described in the above embodiment, or by other formation methods. For the specific description of the semiconductor structure described in the embodiment of the present invention, reference can be made to the corresponding description in the above embodiment.

[0249] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A memory, characterized in that: include: substrate; A first charge storage layer, located on the substrate; a second charge storage layer, located on the substrate at one side of the first charge storage layer and electrically isolated from the first charge storage layer, wherein the second charge storage layer and the first charge storage layer have different charge storage mechanisms; a first tunneling oxide layer, located between the first charge storage layer and the substrate; a second tunneling oxide layer, located between the second charge storage layer and the substrate; a first blocking layer, located on the first charge storage layer and the second charge storage layer; a control gate disposed on the first blocking layer above the first charge storage layer and the second charge storage layer; The source-drain doped regions are located in the substrate on both sides of the first barrier layer.

2. The memory according to claim 1, wherein: The first charge storage layer is a floating gate, and the second charge storage layer is a charge trapping layer; A portion of the top of the source-drain doped region close to one side of the second charge storage layer is covered by the second charge storage layer.

3. The memory according to claim 1 or 2, characterized in that: The substrate includes a channel region; The first charge storage layer covers a portion of the channel region, and the second charge storage layer covers the remaining channel region.

4. The memory according to claim 3, wherein: Along a direction perpendicular to the sidewall of the first charge storage layer, the lateral dimension of the channel region is a first dimension, and the lateral dimension of the channel region not covered by the first charge storage layer is a second dimension, and the ratio of the second dimension to the first dimension is 1 / 4 to 1 / 3.

5. The memory according to claim 2, wherein: The material of the floating gate includes one or more of polysilicon, single crystal silicon and high-K dielectric material; the material of the charge trapping layer includes one or more of silicon nitride and silicon oxynitride.

6. The memory according to claim 2, wherein: The charge trapping layer also covers the sidewall of the floating gate facing the charge trapping layer and the top of the floating gate, and the portion of the charge trapping layer located on the floating gate serves as a second blocking layer.

7. The memory according to claim 6, wherein: The memory further includes a third blocking layer located on a top of the floating gate and between the second blocking layer.

8. The memory according to claim 7, wherein: The third barrier layer is also located between the sidewall of the floating gate and the second barrier layer, and the third barrier layer and the second tunneling oxide layer are an integrated structure.

9. The memory according to claim 7, wherein: The material of the third barrier layer includes one or more of silicon oxide, silicon nitride and silicon oxynitride.

10. The memory according to claim 7, wherein: The material of the first barrier layer is silicon oxide, the material of the second barrier layer is silicon nitride, and the material of the third barrier layer is silicon oxide.

11. The memory according to claim 1, wherein: A programming voltage value of the second charge storage layer is smaller than a programming voltage value of the first charge storage layer, and a thickness of the second tunneling oxide layer is smaller than a thickness of the first tunneling oxide layer.

12. The memory according to claim 1, 2 or 11, characterized in that: The first tunneling oxide layer and the second tunneling oxide layer are an integrated structure.

13. The memory according to claim 1, wherein: The material of the first barrier layer includes one or more of silicon oxide, silicon nitride and silicon oxynitride.

14. The memory according to claim 1, wherein: The control gate above the first charge storage layer and the second charge storage layer is an integrated structure, and the control gate is shared by the first charge storage layer and the second charge storage layer.

15. A method for forming a memory, characterized in that: include: providing a substrate; forming a first tunneling oxide layer and a second tunneling oxide layer on the substrate, wherein the second tunneling oxide layer is located on one side of the first tunneling oxide layer; forming a first charge storage layer on the first tunneling oxide layer, and forming a second charge storage layer on the second tunneling oxide layer, wherein the second charge storage layer is electrically isolated from the first charge storage layer, and the second charge storage layer and the first charge storage layer have different charge storage mechanisms; forming a first blocking layer on the first charge storage layer and the second charge storage layer; forming a control gate on the first blocking layer above the first charge storage layer and the second charge storage layer; Source and drain doped regions are formed in the substrate at both sides of the first barrier layer.

16. The method for forming a memory according to claim 15, wherein: The first charge storage layer is a floating gate, and the second charge storage layer is a charge trapping layer; In the step of forming source-drain doped regions in the substrate on both sides of the first blocking layer, a portion of the top of the source-drain doped region close to one side of the second charge storage layer is covered by the second charge storage layer.

17. The method for forming a memory according to claim 15 or 16, characterized in that: In the step of providing a substrate, the substrate includes a channel region; In the step of forming a first tunneling oxide layer and a second tunneling oxide layer on the substrate, the first tunneling oxide layer covers a portion of the channel region, and the second tunneling oxide layer covers the remaining channel region.

18. The method for forming a memory according to claim 16, wherein: In the step of forming the charge trapping layer, the charge trapping layer also covers the sidewall of the floating gate facing the charge trapping layer and the top of the floating gate, and the portion of the charge trapping layer located on the floating gate serves as a second blocking layer.

19. The method for forming a memory according to claim 18, wherein: Before forming the charge trapping layer, the forming method further includes: forming a third blocking layer on the top of the floating gate.

20. The method for forming a memory according to claim 19, wherein: The step of forming the floating gate and the third barrier layer includes: forming a floating gate material layer and a third barrier material layer covering the floating gate material layer; The third barrier material layer and the floating gate material layer are patterned to form a floating gate and a third barrier layer located on the top of the floating gate.

21. The method for forming a memory according to any one of claims 18 to 20, characterized in that: The step of forming the charge capture layer, the first blocking layer and the control gate comprises: forming a charge capture material layer, a first blocking material layer covering the charge capture material layer, and a control gate material layer covering the first blocking material layer; The control gate material layer, the first blocking material layer and the charge trapping material layer are patterned to form a charge trapping layer on the second tunneling oxide layer, a first blocking layer on the charge trapping layer and the floating gate, and a control gate on the first blocking layer.

22. The method for forming a memory according to claim 19, wherein: After forming a first charge storage layer on the first tunneling oxide layer, the third blocking layer and the second tunneling oxide layer are formed in the same step, and the third blocking layer also covers the sidewall of the floating gate.

23. The method for forming a memory according to claim 15 or 16, characterized in that: The programming voltage value of the second charge storage layer is less than the programming voltage value of the first charge storage layer; Before forming the first tunneling oxide layer and the second tunneling oxide layer, the method further includes: doping growth inhibiting ions into the surface of the substrate at a location where the second charge storage layer is to be formed to form an inhibiting ion doping region; The step of forming a first tunneling oxide layer and a second tunneling oxide layer on the substrate includes: in the same step, forming the first tunneling oxide layer on the substrate without the ion doping inhibition zone, and forming the second tunneling oxide layer on the substrate with the ion doping inhibition zone, wherein the thickness of the second tunneling oxide layer is less than the thickness of the first tunneling oxide layer.

24. The method for forming a memory according to claim 23, wherein: The growth-inhibiting ions include nitrogen ions; The process of doping the growth inhibiting ions into the substrate surface includes an ion implantation process, and the parameters of the ion implantation process include: an implantation energy of 28KeV to 35KeV, and an implantation dose of 1E16 atoms per square centimeter to 1E14 atoms per square centimeter.

25. The method for forming a memory according to claim 15, wherein: In the step of forming the control gate, the control gate above the first charge storage layer and the second charge storage layer is an integrated structure, and the control gate is shared by the first charge storage layer and the second charge storage layer.

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