Preparation method of flash memory device

Abstract

The invention provides a preparation method of a flash memory device, and the method comprises the steps: carrying out the at least two times of inclined ion implantation technology on the surface of an isolation structure exposed out of a peripheral logic region before a gate oxide layer is prepared, so as to enable the vertex angles (the edge of an active region) of two sides of the isolation structure of the peripheral logic region to be in complete contact with implanted doped ions, the ion concentration distribution of the edge region of the active region is improved, Si vacancies exist in bonds formed by Si-doped ions, and the vacancies are beneficial to the oxidation reaction on a SiO2 / Si interface, so that in the subsequent process of preparing a gate oxide layer by a high-temperature furnace tube oxidation process, the yield of the gate oxide layer is improved. The growth speed of the gate oxide layer at the vertex angles of the two sides of the isolation structure is greater than that of the gate oxide layer on the substrate surface far away from the vertex angles of the isolation structure, so that the growth of the gate oxide layer at the edge of the active region is thickened, and the electric field distribution at the edge of the active region is reduced; therefore, the morphology and contour of the gate oxide layer close to the vertex angles at the two sides of the isolation structure and the TDDB performance of the device are improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor manufacturing technology, and in particular to a method for preparing a flash memory device. Background Art

[0002] In the preparation of flash memory devices, the FG-first (floating gate preparation first) technical route is because the floating gate is prepared before the final STI (shallow trench isolation structure). STI is usually composed of an isolation structure and a pad oxide layer. The pad oxide layer on the surface of the isolation structure usually adopts a double-layer oxide layer. However, this can easily cause the floating gate in the storage area to be over-oxidized (consumed by mis-oxidation), resulting in a reduction in the coupling ratio (coupling coefficient), affecting the performance of the storage area device of the flash memory device.

[0003] In addition, if a single-layer oxide layer is used as the liner oxide layer on the surface of the isolation structure, the peripheral logic area will have a thin gate oxide at the corners of the active area due to insufficient corner rounding of the isolation structure, which can easily cause the electric field at the edge of the active area to be too large, and ultimately cause the TDDB (time-dependent dielectric breakdown) of the high-voltage PMOS (such as 5VPMOS) to have a risk of failure. Summary of the invention

[0004] The present application provides a method for preparing a flash memory device, which can solve at least one of the problems in the traditional flash memory device preparation process, namely, that the floating gate of the storage area is over-oxidized, affecting the coupling coefficient, and that the gate oxide layer at the top corner position of the active area / isolation structure (shallow trench isolation structure) in the peripheral area is too thin, thereby affecting the TDDB performance of the device.

[0005] The present invention provides a method for preparing a flash memory device, comprising:

[0006] A substrate is provided, the substrate comprising a storage area and a peripheral logic area, a pad oxide layer and a floating gate material layer are sequentially formed on the surface of the substrate, wherein a plurality of isolation structures are formed in the floating gate material layer, the pad oxide layer and a part of the thickness of the substrate;

[0007] Etching and removing a certain thickness of the isolation structure in the storage area, wherein the remaining thickness of the isolation structure in the storage area protrudes from the surface of the substrate by a certain height;

[0008] Forming an ONO dielectric layer, wherein the ONO dielectric layer covers the floating gate material layer and the isolation structure of the storage area, and the floating gate material layer and the isolation structure of the peripheral logic area;

[0009] Etching and removing the ONO dielectric layer, the floating gate material layer, the isolation structure of a certain thickness and the liner oxide layer in the peripheral logic area;

[0010] Coating a photoresist layer on the ONO dielectric layer in the storage area and on the substrate surface and isolation structure in the peripheral logic area;

[0011] Defining an opening pattern for ion implantation on the photoresist layer to obtain a patterned photoresist layer, wherein the patterned photoresist layer opens an isolation structure of the peripheral logic area;

[0012] Using the patterned photoresist layer as a mask, performing at least two ion tilt implantation processes on the surface of the isolation structure exposed in the peripheral logic region, so that both side corners of the isolation structure in the peripheral logic region are completely in contact with the implanted doping ions;

[0013] removing the patterned photoresist layer; and

[0014] A gate oxide layer is formed on the surface of the substrate in the peripheral logic region by a high temperature furnace tube oxidation process, wherein the thickness of the gate oxide layer close to the top corners on both sides of the isolation structure is greater than the thickness of the gate oxide layer away from the top corners of the isolation structure.

[0015] Optionally, in the preparation method of the flash memory device, during the process of performing at least two tilted ion implantation processes on the surface of the isolation structure exposed in the peripheral logic area using the patterned photoresist layer as a mask, at least one tilted N-type ion implantation is performed tilted toward the left side and at least one tilted N-type ion implantation is performed tilted toward the right side, so that the left side top corner and the right side top corner of the isolation structure in the peripheral logic area are completely in contact with the injected doped ions.

[0016] Optionally, in the method for preparing the flash memory device, in the process of performing N-type ion tilted implantation by tilting the surface of the isolation structure exposed in the peripheral logic area to the left with the patterned photoresist layer as a mask, the tilt angle is 0° to 15°; the ion implantation energy is 8Kev to 15Kev; and the ion implantation dose is 1E13 / cm 2 ~1E15 / cm 2 .

[0017] Optionally, in the method for preparing the flash memory device, in the process of performing N-type ion tilted implantation by tilting the surface of the isolation structure exposed in the peripheral logic area to the right with the patterned photoresist layer as a mask, the tilt angle is 0° to 15°; the ion implantation energy is 8Kev to 15Kev; and the ion implantation dose is 1E13 / cm 2 ~1E15 / cm 2 .

[0018] Optionally, in the method for preparing the flash memory device, the ion concentration at the top corners on both sides of the isolation structure is greater than the ion concentration on the upper surface of the isolation structure.

[0019] Optionally, in the preparation method of the flash memory device, in the process of forming a gate oxide layer on the surface of the substrate in the peripheral logic area through a high-temperature furnace tube oxidation process, the process temperature is 700°C to 900°C, and the oxygen flow rate is 1sccm to 3sccm.

[0020] Optionally, in the method for preparing the flash memory device, the thickness of the gate oxide layer near the top corners on both sides of the isolation structure is The thickness of the gate oxide layer away from the top corner of the isolation structure is

[0022] Optionally, in the method for preparing the flash memory device, after forming a gate oxide layer on the surface of the isolation structure in the peripheral logic area and the surface of the substrate by a high-temperature furnace tube oxidation process, the method for preparing the flash memory device further includes:

[0023] Forming a gate material layer, wherein the gate material layer covers the gate oxide layer, the isolation structure of the peripheral logic area and the ONO dielectric layer of the storage area;

[0024] The gate material layer is etched to define the gate of the peripheral logic area.

[0025] The technical solution of this application has at least the following advantages:

[0026] The present application provides a method for preparing a flash memory device. Before preparing a gate oxide layer, at least two ion tilt implantation processes are performed on the surface of the isolation structure exposed in the peripheral logic region, so that both side corners of the isolation structure in the peripheral logic region (edges of the active region) are completely in contact with the implanted doped ions, and the ion concentration distribution in the edge region of the active region is improved. Si vacancies exist in Si-doped ion (e.g., Si-P) bonds, and the vacancies are conducive to oxidation reactions on the SiO2 / Si interface, so that in the subsequent high-temperature furnace tube oxidation process for preparing the gate oxide layer, the growth rate of the gate oxide layer at the two side corners of the isolation structure is greater than the growth rate of the gate oxide layer on the substrate surface away from the two side corners of the isolation structure, so that the gate oxide layer at the two side corners of the isolation structure (edges of the active region) grows thicker, and then reduces the electric field distribution at the edge of the active region (the electric field at the edge of the active region is weakened), thereby improving the TDDB performance of the device, and improving the morphology and profile of the gate oxide layer near the two side corners of the isolation structure, that is, improving the morphology and profile of the final two side corners of the STI. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0028] Figure 1 is a flow chart of a method for preparing a flash memory device according to an embodiment of the present invention;

[0029] Figure 2-Figure 7 is a schematic diagram of a semiconductor structure in each process step of preparing a flash memory device according to an embodiment of the present invention;

[0030] The reference numerals are described as follows:

[0031] 10 - substrate, 11 - isolation structure, 20 - pad oxide layer, 30 - floating gate material layer, 40 - ONO dielectric layer, 50 - photoresist layer, 60 - gate oxide layer. DETAILED DESCRIPTION

[0032] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in this application. Obviously, the described embodiments are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0033] In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present application. In addition, the terms "first", "second", and "third" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance.

[0034] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, it can also be the internal connection of two components, it can be a wireless connection, or it can be a wired connection. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0035] In addition, the technical features involved in the different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.

[0036] The present application provides a method for preparing a flash memory device, referring to Figure 1 , Figure 1 1 is a flow chart of a method for preparing a flash memory device according to an embodiment of the present invention, wherein the method for preparing a flash memory device comprises:

[0037] First, perform step S1: refer to Figure 2 , Figure 2 It is a schematic diagram of a semiconductor structure after an isolation structure is formed in an embodiment of the present application, and a substrate 10 is provided, wherein the substrate 10 includes a storage area and a peripheral logic area, and a pad oxide layer 20 and a floating gate material layer 30 are sequentially formed on the surface of the substrate 10, wherein a plurality of isolation structures 11 are formed in the floating gate material layer 30, the pad oxide layer 20 and a partial thickness of the substrate 10.

[0038] In the peripheral logic region, the substrate 10 between the isolation structures 11 is an active region.

[0039] Then, execute step S2: refer to Figure 3 , Figure 3 This is a schematic diagram of the semiconductor structure after etching away a certain thickness of the isolation structure of the storage area according to an embodiment of the present application, a layer of photoresist is coated on the surface of the isolation structure 11 and the floating gate material layer 30, an opening pattern for etching the isolation structure of a certain thickness in the storage area is defined on the photoresist, and then, using the photoresist after forming the opening pattern as a mask, etching away a certain thickness of the isolation structure 11 of the storage area, wherein the remaining thickness of the isolation structure 11 of the storage area protrudes a certain height from the surface of the substrate 10.

[0040] In this embodiment, during the process of etching away a certain thickness of the isolation structure 11 of the storage area, a plurality of storage area trenches are formed in the floating gate material layer 30 .

[0041] Next, execute step S3: refer to Figure 4 , Figure 4 It is a schematic diagram of the semiconductor structure after the ONO dielectric layer is formed in an embodiment of the present application, wherein an ONO dielectric layer 40 is formed, wherein the ONO dielectric layer 40 covers the floating gate material layer 30 of the storage area and the sidewalls and bottom walls of the storage area trench, as well as the isolation structure 11 covering the bottom wall of the storage area, and the floating gate material layer 30 and the isolation structure 11 of the peripheral logic area.

[0042] Further, step S4 is performed: refer to Figure 5 , Figure 5It is a schematic diagram of the semiconductor structure after the ONO dielectric layer, the floating gate material layer, the isolation structure of a certain thickness and the pad oxide layer of the peripheral logic area are etched away in an embodiment of the present application. The ONO dielectric layer 40, the floating gate material layer 30, the isolation structure 11 of a certain thickness and the pad oxide layer 20 of the peripheral logic area are etched away.

[0043] Preferably, a dry etching process or a wet etching process may be used to etch and remove the ONO dielectric layer 40 , the floating gate material layer 30 , the isolation structure 11 of a certain thickness, and the liner oxide layer 20 in the peripheral logic region.

[0044] Next, execute step S5: refer to Figure 6(a) and Figure 6(b), Figure 6(a) is a schematic diagram of the semiconductor structure of an embodiment of the present application in which the first ion tilted implantation process is performed on the surface of the isolation structure exposed in the peripheral logic area, and Figure 6(b) is a schematic diagram of the semiconductor structure of an embodiment of the present application in which the second ion tilted implantation process is performed on the surface of the isolation structure exposed in the peripheral logic area, and a photoresist layer 50 is coated on the ONO dielectric layer 40 in the storage area and on the surface of the substrate 10 and the isolation structure 11 in the peripheral logic area.

[0045] Further, step S6 is performed: defining an opening pattern for ion implantation on the photoresist layer 50 to obtain a patterned photoresist layer 50 , wherein the patterned photoresist layer 50 opens the isolation structure 11 of the peripheral logic area.

[0046] Next, execute step S7: continue to refer to Figure 6(a) and Figure 6(b), use the patterned photoresist layer 50 as a mask, and perform at least two ion tilted implantation processes on the surface of the isolation structure exposed in the peripheral logic area, so that the top corners on both sides of the isolation structure of the peripheral logic area are completely in contact with the injected doping ions.

[0047] Preferably, in the process of performing at least two ion tilted implantation processes on the surface of the isolation structure 11 exposed in the peripheral logic area using the patterned photoresist layer as a mask, at least one N-type ion tilted implantation is performed tilted toward the left side and at least one N-type ion tilted implantation is performed tilted toward the right side, so that the left side top corner and the right side top corner of the isolation structure in the peripheral logic area are completely in contact with the injected doped ions.

[0048] As shown in FIG. 6( b ), in the process of tilting the surface of the isolation structure exposed in the peripheral logic area to the left with the patterned photoresist layer as a mask for N-type ion tilting injection, the tilt angle β is 0° to 15°; the ion injection energy is 8Kev to 15Kev; and the ion injection dose is 1E13 / cm 2 ~1E15 / cm 2 .

[0049] Further, as shown in FIG6(a), in the process of performing N-type ion tilting implantation by tilting the surface of the isolation structure exposed in the peripheral logic area to the right with the patterned photoresist layer as a mask, the tilting angle α is 0° to 15°; the ion implantation energy is 8Kev to 15Kev; and the ion implantation dose is 1E13 / cm 2 ~1E15 / cm 2 .

[0050] In this embodiment, the patterned photoresist layer is used as a mask to perform phosphorus (P) ion tilting injection at least once toward the left and at least once toward the right on the surface of the isolation structure exposed in the peripheral logic region.

[0051] Preferably, the ion concentration at the top corners on both sides of the isolation structure 11 is greater than the ion concentration on the upper surface of the isolation structure away from the top corners of the isolation structure.

[0052] Further, step S8 is performed: refer to Figure 7 , Figure 7 It is a schematic diagram of the semiconductor structure after the gate oxide layer is formed according to an embodiment of the present application, and the patterned photoresist layer 50 is removed.

[0053] In this embodiment, the patterned photoresist layer 50 may be removed by an ashing process.

[0054] Finally, step S9 is performed: a gate oxide layer 60 is formed on the surface of the substrate in the peripheral logic area through a high-temperature furnace tube oxidation process, wherein the thickness of the gate oxide layer 60 on the surface of the substrate 10 close to the top corners on both sides of the isolation structure is greater than the thickness of the gate oxide layer 60 on the surface of the substrate 10 away from the top corners of the isolation structure 11.

[0055] Preferably, in the process of forming the gate oxide layer 60 on the surface of the substrate 10 in the peripheral logic region by a high temperature furnace tube oxidation process, the process temperature is 700° C. to 900° C., and the flow rate of oxygen is 1 sccm to 3 sccm.

[0056] In this embodiment, the thickness of the gate oxide layer 60 near the top corners of the isolation structure is The thickness of the gate oxide layer 60 away from the top corner of the isolation structure 11 is

[0057] The present application performs at least two ion tilted implantation processes in different directions on the surface of the isolation structure exposed in the peripheral logic region before preparing the gate oxide layer, so that the two side corners of the isolation structure in the peripheral logic region (edge ​​of the active region) are completely in contact with the implanted doped ions, thereby improving the ion concentration distribution in the edge region of the active region, and Si vacancies exist in the Si-doped ion bonds (such as Si-P bonds). The vacancies are conducive to oxidation reactions on the SiO2 / Si interface, so that in the subsequent high-temperature furnace tube oxidation process for preparing the gate oxide layer, the growth rate of the gate oxide layer at the two side corners of the isolation structure is greater than the growth rate of the gate oxide layer on the substrate surface away from the top corners of the isolation structure, so that the single-layer gate oxide layer at the two side corners of the isolation structure (edge ​​of the active region) grows thicker, thereby reducing the electric field distribution at the edge of the active region (the electric field at the edge of the active region is weakened), thereby improving the TDDB performance of the device, and improving the morphology and contour of the gate oxide layer close to the two side corners of the isolation structure, that is, improving the morphology and contour of the final two side corners of the STI.

[0058] Furthermore, after forming a gate oxide layer 60 on the surface of the isolation structure 11 of the peripheral logic region and the surface of the substrate 10 by a high-temperature furnace tube oxidation process, the method for preparing the flash memory device may further include:

[0059] Step S10: forming a gate material layer (not shown), wherein the gate material layer covers the gate oxide layer and the isolation structure of the peripheral logic area and the ONO dielectric layer of the storage area; and

[0060] Step S11: etching the gate material layer to define the gate of the peripheral logic area, wherein the gate of the peripheral logic area is the gate of the MOS device; and the gate material layer deposited in the storage area serves as the control gate of the flash memory unit.

[0061] Obviously, the above embodiments are merely examples for the purpose of clear explanation, and are not intended to limit the implementation methods. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived therefrom are still within the scope of protection created by this application.

Claims

1. A method for preparing a flash memory device, characterized in that: include: A substrate is provided, the substrate comprising a storage area and a peripheral logic area, a pad oxide layer and a floating gate material layer are sequentially formed on the surface of the substrate, wherein a plurality of isolation structures are formed in the floating gate material layer, the pad oxide layer and a part of the thickness of the substrate; Etching and removing a certain thickness of the isolation structure in the storage area, wherein the remaining thickness of the isolation structure in the storage area protrudes from the surface of the substrate by a certain height; Forming an ONO dielectric layer, wherein the ONO dielectric layer covers the floating gate material layer and the isolation structure of the storage area, and the floating gate material layer and the isolation structure of the peripheral logic area; Etching and removing the ONO dielectric layer, the floating gate material layer, the isolation structure of a certain thickness and the liner oxide layer in the peripheral logic area; Coating a photoresist layer on the ONO dielectric layer in the storage area and on the substrate surface and isolation structure in the peripheral logic area; Defining an opening pattern for ion implantation on the photoresist layer to obtain a patterned photoresist layer, wherein the patterned photoresist layer opens an isolation structure of the peripheral logic area; Using the patterned photoresist layer as a mask, performing at least two ion tilt implantation processes on the surface of the isolation structure exposed in the peripheral logic region, so that both side corners of the isolation structure in the peripheral logic region are completely in contact with the implanted doping ions; removing the patterned photoresist layer; and A gate oxide layer is formed on the surface of the substrate in the peripheral logic region by a high temperature furnace tube oxidation process, wherein the thickness of the gate oxide layer close to the top corners on both sides of the isolation structure is greater than the thickness of the gate oxide layer away from the top corners of the isolation structure.

2. The method for preparing a flash memory device according to claim 1, wherein: In the process of performing at least two ion tilted implantation processes on the surface of the isolation structure exposed in the peripheral logic area using the patterned photoresist layer as a mask, at least one N-type ion tilted implantation is performed tilted to the left and at least one N-type ion tilted implantation is performed tilted to the right, so that the left and right top corners of the isolation structure in the peripheral logic area are completely in contact with the injected doped ions.

3. The method for preparing a flash memory device according to claim 2, wherein: In the process of performing N-type ion tilting implantation by using the patterned photoresist layer as a mask and tilting the surface of the isolation structure exposed in the peripheral logic area to the left, the tilting angle is 0° to 15°; the ion implantation energy is 8Kev to 15Kev; and the ion implantation dose is 1E13 / cm 2 ~1E15 / cm 2 .

4. The method for preparing a flash memory device according to claim 2, wherein: In the process of performing N-type ion tilting implantation by using the patterned photoresist layer as a mask and tilting the surface of the isolation structure exposed in the peripheral logic area to the right, the tilting angle is 0° to 15°; the ion implantation energy is 8Kev to 15Kev; and the ion implantation dose is 1E13 / cm 2 ~1E15 / cm 2 .

5. The method for preparing a flash memory device according to claim 1, wherein: The ion concentration at the top corners on both sides of the isolation structure is greater than the ion concentration on the upper surface of the isolation structure.

6. The method for preparing a flash memory device according to claim 1, characterized in that: In the process of forming a gate oxide layer on the surface of the substrate in the peripheral logic area through a high-temperature furnace tube oxidation process, the process temperature is 700° C. to 900° C., and the flow rate of oxygen is 1 sccm to 3 sccm.

7. The method for preparing a flash memory device according to claim 1, characterized in that: The thickness of the gate oxide layer near the top corners of the isolation structure is The thickness of the gate oxide layer away from the top corner of the isolation structure is 8. The method for preparing a flash memory device according to claim 1, wherein: After forming a gate oxide layer on the surface of the isolation structure in the peripheral logic area and the surface of the substrate by a high-temperature furnace tube oxidation process, the method for preparing the flash memory device further includes: Forming a gate material layer, wherein the gate material layer covers the gate oxide layer, the isolation structure of the peripheral logic area and the ONO dielectric layer of the storage area; The gate material layer is etched to define the gate of the peripheral logic area.

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