Super-junction fast-recovery planar gate silicon carbide VDMOS and preparation method thereof

Abstract

The invention provides a super-junction fast-recovery planar gate silicon carbide VDMOS and a preparation method thereof, metal is deposited on the lower side surface of a silicon carbide substrate to form a drain metal layer, and a drift layer is formed on the upper side surface of the silicon carbide substrate through epitaxial growth; forming a barrier layer, etching, performing ion implantation, and forming a diffusion region, a follow current region and an N-type source region; re-forming a barrier layer, etching the barrier layer to form a through hole, and depositing to form a gate dielectric layer; a barrier layer is formed again, the barrier layer is etched to form a through hole, metal is deposited, and a gate metal layer is formed; the preparation method comprises the following steps: re-forming a barrier layer, etching the barrier layer to form a through hole, depositing metal, forming a source metal layer, removing the barrier layer, and completing preparation, so that a super junction structure constructed by a P-type diffusion region and an N-type current sharing region is constructed in the device, the voltage endurance capability of the device can be effectively improved under the conditions of fixed thickness and area, and a Schottky diode is constructed; the reverse recovery time of the device can be effectively reduced, and fast recovery is realized.

Description

Technical Field

[0001] The invention relates to a super junction fast recovery planar gate silicon carbide VDMOS and a preparation method thereof. Background Art

[0002] Silicon carbide VDMOS is a typical representative of silicon carbide power devices, and is widely used in electric vehicles, aerospace, power conversion and other fields. For silicon carbide power VDMOS, different fields have different requirements for device performance, but the overall requirements include higher voltage resistance, lower on-resistance, faster switching speed, higher reliability (including gate reliability, drain voltage impact reliability, short-circuit reliability, etc.), and lower body diode conduction loss; the existing VDMOS needs to be further improved in voltage resistance, and its reverse recovery time is relatively long, which urgently needs to be further improved. Summary of the invention

[0003] The technical problem to be solved by the present invention is to provide a super-junction fast recovery planar gate silicon carbide VDMOS and a preparation method thereof, wherein a super-junction structure composed of a P-type diffusion region and an N-type current equalizing region is constructed inside the device, which can effectively improve the voltage resistance of the device under fixed thickness and area conditions, and construct a Schottky diode, which can effectively reduce the reverse recovery time of the device and achieve fast recovery.

[0004] In a first aspect, the present invention provides a method for preparing a super junction fast recovery planar gate silicon carbide VDMOS, comprising the following steps:

[0005] Step 1: depositing metal on the lower side of the silicon carbide substrate to form a drain metal layer, and epitaxially growing on the side of the silicon carbide substrate to form a drift layer;

[0006] Step 2: forming a barrier layer above the drift layer, etching the barrier layer to form a through hole, and implanting ions into the drift layer to form a diffusion region;

[0007] Step 3, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, and performing ion implantation into the drift layer to form a freewheeling region;

[0008] Step 4, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, and performing ion implantation into the diffusion region to form an N-type source region;

[0009] Step 5, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, and depositing to form a gate dielectric layer;

[0010] Step 6: remove the original barrier layer, re-form the barrier layer, etch the barrier layer to form a through hole, deposit metal, and form a gate metal layer;

[0011] Step 7: remove the original barrier layer, re-form the barrier layer, etch the barrier layer to form a through hole, deposit metal to form a source metal layer, remove the barrier layer, and complete the preparation.

[0012] In a second aspect, the present invention provides a super junction fast recovery planar gate silicon carbide VDMOS, wherein the silicon carbide VDMOS is prepared by the method for preparing a super junction fast recovery planar gate silicon carbide VDMOS described in the first aspect.

[0013] The advantages of the present invention are:

[0014] 1. The present invention constructs a super junction structure of the device by constructing a diffusion region and a freewheeling region in the drift layer, thereby changing the longitudinal withstand voltage of the device to a structure that withstands both longitudinal and lateral withstand voltages, i.e., a super junction structure, to improve the withstand voltage capability of devices with the same thickness and width;

[0015] Second, the direct Schottky contact between the source metal layer and the drift layer of the present invention can form a parasitic Schottky body diode of the device, thereby improving the reverse recovery speed of the device, reducing the reverse recovery time, and improving the switching speed of the device;

[0016] 3. The diffusion region of the device that constitutes the super junction structure completely surrounds the N-type source region, so no additional well region process is required, which can effectively reduce the complexity of the device preparation process and reduce the device manufacturing cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The present invention will be further described below in conjunction with embodiments with reference to the accompanying drawings.

[0018] Figure 1 The schematic diagram of a superjunction fast recovery planar gate silicon carbide VDMOS of the present invention is shown.

[0019] Figure 2 This is a cross-sectional view of the process of a super-junction fast recovery planar gate silicon carbide VDMOS of the present invention. Figure 1 .

[0020] Figure 3 This is a cross-sectional view of the process of a super-junction fast recovery planar gate silicon carbide VDMOS of the present invention. Figure 2 .

[0021] Figure 4 This is a cross-sectional view of the process of a super-junction fast recovery planar gate silicon carbide VDMOS of the present invention. Figure 3 .

[0022] Figure 5 This is a cross-sectional view of the process of a super-junction fast recovery planar gate silicon carbide VDMOS of the present invention. Figure 4 .

[0023] Figure 6This is a cross-sectional view of the process of a super-junction fast recovery planar gate silicon carbide VDMOS of the present invention. Figure 5 .

[0024] Figure 7 This is a cross-sectional view of the process of a super-junction fast recovery planar gate silicon carbide VDMOS of the present invention. Figure 6 .

[0025] Figure 8 This is a cross-sectional view of the process of a super-junction fast recovery planar gate silicon carbide VDMOS of the present invention. Figure 7 . DETAILED DESCRIPTION

[0026] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0027] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0028] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "in contact with ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer, doping type or part discussed below can be represented as a second element, component, region, layer or part.

[0029] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of one element or feature described in the figures to other elements or features. It should be understood that, in addition to the orientations described in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0030] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the relevant listed items.

[0031] like Figures 1 to 8 As shown, the embodiment of the present application provides a method for preparing a super junction fast recovery planar gate silicon carbide VDMOS, comprising the following steps:

[0032] Step 1: depositing metal on the lower side of the silicon carbide substrate 1 to form a drain metal layer 8, and epitaxially growing a drift layer 2 on the upper side of the silicon carbide substrate 1;

[0033] Step 2, forming a barrier layer 9 on the drift layer 2, etching the barrier layer 9 to form a through hole, and performing ion implantation into the drift layer 2 to form a diffusion region 3;

[0034] Step 3, removing the original barrier layer 9, re-forming the barrier layer 9, etching the barrier layer 9 to form a through hole, and performing ion implantation into the drift layer 2 to form a freewheeling region 4;

[0035] Step 4, removing the original barrier layer 9, re-forming the barrier layer 9, etching the barrier layer 9 to form a through hole, and performing ion implantation into the diffusion region 3 to form an N-type source region 31;

[0036] Step 5, removing the original barrier layer 9, re-forming the barrier layer 9, etching the barrier layer 9 to form a through hole, and depositing to form a gate dielectric layer 5;

[0037] Step 6, removing the original barrier layer 9, re-forming the barrier layer 9, etching the barrier layer 9 to form a through hole, depositing metal, and forming a gate metal layer 6;

[0038] Step 7, remove the original barrier layer 9, re-form the barrier layer 9, etch the barrier layer 9 to form a through hole, deposit metal to form a source metal layer 8, remove the barrier layer 9, and complete the preparation.

[0039] In this embodiment, preferably, the doping concentration of the N-type source region 31 is greater than the doping concentration of the diffusion region 3 , and the doping concentration of the diffusion region 3 is greater than the doping concentration of the drift layer 2 .

[0040] In this embodiment, preferably, the total width of the diffusion region 3 is 40% of the width of the drift layer 2 .

[0041] In this embodiment, preferably, the width of the freewheeling region 4 is 20% of the width of the drift layer 2 .

[0042] In this embodiment, preferably, the distance between the inner side surface of the N-type source region 31 and the inner side surface of the diffusion region 3 is 20 nm.

[0043] In this embodiment, preferably, the distance between the inner side surface of the diffusion region 3 and the outer side surface of the freewheeling region 4 is 5% of the width of the drift layer 2 .

[0044] like Figure 1 As shown, the silicon carbide VDMOS obtained by the above manufacturing method includes:

[0045] Silicon carbide substrate 1,

[0046] A drift layer 2, wherein the lower side of the drift layer 2 is connected to the silicon carbide substrate 1;

[0047] A diffusion region 3, wherein the diffusion region 3 is disposed in the drift layer 2 and penetrates the drift layer 2, the lower side of the diffusion region 3 is connected to the upper side of the silicon carbide substrate 1, and an N-type source region 31 is disposed on the diffusion region 3;

[0048] A freewheeling region 4, wherein the freewheeling region 4 is disposed in the drift layer 2 and penetrates the drift layer 2, and a lower side of the freewheeling region 4 is connected to an upper side of the silicon carbide substrate 1;

[0049] A gate dielectric layer 5, the lower side of which is respectively connected to the drift layer 2, the freewheeling region 4 and the diffusion region 3;

[0050] A gate metal layer 6, wherein the gate metal layer 6 is connected to the gate dielectric layer 5;

[0051] A source metal layer 7, the lower side of the source metal layer 7 is connected to the drift layer 2, the diffusion region 3 and the N-type source region 31;

[0052] and a drain metal layer 8 , wherein the drain metal layer 8 is connected to the silicon carbide substrate 1 .

[0053] In another embodiment of the present invention, the silicon carbide substrate 1, the drift layer 2 and the freewheeling region 4 are all N-type; the diffusion region 3 is P-type; the doping concentration of the silicon carbide substrate 1 is 2-8e18cm -3 , the doping concentration of the N-type drift layer 2 is 1-5e17cm -3 , the doping concentration of the P-type diffusion region 3 is 1-5e18cm -3 , the doping concentration of the N-type freewheeling region 4 is 1-2e18cm -3 The gate dielectric layer 5 is silicon dioxide, and the doping concentration of the N-type source region 31 is 2-8e18cm -3 ; The concentration of the N-type silicon carbide substrate 1 is to ensure the formation of a low-resistance ohmic contact with the drain metal layer 8, thereby reducing the overall on-resistance of the device; the doping concentration of the N-type drift layer 2 is a compromise between the reverse withstand voltage and on-resistance of the device; the P-type diffusion region 3 and the N-type freewheeling region 4 are to construct a superjunction structure in the device, and their concentrations are designed to achieve a compromise between withstand voltage and the conduction of potential from the drain to the source; the P-type diffusion region 3 also takes into account the role of the well region of the device; the doping concentration of the N-type source region 31 is to reduce the source contact resistance of the device and reduce the on-resistance of the device; in addition to forming a superjunction structure, the N-type freewheeling region 4 also provides a freewheeling channel when the device is turned on, thereby reducing the on-resistance of the device.

[0054] The thickness of the N-type silicon carbide substrate 1 of the device is 1 μm, and the thickness of the N-type drift layer 2 is 10-30 μm, which is adjusted within the above range according to different requirements for the withstand voltage characteristics of the device. The total width of the P-type diffusion region 3 is 40% of the width of the drain metal layer 8, the width of the N-type freewheeling region 4 is 20% of the width of the drain metal layer 8, and the distance between the outer side of the N-type freewheeling region 4 and the inner side of the P-type diffusion region 3 is 5% of the width of the drain metal layer 8. This is to suppress the influence of the N-type freewheeling region 4 and the P-type diffusion region 3 on the device gate structure. The width of the N-type source region 31 is 10% of the width of the drain metal layer 8, and the distance between the inner side of the N-type source region 31 and the inner side of the P-type diffusion region is 20nm. This part of the area is distributed below the device gate. The thickness of the N-type source region 31 is 200nm, the thickness of the source metal layer 7 is 200nm, and the thickness of the gate metal layer 6 is 150nm;

[0055] By constructing a P-type diffusion region 3 and an N-type freewheeling region 4 in the N-type drift layer 2, a super junction structure of the device is constructed, so that the longitudinal withstand voltage of the device is changed to a structure that withstands both longitudinal and lateral withstand voltages, i.e., a super junction structure, so as to improve the withstand voltage capability of devices with the same thickness and width;

[0056] The direct Schottky contact between the source metal layer 7 and the N-type drift layer 2 of the device can form a parasitic Schottky body diode of the device, thereby improving the reverse recovery speed of the device, reducing the reverse recovery time, and improving the switching speed of the device;

[0057] The P-type diffusion region 3 of the device forming the super junction structure completely surrounds the N-type source region 31, so that no additional P-type well region process is required, which can effectively reduce the complexity of the device preparation process and reduce the device manufacturing cost.

[0058] Although the specific implementation modes of the present invention are described above, those skilled in the art should understand that the specific implementation modes described are only illustrative and are not intended to limit the scope of the present invention. Equivalent modifications and changes made by those skilled in the art in accordance with the spirit of the present invention should be included in the scope of protection of the claims of the present invention.

Claims

1. A method for preparing a superjunction fast recovery planar gate silicon carbide VDMOS, characterized in that: The steps include: Step 1: depositing metal on the lower side of the silicon carbide substrate to form a drain metal layer, and epitaxially growing on the side of the silicon carbide substrate to form a drift layer; Step 2: forming a barrier layer above the drift layer, etching the barrier layer to form a through hole, and implanting ions into the drift layer to form a diffusion region; Step 3, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, and performing ion implantation into the drift layer to form a freewheeling region; Step 4, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, and performing ion implantation into the diffusion region to form an N-type source region; Step 5, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, and depositing to form a gate dielectric layer; Step 6: remove the original barrier layer, re-form the barrier layer, etch the barrier layer to form a through hole, deposit metal, and form a gate metal layer; Step 7: remove the original barrier layer, re-form the barrier layer, etch the barrier layer to form a through hole, deposit metal to form a source metal layer, remove the barrier layer, and complete the preparation.

2. The method for preparing a super junction fast recovery planar gate silicon carbide VDMOS according to claim 1, characterized in that: The doping concentration of the N-type source region is greater than the doping concentration of the diffusion region, and the doping concentration of the diffusion region is greater than the doping concentration of the drift layer.

3. The method for preparing a super junction fast recovery planar gate silicon carbide VDMOS according to claim 1, characterized in that: The total width of the diffusion region is 40% of the width of the drift layer.

4. The method for preparing a superjunction fast recovery planar gate silicon carbide VDMOS according to claim 1, characterized in that: The width of the freewheeling region is 20% of the width of the drift layer.

5. The method for preparing a super junction fast recovery planar gate silicon carbide VDMOS according to claim 1, characterized in that: The distance between the inner side surface of the N-type source region and the inner side surface of the diffusion region is 20 nm.

6. The method for preparing the super junction fast recovery planar gate silicon carbide VDMOS according to claim 1 is characterized by: The distance between the inner side surface of the diffusion region and the outer side surface of the freewheeling region is 5% of the width of the drift layer.

7. A superjunction fast recovery planar gate silicon carbide VDMOS, characterized in that: The silicon carbide VDMOS is prepared by any one of the preparation methods of claim 1 to claim 6.

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