Process method for improving channel mobility and gate dielectric layer reliability of SiC MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor)

Abstract

The invention relates to a process method for improving channel mobility and gate dielectric layer reliability of a SiC MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor). The process method comprises the following steps of: forming a channel layer on an epitaxial layer by adopting ion implantation; carrying out surface treatment on the SiC epitaxial layer in a sacrificial oxidation mode; forming SiO2 on the surface of SiC by adopting a low-pressure chemical vapor deposition process to serve as a gate dielectric layer; and performing an NO post-deposition annealing process on the gate dielectric layer. The SiC / SiO2 interface roughness formed by the method is reduced, the problem that carbon clusters and carbon particles are generated in traditional thermal oxidation is avoided, and the interface state density is reduced, so that the channel carrier mobility is enhanced; besides, a step-by-step low-pressure chemical vapor deposition process is adopted, gate dielectric layer densification is carried out in a gap between two or more stages of deposition processes, residues of a precursor in deposition are fully decomposed, stress of the gate dielectric layer is released, the electric leakage level of the gate dielectric layer is reduced, the reliability of the gate dielectric layer is enhanced, and the device yield is improved.

Description

Technical Field

[0001] The present invention relates to a semiconductor device manufacturing process, and in particular to a process method for improving SiC MOSFET channel mobility and gate dielectric layer reliability. Background Art

[0002] Silicon carbide has attracted extensive attention from industry and academia in recent years due to its wide bandgap, high critical breakdown field strength and high thermal conductivity. It has broad prospects for industrialization, among which SiC MOSFET devices have received great attention as the main device.

[0003] However, due to the presence of carbon in silicon carbide materials and its large bandgap, the gate oxide interface state density of SiC / SiO2 is extremely high, generally 1-3 orders of magnitude higher than the interface state density of traditional Si / SiO2. The extremely high interface state density leads to extremely low channel carrier mobility of MOSFET, affecting the channel on-state characteristic resistance of MOSFET devices, and further affecting the on-state characteristic resistance of MOSFET devices.

[0004] At present, it is believed that the source of the SiC / SiO2 interface state is that when SiC and O2 undergo a chemical reaction during high-temperature oxidation to generate SiO2, C clusters remain at the SiC / SiO2 interface, affecting the interface quality of SiC / SiO2.

[0005] Therefore, in order to avoid the generation of C clusters during the thermal oxidation process, the gate dielectric layer can be directly prepared by deposition. Generally, chemical deposition or physical deposition can be used to deposit the oxide. However, although this method can avoid the generation of C clusters caused by traditional thermal oxidation, the density of the deposited gate dielectric layer is not as good as that of the thermal oxidation method, resulting in a large gate leakage of the gate dielectric and a serious reduction in the reliability of the gate. Summary of the invention

[0006] In order to solve one or more technical problems of the above-mentioned prior art, the present invention proposes a process method for improving the channel mobility and gate dielectric layer reliability of SiC MOSFET.

[0007] According to an embodiment of the present invention, a process method for improving the channel mobility and gate dielectric layer reliability of SiC MOSFET is proposed, characterized in that it includes: step S1, forming an epitaxial layer on a silicon carbide substrate with a first type of doping, and the doping type of the epitaxial layer can be the first doping type or the second doping type; step S2, forming a base region with a second doping type on the silicon carbide epitaxial layer with the first doping type by ion implantation, or forming a base region with the first doping type on the silicon carbide epitaxial layer with the second doping type by ion implantation; or directly using the epitaxial layer as the base region; step S3, in the base region, forming a source contact region and a drain contact region of the MOSFET by ion implantation; when the base region has the first doping type, the source contact region and the drain contact region formed by ion implantation have the second doping type; when the base region has the second doping type, the source contact region and the drain contact region formed by ion implantation have the first doping type; step S4, in the base region, forming a body region by ion implantation, the body region and the base region have the same doping type, and the doping concentration of the body region is 1×10 19 ~1×10 21 cm -3 ; Step S5, the channel region is located between the source contact region and the drain contact region, and while the source contact region and the drain contact region are formed by ion implantation, a channel region is naturally formed between the two contact regions; Step S6, the surface of the silicon carbide wafer is treated by sacrificial oxidation to reduce the formation of natural oxides and reduce the roughness of the surface of the silicon carbide wafer; Step S7, by low-pressure chemical vapor deposition, tetraethyl orthosilicate is used as a deposition precursor to form SiO2 as a gate dielectric layer on the surface of the silicon carbide wafer; Step S8, the gate dielectric layer is annealed in a NO or N2 or N2O or NH3 atmosphere after deposition; Step S9, polysilicon is deposited on the gate dielectric layer by low-pressure chemical vapor deposition and the polysilicon is deposited and annealed by POCL3 to form a gate electrode; Step S10, metal is deposited or sputtered in the source contact region, the drain contact region and the body region, and ohmic contact is formed by annealing.

[0008] Furthermore, in step S3, ion implantation of the source contact region and the drain contact region of the MOSFET is performed at room temperature or 500°C, with an implantation angle of 7°, and a junction depth of 0.2um-0.5um is formed.

[0009] Furthermore, in step S4, the ion implantation of the body region of the MOSFET is performed at room temperature or 500°C, the implantation angle is 7°, the junction depth is 0.2um-0.5um, and the doping concentration is 1×10 19 ~1×10 21 cm -3 .

[0010] Furthermore, in step S7, the process flow of the low-pressure chemical vapor deposition process includes depositing to form a gate dielectric layer, heating up the gate dielectric layer after deposition to densify the gate dielectric layer, cooling down after the first densification and then re-depositing to prepare the gate dielectric layer, and heating up the gate dielectric layer again after the second deposition to densify the gate dielectric layer.

[0011] Further, in step S7, the deposition process temperature of the gate dielectric layer formed by the low-pressure chemical vapor deposition process is 640°C-690°C, and the deposition time is 8min-12min. After the first stage of deposition, the process temperature is increased to 750°C. During the heating process, the oxygen content is gradually increased and the precursor valve is gradually closed, and the residual precursor in the furnace tube equipment is removed, and the pure oxygen environment is maintained at an ambient temperature of 750°C for 30min-120min. Then, the process temperature is reduced to the deposition process temperature of 640°C-690°C, and the gas atmosphere is restored to that when SiO2 is deposited, that is, the flow rate of the precursor is increased and the oxygen flow rate is reduced. The deposition time is 8min-12min. Then, the densification process after deposition is repeated, and the process temperature is increased to 750°C. During the heating process, the oxygen content is gradually increased and the precursor valve is gradually closed, and the residual precursor in the furnace tube equipment is removed, and the pure oxygen environment is maintained at an ambient temperature of 750°C for 30min-120min. After the densification is completed, the temperature is reduced and the sheet is taken out to complete the preparation of the gate dielectric layer.

[0012] Furthermore, the thickness of the deposited SiO2 gate dielectric layer is 35nm-60nm.

[0013] Furthermore, in step S8, the temperature of the post-deposition annealing is 1200° C.-1400° C., the annealing time is 30 min-90 min, and the annealing gas may be NO, N2, N2O or NH3.

[0014] Further, in step S10, metal nickel is sputtered as an ohmic contact material by sputtering or evaporation, the thickness of the metal nickel is 100nm-300nm, and annealing is performed at 650℃-950℃ in N2 atmosphere for 60s-240s. After the ohmic contact is formed, dilute sulfuric acid is used to clean and remove excess metal nickel in the unalloyed area.

[0015] According to another embodiment of the present invention, a silicon carbide MOSFET device is proposed, characterized in that it is prepared by the above-mentioned process method for improving the channel mobility and gate dielectric layer reliability of SiC MOSFET, and includes a silicon carbide substrate layer, an epitaxial layer, a base region, a source contact region, a drain contact region, a body region, a gate dielectric layer, a gate and an ohmic contact region.

[0016] According to another embodiment of the present invention, a process method for improving the channel mobility and gate dielectric layer reliability of SiC MOSFET is proposed, comprising the following steps: preparing an N-type silicon carbide substrate material; preparing an N-type epitaxial layer on the prepared N-type silicon carbide substrate material; forming a base region with P-type doping on the prepared N-type silicon carbide epitaxial layer by ion implantation; forming an N-type source contact region and a drain contact region with a high doping concentration in the prepared P-type base region by ion implantation; forming a P-type body region with a high doping concentration in the prepared P-type base region by ion implantation; preparing a gate dielectric layer by a low-pressure chemical vapor deposition process, in which the gate dielectric is first deposited, the temperature is increased to compact the gate dielectric, and the temperature is decreased to form a P-type body region with a high doping concentration; The gate dielectric is deposited, and then the temperature is increased to densify the gate dielectric. During the temperature increase and decrease process and the densification process, the gate dielectric stress obtained by the deposition is fully released, and the precursor residue is decomposed; polysilicon is deposited on the prepared gate dielectric layer by low-pressure chemical vapor deposition, and phosphorus is doped on the polysilicon by low-pressure chemical vapor deposition; an insulating dielectric layer is formed by low-pressure chemical vapor deposition or plasma enhanced chemical vapor deposition to insulate and isolate the gate from the source and the drain, and a metal nickel with a thickness of 100nm-300nm is formed on the semiconductor surface by magnetron sputtering or evaporation, and the metal and the semiconductor are formed into an ohmic contact by rapid thermal annealing, and finally the SiC MOSFET device is formed.

[0017] The beneficial effects of the present invention include but are not limited to:

[0018] 1. The gate dielectric layer is deposited on the silicon carbide wafer by low-pressure chemical vapor deposition, which avoids the carbon clusters generated at the SiC / SiO2 interface by the traditional thermal oxidation method, improves the SiC / SiO2 interface quality, reduces the interface state density of SiC / SiO2, and improves the channel mobility of SiC MOSFET.

[0019] 2. In the low-pressure chemical vapor deposition process, a deposition-densification-re-deposition-re-densification method is adopted. After deposition, the internal temperature of the furnace tube equipment is changed to release the stress of the gate dielectric layer, eliminate the precursor residue, and densify the gate dielectric layer. The segmented deposition and densification method is adopted to improve the density of the gate dielectric layer in a layered manner, which solves the problems of large leakage of the gate dielectric layer and low reliability of the gate dielectric layer caused by the traditional deposition process, improves the reliability of the gate dielectric layer, and improves the preparation yield of the overall device, which has certain industrial application value. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 A flowchart of a process method for improving SiC MOSFET channel mobility and gate dielectric reliability according to an embodiment of the present invention;

[0021] Figure 2A schematic diagram of a process flow of a low pressure chemical vapor deposition process according to an embodiment of the present invention;

[0022] Figure 3 A comparison diagram of leakage curves of a gate dielectric layer prepared by a low pressure chemical vapor deposition process according to an embodiment of the present invention and a gate dielectric layer prepared by a traditional low pressure chemical vapor deposition process;

[0023] Figure 4 FIG. 1 is a schematic diagram of a process flow for preparing a SiC MOSFET according to an embodiment of the present invention. DETAILED DESCRIPTION

[0024] The specific embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings. It should be noted that the embodiments described herein are only for illustration and are not intended to limit the present invention. In the following description, a large number of specific details are set forth to facilitate a thorough understanding of the present invention. However, it will be appreciated by those of ordinary skill in the art that these specific details are not necessary for implementing the present invention. In addition, in some embodiments, in order to avoid confusing the present invention, known circuits, materials or methods are not specifically described.

[0025] Throughout the specification, references to "one embodiment", "an embodiment", "an example" or "an example" mean that the specific features, structures or characteristics described in conjunction with the embodiment or example are included in at least one embodiment of the present invention. Therefore, the phrases "in one embodiment", "in an embodiment", "an example" or "an example" appearing in various places throughout the specification do not necessarily refer to the same embodiment or example. In addition, specific features, structures or characteristics can be combined in one or more embodiments or examples in any appropriate combination and / or sub-combination. In addition, it should be understood by those of ordinary skill in the art that the figures provided herein are for illustrative purposes, in which the same figure numbers indicate the same elements. The term "and / or" used herein includes any and all combinations of one or more related listed items. The individual steps are not limited to a strict front-to-back order relationship. For example, in the ten steps of step S1 to step S10, the steps can be implemented in any order as needed.

[0026] The power MOSFET device described in the present invention includes but is not limited to planar MOSFET, trench MOSFET, split-gate MOSFET, the parasitic diode includes but is not limited to pin diode and Schottky diode, and the material includes but is not limited to silicon carbide, gallium nitride, and silicon.

[0027] The present invention provides a process method for improving the channel mobility and gate dielectric reliability of SiC MOSFET, which forms a gate dielectric layer on the surface of a silicon carbide wafer by low-pressure chemical vapor deposition, avoids the formation of carbon clusters at the SiC / SiO2 interface by the traditional thermal oxidation method, improves the SiC / SiO2 interface quality, reduces the SiC / SiO2 interface state density, and improves the channel mobility of SiC MOSFET. The low-pressure chemical vapor deposition process adopts a deposition-densification-re-deposition-re-densification method, completes the deposition densification work in the same process in the same equipment, fully releases the gate dielectric layer stress, improves the density of the gate dielectric layer, reduces the leakage level of the gate dielectric layer, and improves the reliability of the gate dielectric layer.

[0028] Specifically, Figure 1 As shown, the present invention provides a process method for improving SiC MOSFET channel mobility and gate dielectric layer reliability, comprising the following steps:

[0029] Step S0: preparing a silicon carbide substrate.

[0030] Step S1: forming an epitaxial layer on a silicon carbide substrate, with a substrate doping concentration of 1×10 19 cm -3 The thickness is 350um, and an N-type epitaxial layer is formed on the substrate, and the doping concentration of the epitaxial layer is 8×10 15 cm -3 , with a thickness of 12um. After the epitaxial layer growth is completed, RCA cleaning is performed to remove the contamination and natural oxide layer on the wafer surface.

[0031] Step S2: Form a base region on the epitaxial layer by ion implantation. The doping concentration of the base region can be 1e 17 cm -3 , the injection conditions can be 25keV 3.6E11cm -2 ; 60keV 5.8E11cm -2 ; 115keV 9E11cm -2 ; 200keV 1.5E12cm -2 .

[0032] Step S3: In the base region, a source contact region and a drain contact region are formed by ion implantation. The doping concentration of the contact region can be 5e19cm -3 , the injection conditions can be 60keV 9E15cm-2; 80keV 1E16cm -2 ; 100keV 9E15cm -2 ;180keV9E15cm -2 .

[0033] Step S4: In the base region, a body region is formed by ion implantation, and the doping concentration of the body region is 2e19cm -3 , injection conditions are 30keV 5E14cm -2 ; 90keV 1E15cm -2 ; 200keV 4E15cm -2 .

[0034] Step S5: performing activation annealing on all implants. The activation annealing temperature may be 1600° C.-1850° C., and the annealing time may be 20 min-90 min.

[0035] Step S6: further performing sacrificial oxidation on the silicon carbide wafer, and using BOE to remove the oxide layer.

[0036] Step S7: further placing the wafer into the furnace tube of the low-pressure chemical vapor deposition equipment, the deposition process temperature of the gate dielectric layer can be 640°C-690°C, the deposition time can be 8min-12min, after the first stage of deposition, the process temperature is raised to 750°C, during the heating process, the oxygen content is gradually increased while the precursor valve is gradually closed, and the residual precursor in the furnace tube equipment is removed, and the pure oxygen environment is maintained at an ambient temperature of 750°C for 30min-120min. Then the process temperature is reduced to a deposition process temperature between 640°C-690°C or 640°C or 690°C, and the gas atmosphere is restored to the deposition of SiO2, that is, the flow rate of the precursor is increased and the oxygen flow rate is reduced, and the deposition time can be 8min-12min. Then repeat the densification process after deposition, raise the process temperature to 750°C, during the heating process, gradually increase the oxygen content while gradually closing the precursor valve, and remove the residual precursor in the furnace tube equipment, and maintain the pure oxygen environment at an ambient temperature of 750°C for 30min-120min. After densification is completed, the temperature is lowered and the wafer is taken out to complete the preparation of the gate dielectric layer. The thickness of the gate dielectric layer can be 40nm-60nm.

[0037] Step S8: annealing the gate dielectric layer after deposition, the annealing temperature is 1200°C, the gas atmosphere is a mixture of NO and N2, the gas ratio can be 1:4; the annealing time can be 45 minutes

[0038] Step S9: deposit polysilicon by low-pressure chemical vapor deposition and perform POCL3 annealing to dope P element into the polysilicon to form a gate electrode.

[0039] Step S10: low pressure chemical vapor deposition is used to deposit an insulating dielectric layer forming a gate, a source, and a drain.

[0040] Step S11: sputtering metal nickel by magnetron sputtering, and annealing in a rapid annealing device to form ohmic contact between the source and the drain. The annealing atmosphere is N2, the temperature is 900° C., and the time is 2 minutes.

[0041] Figure 2 The process flow chart of the low-pressure chemical vapor deposition process proposed in the present invention mainly includes depositing to form a gate dielectric layer S70, heating up the gate dielectric layer after deposition to densify it S71, cooling down after the first step of densification and then re-depositing to prepare the gate dielectric layer S72, and heating up the gate dielectric layer again after the second step of deposition to densify it S73.

[0042] Figure 3 This is a comparison chart of the leakage level test of a gate dielectric layer prepared by the low-pressure chemical vapor deposition process proposed in the present invention, i.e., deposition-densification-redeposition-redensification, and a gate dielectric layer formed by general low-pressure chemical vapor deposition. It can be seen from the figure that the breakdown field strength of the gate dielectric layer prepared by the process proposed in the present invention is improved by nearly 4MV / cm compared with the general deposition process. When the gate electric field is 4MV / cm, the leakage current level of the deposition process proposed in the present invention is reduced by 3 orders of magnitude compared with the general preparation process, thereby greatly improving the reliability of the gate dielectric layer.

[0043] Figure 4 The process flow chart for preparing the SiC MOSFET is as follows: Figure 4 (a) Prepared N-type silicon carbide substrate material; Figure 4 (b) shows the preparation of an N-type epitaxial layer on the prepared N-type silicon carbide substrate material; Figure 4 (c) shows that a base region with P-type doping is formed on the prepared N-type silicon carbide epitaxy by ion implantation; Figure 4 (d) shows that an N-type source contact region and a drain contact region with a high doping concentration are formed in the prepared P-type base region by ion implantation; Figure 4 (e) shows that a P-type body region with a high doping concentration is formed in the prepared P-type base region by ion implantation; Figure 4 (f) The process is a schematic diagram of the process of preparing a gate dielectric layer by the low-pressure chemical vapor deposition process proposed in the present invention. In this process step, the gate dielectric is first deposited, and then the temperature is increased to compact the gate dielectric. The gate dielectric is deposited while the temperature is decreased, and then the temperature is increased to compact the gate dielectric. During the temperature increase and decrease process and the compaction process, the gate dielectric stress obtained by the deposition is fully released to decompose the precursor residue. Figure 4 (g) shows that polysilicon is deposited on the prepared gate dielectric layer by low-pressure chemical vapor deposition and phosphorus is doped into the polysilicon by low-pressure chemical vapor deposition; Figure 4 (h) shows that the gate is insulated from the source and drain by forming an insulating dielectric layer by low pressure chemical vapor deposition or plasma enhanced chemical vapor deposition. Figure 4 (i) shows that metal nickel with a thickness of 100nm-300nm is formed on the semiconductor surface by magnetron sputtering or evaporation, and the metal and the semiconductor are made to form an ohmic contact through rapid thermal annealing, and finally a SiC MOSFET device is formed;.

[0044] In summary, the present invention adopts low-pressure chemical vapor deposition to prepare the gate dielectric layer of SiC MOSFET, and adopts tetraethyl orthosilicate as a precursor to deposit SiO2, thereby avoiding the formation of carbon clusters at the SiC / SiO2 interface by the traditional thermal oxidation method, improving the quality of the SiC / SiO2 interface, reducing the SiC / SiO2 interface state density, and improving the channel mobility of the SiC MOSFET. The low-pressure chemical vapor deposition process adopts the method of deposition-densification-re-deposition-re-densification, and completes the deposition and densification work in the same process in the same equipment, fully releasing the stress of the gate dielectric layer, improving the density of the gate dielectric layer, reducing the leakage level of the gate dielectric layer, and improving the reliability of the gate dielectric layer.

[0045] Although the present invention has been described with reference to several typical embodiments, it should be understood that the terms used are illustrative and exemplary, rather than restrictive. Since the present invention can be embodied in a variety of forms without departing from the spirit or essence of the invention, it should be understood that the above embodiments are not limited to any of the foregoing details, but should be interpreted broadly within the spirit and scope defined by the appended claims, so all changes and modifications falling within the scope of the claims or their equivalents should be covered by the appended claims.

Claims

1. A process method for improving SiC MOSFET channel mobility and gate dielectric layer reliability, characterized in that: include: Step S0, preparing a silicon carbide substrate; Step S1, forming an epitaxial layer on a silicon carbide substrate having a first type of doping, wherein the doping type of the epitaxial layer is the first doping type or the second doping type; Step S2, forming a base region with a second doping type on the silicon carbide epitaxy with the first doping type by ion implantation, or forming a base region with a first doping type on the silicon carbide epitaxy with the second doping type by ion implantation, or directly using the epitaxial layer as the base region; Step S3, in the base region, forming a source contact region and a drain contact region of the MOSFET by ion implantation; when the base region has a first doping type, the source contact region and the drain contact region formed by the ion implantation have a second doping type; when the base region has a second doping type, the source contact region and the drain contact region formed by the ion implantation have a first doping type; Step S4: In the base region, a body region is formed by ion implantation. The body region has the same doping type as the base region. The doping concentration of the body region can be 1×10 19 ~1×10 21 cm -3 between; Step S5, the channel region is located between the source contact region and the drain contact region, and while the source contact region and the drain contact region are formed by ion implantation, the channel region is naturally formed between the two contact regions; Step S6, treating the surface of the silicon carbide wafer by sacrificial oxidation to reduce the formation of natural oxides and reduce the roughness of the surface of the silicon carbide wafer; Step S7, forming SiO2 as a gate dielectric layer on the surface of the silicon carbide wafer by low pressure chemical vapor deposition using tetraethyl orthosilicate as a deposition precursor; Step S8, annealing the gate dielectric layer in an atmosphere of NO, N2, N2O or NH3 after deposition; Step S9, depositing polysilicon on the gate dielectric layer by low pressure chemical vapor deposition and annealing the polysilicon after deposition by POCL3 to form a gate electrode; Step S10: low pressure chemical vapor deposition is used to deposit an insulating dielectric layer forming a gate, a source, and a drain. Step S11 , depositing or sputtering metal in the source contact region, the drain contact region and the body region, and forming ohmic contacts by annealing.

2. A process for improving SiC MOSFET channel mobility and gate dielectric layer reliability according to claim 1, characterized in that: In step S3, ion implantation of the source contact region and the drain contact region of the MOSFET is performed at room temperature or 500°C, with an implantation angle of 7°, and a junction depth of 0.2um-0.5um is formed.

3. A process for improving SiC MOSFET channel mobility and gate dielectric layer reliability according to claim 1, characterized in that: In step S4, the ion implantation of the body region of the MOSFET is performed at room temperature or 500°C, the implantation angle is 7°, the junction depth is 0.2um-0.5um, and the doping concentration is 1×10 19 ~1×10 21 cm -3 .

4. A process for improving SiC MOSFET channel mobility and gate dielectric layer reliability according to claim 1, characterized in that: In step S7, the process flow of the low-pressure chemical vapor deposition process includes depositing to form a gate dielectric layer, heating up the gate dielectric layer after deposition to densify the gate dielectric layer, cooling down after the first densification and then depositing the gate dielectric layer, and heating up the gate dielectric layer again after the second deposition to densify the gate dielectric layer.

5. A process for improving SiC MOSFET channel mobility and gate dielectric layer reliability according to claim 1, characterized in that: In step S7, the deposition process temperature of the gate dielectric layer formed by the low-pressure chemical vapor deposition process is 640°C-690°C, and the deposition time is 8min-12min. After the first stage of deposition, the process temperature is increased to 750°C. During the heating process, the oxygen content is gradually increased and the precursor valve is gradually closed, and the residual precursor in the furnace tube equipment is removed. The pure oxygen environment is maintained at an ambient temperature of 750°C for 30min-120min. Then the process temperature is reduced to the deposition process temperature of 640°C-690°C, and the gas atmosphere is restored to that when SiO2 is deposited, that is, the flow rate of the precursor is increased and the oxygen flow rate is reduced. The deposition time is 8min-12min. Then the densification process after deposition is repeated, the process temperature is increased to 750°C, and during the heating process, the oxygen content is gradually increased and the precursor valve is gradually closed, and the residual precursor in the furnace tube equipment is removed. The pure oxygen environment is maintained at an ambient temperature of 750°C for 30min-120min. After the densification is completed, the temperature is reduced and the sheet is taken out to complete the preparation of the gate dielectric layer.

6. A process for improving SiC MOSFET channel mobility and gate dielectric layer reliability as claimed in claim 5, characterized in that: The thickness of the deposited SiO2 gate dielectric layer is 35nm-60nm.

7. A process for improving SiC MOSFET channel mobility and gate dielectric layer reliability according to claim 1, characterized in that: In step S8, the temperature of the post-deposition annealing is 1200° C.-1400° C., the annealing time is 30 min-90 min, and the annealing gas can be NO, N2, N2O or NH3.

8. A process for improving SiC MOSFET channel mobility and gate dielectric layer reliability as claimed in claim 1, characterized in that: In step S10, metal nickel is sputtered as an ohmic contact material by sputtering or evaporation, the thickness of the metal nickel is 100nm-300nm, and annealing is performed at 650℃-950℃ in N2 atmosphere for 60s-240s. After the ohmic contact is formed, dilute sulfuric acid is used to clean and remove excess metal nickel in the unalloyed area.

9. A silicon carbide MOSFET device, characterized in that: The method for improving the channel mobility and gate dielectric layer reliability of SiCMOSFET according to any one of claims 1 to 7 is prepared, comprising a silicon carbide substrate layer, an epitaxial layer, a base region, a source contact region, a drain contact region, a body region, a gate dielectric layer, a gate and an ohmic contact region.

10. A process method for improving SiC MOSFET channel mobility and gate dielectric layer reliability, characterized in that: The following steps are involved: Prepare an N-type silicon carbide substrate material; prepare an N-type epitaxial layer on the prepared N-type silicon carbide substrate material; form a base region with P-type doping on the prepared N-type silicon carbide epitaxial layer by ion implantation; form an N-type source contact region and a drain contact region with a high doping concentration in the prepared P-type base region by ion implantation; form a P-type body region with a high doping concentration in the prepared P-type base region by ion implantation; prepare a gate dielectric layer by a low-pressure chemical vapor deposition process, in which the gate dielectric is first deposited, the temperature is increased to compact the gate dielectric, the gate dielectric is deposited after the temperature is decreased, and the temperature is increased to compact the gate dielectric. Densification, during the temperature rise and fall process and the densification process, the gate dielectric stress obtained by deposition is fully released, and the precursor residue is decomposed; polysilicon is deposited on the prepared gate dielectric layer by low-pressure chemical vapor deposition, and the polysilicon is doped with phosphorus by low-pressure chemical vapor deposition; an insulating dielectric layer is formed by low-pressure chemical vapor deposition or plasma enhanced chemical vapor deposition to insulate and isolate the gate from the source and the drain, and metal nickel with a thickness of 100nm-300nm is formed on the semiconductor surface by magnetron sputtering or evaporation, and the metal and the semiconductor are formed into ohmic contact by rapid thermal annealing, and finally the SiC MOSFET device is formed.

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