SBD-integrated SiCMOSFET device and preparation method thereof

Abstract

The invention discloses an SBD-integrated SiC MOSFET device and a preparation method thereof, and relates to the technical field of semiconductors. An SBD structure is arranged in the SiC MOSFET chip and connected with a body diode of the SBD structure in parallel, the embedded SBD diode increases the contact area of an N + region and metal in the vertical direction through a groove structure, meanwhile, the doping concentration of the N + region is far larger than that of an N-drift layer, the heavily-doped N + region can also reduce the conduction voltage drop of the embedded SBD diode, the follow current capacity of the SiC MOSFET device is greatly improved, and the performance of the SiC MOSFET device is improved. And the power loss is reduced. In the blocking state, the deeply injected PP region is beneficial to shielding the embedded SBD region and a high electric field at the bottom of the gate trench, and the reliability of the device can be improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a SiC MOSFET device integrated with an SBD and a preparation method thereof. Background Art

[0002] SiC MOSFET has been used in more and more industries due to its performance advantages, such as energy storage, charging piles, photovoltaic inverters, motor drives, and industrial control power supplies; when used in motor control units, it can significantly improve the energy efficiency of motors. Compared with traditional silicon-based IGBT modules, silicon carbide modules can achieve an energy efficiency improvement of about 5%, which means that for electric vehicles, energy consumption can be reduced by about 5%, thereby improving mileage and performance.

[0003] In applications such as motor drives and synchronous rectifiers, SiC MOSFETs usually require a freewheeling diode in anti-parallel connection for rectification, which not only takes up additional packaging area, but also introduces parasitic inductance, thereby limiting the switching frequency and reducing the power density of the power converter / inverter. Although the body diode of SiC MOSFET can achieve the rectification function, there is a risk of bipolar degradation and increased conduction power consumption. Therefore, how to design a SiC MOSFET device that significantly reduces the chip footprint and reduces the conduction loss and switching loss is a technical problem that needs to be solved urgently. Summary of the invention

[0004] In view of the above problems, the present invention provides a SiC MOSFET device with integrated SBD and a preparation method thereof, which can improve the freewheeling capability of the SiC MOSFET device, reduce power loss, and improve the reliability of the device.

[0005] The technical solution of the present invention is: A method for preparing a SiC MOSFET device with integrated SBD comprises the following steps: S100, in heavily doped N + An N-type buffer layer and an N-type - drift layer; S200, in N - A P-well region is formed on the drift layer by ion implantation, and a heavily doped NP region and a heavily doped PP region are formed on the P-well region by ion implantation; S300, forming a first trench region on the NP region by dry etching; forming a second trench region on the P-well region by dry etching; S400, N formed by ion implantation on the P-well region + Area, where high temperature ions are activated after implantation; S500, forming a gate oxide layer in the first trench region by thermal oxidation, and forming a Poly layer by deposition; S600, forming a dielectric layer on the gate oxide layer and the Poly layer to isolate the gate electrode and the source electrode metal; S700, forming a source ohmic contact alloy layer on the NP region and the PP region by metal sputtering; S800, in N + A Schottky metal is formed on the region, dielectric layer, and source ohmic contact alloy layer by metal sputtering; a source metal layer is formed on the Schottky metal by sputtering, and a source electrode is led out; S900, in N + The back side of the substrate layer reduces N + The thickness of the substrate layer is prepared by metal evaporation to form a drain metal layer and lead out a drain electrode.

[0006] Specifically, in step S100, N + The substrate layer is doped with N ions with a doping concentration of 1e 19 cm -2 ±10%; N-type buffer layer is doped with N ions, with a doping concentration of 1e 18 cm -2 ±10%; N - The drift layer is doped with N ions with a doping concentration of 8e 15 -2e 16 cm -2 , thickness is 5-20um.

[0007] Specifically, in step S200, the P-well region is doped with Al ions at a doping concentration of 1e 17 -1e 18 cm -2 NP region is doped with N ions, and the doping concentration is 1e 18 -5e 18 cm -2 PP region is doped with Al ions at a concentration of 5e 18 -1e 19 cm -2 .

[0008] Specifically, in step S400, N + The region is doped with N ions with a doping concentration of 5e 18 -1e 19 cm -2 .

[0009] A SiC MOSFET device with an integrated SBD, comprising a drain metal layer, an N + Substrate layer, N-type buffer layer, N -Drift layer, P-well region, NP region, source ohmic contact alloy layer, Schottky metal and source metal layer; The N - The drift layer contains: A PP region extending downward is provided at the outer end of the NP region, and the PP region extends downward from the top surface of the P-well region.

[0010] A first trench region extending downward is provided on the top surface of the NP region; the first trench region is in a U-shaped structure and is filled with a gate oxide layer and a Poly layer in sequence; The outer end of the PP zone is provided with an N + Area; said N + The region extends downward from the top surface of the P-well region, and has a depth greater than the second trench region and less than the PP region; The N + A second trench region extending downward is provided on the top surface of the region; the second trench region is in a rectangular structure and is filled with a Schottky metal layer and a source metal layer in sequence; A dielectric layer covering the gate oxide layer and the Poly layer is disposed on the top surface of the NP region.

[0011] Beneficial effects of the present invention: Improving the freewheeling capability of SiC MOSFET devices: Due to the stacking defects in the drift layer of 4H-SiC MOSFET, when the body diode of a conventional SiC MOS device is forward biased, electrons and holes recombine in the drift layer, and the energy generated activates BPDs (base plane dislocation). Due to the presence of BPDs, the lifetime and mobility of carriers are reduced, thereby reducing the main carrier conduction current capability and increasing the reverse leakage current in the forward blocking mode. This paper sets up an SBD structure in parallel with the built-in body diode inside the SiC MOSFET chip. The unipolar SBD structure can avoid the recombination of electrons and holes in the drift layer, so that the body diode will not be degraded during use, and the embedded SBD diode uses a trench structure to increase the vertical N + The area of ​​the heavily doped N + The area can also reduce the conduction voltage drop of the SiC MOSFET chip body diode, greatly improving the freewheeling capability of the SiC MOSFET device and reducing power loss.

[0012] Improving the reliability of SiC UMOSFET devices: In this case, a deep-injected PP region is set inside the SiC UMOSFET chip. In the blocking state, electrons and holes in the vicinity of the deep-injected PP region will be swept out of the space charge region under the action of an external electric field, thereby forming a depletion region. The expansion of the depletion region is conducive to shielding the surrounding electric field of the surrounding embedded SBD structure and trench gate structure, thereby reducing the electric field concentration effect of these fragile structures, avoiding failure here during long-term aging, and improving the reliability of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 It is a structural schematic diagram of step S100 of the present invention; Figure 2 It is a structural schematic diagram of step S200 of the present invention; Figure 3 It is a structural schematic diagram of step S300 of the present invention; Figure 4 is a structural schematic diagram of step S400 of the present invention; Figure 5 is a schematic structural diagram of step S500 of the present invention; Figure 6 is a schematic structural diagram of step S600 of the present invention; Figure 7 is a schematic structural diagram of step S700 of the present invention; Figure 8 is a structural schematic diagram of step S800 of the present invention; Fig. 9 is a structural schematic diagram of step S900 of the present invention; Fig.10 is a structural schematic diagram of step S1000 of the present invention; Fig.11 is a structural schematic diagram of step S1100 of the present invention; Fig.12 is a schematic diagram of the structure of step S1200 of the present invention; Fig.13 is a schematic diagram of the structure of step S1300 of the present invention; Fig.14 It is a structural schematic diagram of step S1400 of the present invention; In the figure, 1 is N + Substrate layer, 2 is N-type buffer layer, 3 is N - Drift layer, 4 is P-well region, 5 is NP region, 6 is PP region, 7 is the first trench region, 8 is the second trench region, 9 is N + Region, 10 is a gate oxide layer, 11 is a Poly layer, 12 is a dielectric layer, 13 is a source ohmic contact alloy layer, 14 is a Schottky metal, 15 is a source metal layer, and 16 is a drain metal layer. DETAILED DESCRIPTION

[0014] The present invention is described in detail below in conjunction with specific practical cases. Examples of the embodiments are shown in the accompanying drawings, and the schematic implementation methods of the present invention and their descriptions are only used to explain the present invention and are not intended to limit the present invention.

[0015] A method for preparing a SiC MOSFET device with integrated SBD comprises the following steps: S100, refer to Figure 1 As shown, in heavily doped N + An N-type buffer layer 2 is grown on the substrate layer 1; N in step S100 + Substrate layer 1 is doped with N ions, with a thickness of 360-400um and a doping concentration of 1e 19 cm -2 ±10%, the N-type buffer layer 2 is also doped with N ions, with a thickness of 0.8-1.2um and a doping concentration of 1e 18 cm -2 ±10%.

[0016] S200, refer to Figure 2 As shown, a layer of N type buffer layer 2 is epitaxially grown. - Drift layer 3; The N of step S200 - The drift layer 3 is doped with N ions at a doping concentration of 8e 15 -2e 16 cm -2 , thickness is 5-20um.

[0017] S300, refer to Figure 3 As shown, in N - A P-well region 4 is formed on the drift layer 3 by ion implantation; The P-well region 4 in step S300 is doped with Al ions at a doping concentration of 1e 17 -1e 18 cm -2 .

[0018] S400, refer to Figure 4 As shown, a heavily doped NP region 5 is formed in the P-well region 4 by ion implantation; In step S400, the NP region 5 is doped with N ions with a thickness of 0.2-0.5um and a doping concentration of 1e 18 -5e 18 cm -2 .

[0019] S500, refer to Figure 5As shown, in the P-well region 4, the side of the NP region 5 is formed into a heavily doped PP region 6 by ion implantation; In step S500, the PP region 6 is doped with Al ions at a doping concentration of 5e 18 -1e 19 cm -2 The injection depth is 1.2-1.5um.

[0020] S600, refer to Figure 6 As shown, a first trench region 7 extending to below the P-well region 4 is formed on the surface of the NP region 5 by dry etching; S700, reference Figure 7 As shown, a second trench region 8 extending downward is formed on the surface of the P-well region 4 by dry etching; In step S700 , the etching depth of the second trench region 8 is greater than the depth of the P-well region 4 , and may be inconsistent with the depth of the first trench region 7 .

[0021] S800, reference Figure 8 As shown, N is formed in the second trench region 8 by ion implantation. + Zone 9, high temperature ion activation after implantation; N in step S800 + Region 9 is doped with N ions at a doping concentration of 5e 18 -1e 19 cm -2 , the doping depth is less than the depth of PP zone 6.

[0022] S900, refer to Fig. 9 As shown, a gate oxide layer 10 is formed in the first trench region 7 by a dry oxygen thermal oxidation process, and a channel is formed at the interface with the P-Well region 4; In step S900 , the gate oxide layer 10 is grown at a temperature of 1250-1350° C. and a thickness of 40-60 nm. It needs to be annealed in a NO atmosphere at a temperature of 1250° C. for 1 hour to improve the compactness of the gate oxide layer 10 and reduce defects.

[0023] S1000, refer to Fig.10 As shown, polysilicon is deposited on the gate oxide layer 10 to form a Poly layer 11, and a gate electrode is led out; S1100, reference Fig.11 As shown, a dielectric layer 12 is formed by depositing oxide on the Poly layer 11 to isolate the gate electrode and the source electrode metal; S1200, refer to Fig.12 As shown, a source ohmic contact alloy layer 13 is formed on the NP region 5 and the PP region 6 by sputtering Ni metal; In step S1200 , the source ohmic contact alloy layer 13 is annealed at a temperature of 1000° C. for 5 minutes to form an alloy and achieve an ohmic contact effect.

[0024] S1300, refer to Fig.13 As shown, in the source ohmic contact alloy layer 13, the dielectric layer 12, N + A Schottky metal 14 and a source metal layer 15 are formed on the upper surface of the region 9 by sputtering Ti / AlCu metal to lead out a source electrode; S1400, reference Fig.14 As shown, in N + The back side of the substrate layer 1 is thinned to reduce N + The substrate layer 1 is 1000 mm thick, and then Ni metal is sputtered and Ti / Ni / Ag metal is evaporated to form a drain metal layer 16 to lead out a drain electrode.

[0025] In step S1400, the drain metal layer 16 needs to be laser annealed after Ni metal sputtering, and the laser energy is 2-4mJ / cm 2 ; Later, multiple layers of metals such as Ti / Ni / Ag are evaporated, or other metals can be used, with a total thickness of 1.4-2um.

[0026] A SiC MOSFET device with integrated SBD, comprising a drain metal layer 16, an N + Substrate layer 1, N-type buffer layer 2, N - Drift layer 3, source ohmic contact alloy layer 13, Schottky metal 14 and source metal layer 15; The N - The drift layer 3 is provided with: P-well region 4, from the N - The top surface of the drift layer 3 extends downward; A plurality of NP regions 5 are provided, each extending downward from the top surface of the P-well region 4 and having a spacing with the bottom surface of the P-well region 4; A plurality of PP regions 6 are provided, each extending downward from the top surface of the P-well region 4 and located at the side of the NP region 5; the PP region 6 extends downward to below the P-well region 4; N + The zone 9 has a U-shaped cross section, extends downward from the top surface of the NP zone (5), and is located between the pair of PP zones 6 in the middle; the N + The bottom surface of region 9 is located between the bottom surface of P-well region 4 and the bottom surface of PP region 6; The gate oxide layer 10 is provided with a plurality of U-shaped cross-sections, each extending downward from the top surface of the NP region 5 to the bottom of the P-well region 4; the bottom surface of the gate oxide layer 10 is located between the bottom surface of the P-well region 4 and the bottom surface of the PP region 6; A Poly layer 11, disposed in the gate oxide layer 10; The top surface of the NP region 5 is provided with a plurality of dielectric layers 12 connected to the gate oxide layer 10 and the Poly layer 11 respectively.

[0027] The source ohmic contact alloy layer 13 is provided with a plurality of layers, each of which is located at the side of the dielectric layer 12 ; the bottom surface of the source ohmic contact alloy layer 13 is connected to the NP region 5 and the PP region 6 , respectively.

[0028] The bottom surface of the Schottky metal 14 is respectively connected to the source ohmic contact alloy layer 13, the dielectric layer 12 and the N + Zone 9 connection.

[0029] The bottom surface of the source metal layer 15 covers the Schottky metal 14, and the middle part is filled downward to N + In the middle groove of zone 9.

[0030] The present invention improves the freewheeling capability of SiC MOSFET devices by setting an SBD structure (composed of Schottky metal 14 and N + The embedded SBD diode increases the vertical direction of N by using the trench structure. + The area of ​​area 9 in contact with the metal, and N + The doping concentration of region 9 is much greater than that of N - Drift layer 3, heavily doped N + Region 9 can also reduce the on-state voltage drop of the embedded SBD diode, greatly improving the freewheeling capability of the SiC MOSFET device and reducing power loss. In the blocking state, the deeply implanted PP region is conducive to shielding the embedded SBD area and the high electric field at the bottom of the gate trench, which can improve the reliability of the device.

Claims

1. A method for preparing a SiC MOSFET device with integrated SBD, characterized in that: The steps include: S100, in heavily doped N + An N-type buffer layer (2) and an N-type buffer layer (2) are sequentially grown on the substrate layer (1). - Drift layer (3); S200, in N - A P-well region (4) is formed on the drift layer (3) by ion implantation, and a heavily doped NP region (5) and a heavily doped PP region (6) are formed on the P-well region (4) by ion implantation; S300, etching on the NP region (5) to form a first trench region (7), and etching on the P-well region (4) to form a second trench region (8); S400, forming N in the second trench region (8) by ion implantation + Area (9); S500, forming a gate oxide layer (10) in the first trench region (7) by thermal oxidation, and forming a Poly layer (11) by deposition; S600, forming a dielectric layer (12) on the Poly layer (11) to isolate the gate electrode and the source electrode metal; S700, forming a source ohmic contact alloy layer (13) on the NP region (5) and the PP region (6) by metal sputtering; S800, in N + A Schottky metal (14) is formed on the region (9), the dielectric layer (12) and the source ohmic contact alloy layer (13) by metal sputtering, and a source metal layer (15) is formed on the Schottky metal (14) by metal sputtering to lead out a source electrode; S900, in N + The back side of the substrate layer (1) reduces N + The substrate layer (1) has a thickness of 1000 nm, and a drain metal layer (16) is formed by metal evaporation to lead out a drain electrode.

2. The method for preparing a SiC MOSFET device with integrated SBD according to claim 1, characterized in that: In step S100, N + The substrate layer (1) is doped with N ions at a doping concentration of 1e 19 cm -2 ±10%.

3. The method for preparing a SiC MOSFET device with integrated SBD according to claim 1, characterized in that: In step S100, the N-type buffer layer (2) is doped with N ions at a doping concentration of 1e 18 cm -2 ±10%.

4. The method for preparing a SiC MOSFET device with integrated SBD according to claim 1, characterized in that: In step S100, N - The drift layer (3) is doped with N ions at a doping concentration of 8e 15 -2e 16 cm -2 , thickness is 5-20um.

5. The method for preparing a SiC MOSFET device with integrated SBD according to claim 1, characterized in that: In step S200, the P-well region (4) is doped with Al ions at a doping concentration of 1e 17 -1e 18 cm -2 .

6. The method for preparing a SiC MOSFET device with integrated SBD according to claim 1, characterized in that: In step S200, the NP region (5) is doped with N ions at a doping concentration of 1e 18 -5e 18 cm -2 .

7. The method for preparing a SiC MOSFET device with integrated SBD according to claim 1, characterized in that: In step S200, the PP region (6) is doped with Al ions at a doping concentration of 5e 18 -1e 19 cm -2 , the injection depth is 1.2-1.5um.

8. The method for preparing a SiC MOSFET device with integrated SBD according to claim 1, characterized in that: In step S300, the etching depth of the first trench region (7) and the second trench region (8) is greater than the implantation depth of the P-well region (4).

9. The method for preparing a SiC MOSFET device with integrated SBD according to claim 1, characterized in that: In step S400, N + Region (9) is doped with N ions at a concentration of 5e 18 -1e 19 cm -2 .

10. A SiC MOSFET device with integrated SBD, comprising: a method for preparing a SiC MOSFET device with integrated SBD according to any one of claims 1 to 9, characterized in that: The drain metal layer (16), N + Substrate layer (1), N-type buffer layer (2), N - A drift layer (3), a source ohmic contact alloy layer (13), a Schottky metal (14) and a source metal layer (15); The N - The drift layer (3) is provided with: P-well region (4), from the N - The top surface of the drift layer (3) extends downward; A plurality of NP regions (5) are provided, each extending downward from the top surface of the P-well region (4) and having a spacing with the bottom surface of the P-well region (4); A plurality of PP regions (6) are provided, each extending downward from the top surface of the P-well region (4) and located at the side of the NP region (5); the PP region (6) extends downward to below the P-well region (4); N + The zone (9) has a U-shaped cross section, extends downward from the top surface of the NP zone (5), and is located between a pair of the PP zones (6) in the middle; the N + The bottom surface of the region (9) is located between the bottom surface of the P-well region (4) and the bottom surface of the PP region (6); The gate oxide layer (10) is provided with a plurality of U-shaped cross-section structures, each extending downward from the top surface of the NP region (5) to the bottom of the P-well region (4); the bottom surface of the gate oxide layer (10) is located between the bottom surface of the P-well region (4) and the bottom surface of the PP region (6); A Poly layer (11) is arranged in the gate oxide layer (10); The top surface of the NP region (5) is provided with a plurality of dielectric layers (12) respectively connected to the gate oxide layer (10) and the Poly layer (11).

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