SOI wafer and preparation method thereof
During the preparation of the SOI wafer, the thinning thickness of the top silicon layer is controlled and appropriately processed before the non-contact planarization process is solved, and a higher surface flatness and integrity are achieved.
Patent Information
- Application Number
- CN202411680930.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-21
- Publication Date
- 2025-03-07
AI Technical Summary
In the prior art, the surface of the SOI wafer has a problem of hole defects after the non-contact planarization process.
By providing the first silicon wafer and the second silicon wafer, ions are injected into the first silicon wafer to form a brittle layer, bonding and thermal reaction peeling to form the top silicon layer, and then an oxidation thinning process is performed and the thinning thickness of the top silicon layer is controlled so that it is within the target thickness range before the contactless planarization process.
It effectively reduces the void defects and surface particles on the surface of SOI wafer, making the wafer surface more flat and intact.
Smart Images
Figure CN119584637A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor technology, and in particular to an SOI wafer and a preparation method thereof. Background Art
[0002] Silicon on insulator (SOI) technology has become one of the mainstream products in most electronic materials fields. The core feature of this special silicon-based semiconductor manufacturing technology is to form a thin top layer of silicon on the insulator. This structure makes SOI devices perform well in many aspects, such as low power consumption, radiation resistance, and high speed.
[0003] There are three main technologies for preparing SOI wafers: the first is oxygen injection separation technology, the second is bonding etch-back technology, and the third is layer transfer technology based on ion implantation. Currently, the most commonly used are bonding etch-back technology and ion implantation-based layer transfer technology. Bonding etch-back technology is to tightly bond two wafers together through bonding technology, and the silicon dioxide layer formed between the wafers is used as an oxide buried layer. Then, the thickness of the wafer on one side is thinned to the required thickness by etching-back technology to form an SOI wafer. Layer transfer technology based on ion implantation is derived from bonding etch-back technology. First, two silicon wafers are prepared, and a silicon dioxide insulating layer is generated on one wafer by thermal oxidation. Then, hydrogen ions are implanted into the silicon wafer by ion implantation, and then the two silicon wafers are bonded, and the silicon wafer implanted with hydrogen ions is peeled off by thermal reaction to form a top silicon layer film.
[0004] When obtaining SOI wafers using layer transfer technology based on ion implantation, it is often necessary to perform an oxidation thinning process and a non-contact planarization process on the SOI wafer. The surface of the top silicon layer obtained after peeling is rough and has a damaged layer. The damaged layer can be removed by the oxidation thinning process, and the surface roughness can be improved by the non-contact planarization process. The non-contact planarization process uses different physical or chemical methods to achieve the improvement of surface flatness. It does not rely on polishing pads and corresponding mechanical forces, can reduce mechanical damage, and improve uniformity. However, there is a problem in the prior art that there are hole defects on the surface of the SOI wafer after the non-contact planarization process. Summary of the invention
[0005] The object of the present invention is to provide a SOI wafer and a method for preparing the same, so as to solve one or more problems in the prior art.
[0006] In order to solve the above problems, the present invention provides a method for preparing an SOI wafer, comprising:
[0007] Providing a first silicon wafer and a second silicon wafer, and implanting ions into the first silicon wafer to form an embrittled layer;
[0008] Bonding the first silicon wafer and the second silicon wafer together, and peeling the first silicon wafer along the embrittled layer by thermal reaction to form a top silicon layer, so as to obtain an SOI wafer; and,
[0009] The SOI wafer is sequentially subjected to an oxidation thinning process and a non-contact planarization process, wherein when the oxidation thinning process is performed, the thinning thickness of the top silicon layer is controlled so that before the non-contact planarization process is performed, the thickness of the top silicon layer is within a target thickness range.
[0010] Optionally, in the method for preparing the SOI crystal edge, the thickness of the top silicon layer obtained by peeling is X μm, and before performing the non-contact planarization process, the thickness of the top silicon layer is Y μm, X-0.13<Y<X-0.05.
[0011] Optionally, in the method for preparing the SOI crystal edge, the non-contact planarization process is a thermal treatment planarization process.
[0012] Optionally, in the method for preparing the SOI crystal edge, the process parameters of the heat treatment planarization process include:
[0013] The temperature is 1100-1200° C., the time is 30-300 min, and the gas used is an inert gas including argon.
[0014] Optionally, in the method for preparing the SOI wafer edge, the method further comprises: forming an oxide layer on the surface of the first silicon wafer;
[0015] When ions are implanted into the first silicon wafer, ions are implanted into the first silicon wafer from a side of the first silicon wafer on which the oxide layer is formed to form the embrittled layer.
[0016] Optionally, in the method for preparing the SOI crystal edge, the thickness of the oxide layer is less than 0.3 μm.
[0017] Optionally, in the method for preparing the SOI crystal edge, the ion implantation energy when forming the embrittlement layer is 20 to 80 KeV, and the implantation depth is 0.2 to 0.6 μm.
[0018] Optionally, in the method for preparing the SOI wafer edge, when the first silicon wafer and the second silicon wafer are bonded together, the thickness of the buried oxide layer between the first silicon wafer and the second silicon wafer is 0.01 to 2 μm.
[0019] Optionally, in the method for preparing the SOI wafer edge, the ions implanted into the first silicon wafer are hydrogen ions, or the ions implanted into the first silicon wafer are hydrogen ions and helium ions.
[0020] The present invention provides an SOI wafer, which is prepared by the preparation method as described in any of the preceding items, has no void defects on the surface of the SOI wafer, and in a light scattering channel with a size greater than or equal to 65nm, the number of particles on the surface of the SOI wafer is less than 30.
[0021] In summary, the SOI wafer and its preparation method provided by the present invention include: providing a first silicon wafer and a second silicon wafer, injecting ions into the first silicon wafer to form an embrittled layer; bonding the first silicon wafer and the second silicon wafer together, and using a thermal reaction to peel off the first silicon wafer along the embrittled layer to form a top silicon layer to obtain an SOI wafer; and sequentially performing an oxidation thinning process and a non-contact planarization process on the SOI wafer, wherein when performing the oxidation thinning process, the thinning thickness of the top silicon layer is controlled so that before performing the non-contact planarization process, the thickness of the top silicon layer is within a target thickness range. The SOI wafer preparation method provided by the present invention controls the thickness of the top silicon layer during the non-contact planarization process, so that the number of surface void defects and surface particles in the prepared SOI wafer is reduced. BRIEF DESCRIPTION OF THE DRAWINGS
[0022] Figure 1 A flow chart of a method for preparing an SOI wafer provided in an embodiment of the present invention;
[0023] Figure 2 to Figure 4 for Figure 1 Schematic diagram of the structure corresponding to each step;
[0024] Figure 5 This is a graph showing the particle inspection results of Comparative Example 1 in an embodiment of the present invention;
[0025] Figure 6 This is a scanning electron microscope image of comparative example 1 in an embodiment of the present invention;
[0026] Figure 7 This is a graph showing the particle inspection results of Comparative Example 2 in an embodiment of the present invention;
[0027] Figure 8 This is a scanning electron microscope image of comparative example 2 in the embodiment of the present invention;
[0028] Fig. 9 This is a graph showing the particle inspection results of Comparative Example 3 in an embodiment of the present invention;
[0029] Fig.10 This is a scanning electron microscope image of comparative example 3 in the embodiment of the present invention;
[0030] Fig.11 A statistical diagram showing the change in the number of void defects with oxidation thinning thickness in an embodiment of the present invention;
[0031] The descriptions of the reference numerals are as follows:
[0032] 10 - first silicon wafer; 20 - oxide layer; 30 - embrittlement layer; 40 - second silicon wafer; 101 - top silicon layer. DETAILED DESCRIPTION
[0033] The following is a further detailed description of the SOI wafer and the method for preparing the same proposed by the present invention in conjunction with the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are all in non-precise proportions, which are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. In addition, the structure shown in the drawings is often a part of the actual structure. In particular, the emphasis required to be shown in each drawing is different, and sometimes different proportions are used. It should be recognized that relative terms such as "above", "below", "top", "bottom", "above" and "below" shown in the drawings can be used to describe the relationship between various elements. These relative terms are intended to cover different orientations of elements other than the orientations depicted in the drawings. For example, if the device is inverted relative to the view in the drawings, for example, an element described as "above" another element will now be below the element. It should also be understood that, unless otherwise specified or indicated, the terms "first", "second", "third" and the like in the specification are only used to distinguish between the various components, elements, steps, etc. in the specification, rather than to represent the logical relationship or sequential relationship between the various components, elements, steps, etc.
[0034] like Figure 1 As shown, an embodiment of the present invention provides a method for preparing an SOI wafer, comprising the following steps:
[0035] S1, providing a first silicon wafer and a second silicon wafer, and implanting ions into the first silicon wafer to form an embrittled layer;
[0036] S2, bonding the first silicon wafer and the second silicon wafer together, and peeling off the first silicon wafer by thermal reaction to form a top silicon layer, so as to obtain an SOI wafer; and,
[0037] S3, sequentially performing an oxidation thinning process and a planarization process on the SOI wafer, wherein when performing the oxidation thinning process, the thinning thickness of the top silicon layer is controlled so that before performing the non-contact planarization process, the thickness of the top silicon layer is within a target thickness range.
[0038] By using the SOI wafer preparation method provided by the embodiment of the present invention, the thickness of the top silicon layer is controlled during the non-contact planarization process, so that the surface void defects and the number of surface particles of the prepared SOI wafer are reduced.
[0039] The following combination Figure 2 to Figure 4The method for preparing the SOI wafer provided in the embodiment of the present invention is further described in detail.
[0040] First, execute step S1, see Figure 2 , a first silicon wafer 10 and a second silicon wafer 40 are provided, the first silicon wafer 10 is used as a device wafer, that is, used to form a device layer of an SOI wafer, and the second silicon wafer 40 is used as a support wafer, that is, used to form a substrate layer of the SOI wafer.
[0041] Optionally, step S1 further includes: forming an oxide layer 20 on the surface of the first silicon wafer 10, and implanting ions into the first silicon wafer 10 from the side of the first silicon wafer 10 where the oxide layer 20 is formed to form an embrittlement layer 30. The oxide layer 20 can be formed by a thermal oxidation process on the surface of the first silicon wafer 10. The oxide layer 20 is used to isolate the first silicon wafer 10 from the second silicon wafer 40 after the two are bonded.
[0042] The first silicon wafer 10 and the second silicon wafer 40 can be obtained by cutting a crystal ingot grown by a direct method. The specific process may include: providing a silicon crystal ingot grown by a direct pulling method, the crystal growth direction is (100) or (110) or (111), rolling the edge of the crystal ingot to a target diameter and cutting it to obtain a crystal segment, slicing the crystal segment, and obtaining the final silicon wafer through grinding, polishing and cleaning to obtain the first silicon wafer 10 and the second silicon wafer 40. Optionally, the thickness of the first silicon wafer 10 and the second silicon wafer 40 are both 500 to 800 μm. In addition, optionally, the ions injected into the first silicon wafer 10 are hydrogen ions, or the ions injected into the first silicon wafer 10 are hydrogen ions and helium ions.
[0043] The thickness of the oxide layer 20 affects the ion implantation depth at the same implantation energy, thereby affecting the thickness of the subsequently formed top silicon layer 101. Preferably, the thickness of the oxide layer 20 is less than 0.3 μm, the ion implantation energy when forming the embrittlement layer 30 is 20-80 KeV, and the implantation depth is 0.2-0.6 μm, so that the top silicon layer 101 of the final target thickness can be obtained after the first silicon wafer 10 is peeled off.
[0044] Next, execute step S2, see Figure 4 , the first silicon wafer 10 and the second silicon wafer 40 are bonded together. When the first silicon wafer 10 and the second silicon wafer 40 are bonded together, the two are isolated by a buried oxide layer.
[0045] Optionally, the oxide layer 20 on the surface of the first silicon wafer 10 constitutes the buried oxide layer; or, the oxide layer 20 is formed on the surface of the second silicon wafer 40, and the oxide layer on the surface of the second silicon wafer 40 constitutes the buried oxide layer; or, an oxide layer 20 is also formed on the surface of the second silicon wafer 40, and the oxide layer 20 on the surface of the first silicon wafer 10 and the oxide layer 20 on the surface of the second silicon wafer 40 together constitute the buried oxide layer, and the thickness of the buried oxide layer ranges from 0.01 to 2 μm.
[0046] After the first silicon wafer 10 and the second silicon wafer 40 are bonded together, Figure 5 The first silicon wafer 10 is peeled off along the embrittled layer 30 by thermal reaction to form a top silicon layer 101 , thereby obtaining an SOI wafer with a thinner top silicon layer 101 .
[0047] The embrittled layer 30 has an upper surface and a lower surface relative to each other, and the upper surface is closer to the oxide layer 20 than the lower surface. When the first silicon wafer 10 is peeled off by thermal reaction, the first silicon wafer 10 is divided into two along the lower surface of the hydrogen ion implantation layer 30, so that a part of the thickness of the first silicon wafer 10 falls off to form the top silicon layer 101.
[0048] Next, step S3 is performed to perform an oxidation thinning process and a non-contact planarization process on the SOI wafer.
[0049] The technicians of the present invention have studied and found that the reason why the problem of hole defects on the surface of the SOI wafer after the non-contact planarization process exists in the prior art is that if the oxidation time of the SOI wafer surface is too long when performing the oxidation thinning process, it will cause the SOI wafer surface to deteriorate, and thus after the planarization process, hole defects are likely to appear on the SOI wafer surface.
[0050] In view of this, when step S3 is executed, the thickness of the top silicon layer 101 thinned by the oxidation thinning process is controlled to avoid the occurrence of the defect.
[0051] Preferably, if the thickness of the top silicon layer 101 obtained by stripping is Xμm, the thickness of the top silicon layer 101 thinned by the oxidation thinning process is controlled so that after performing the oxidation thinning process and before performing the non-contact planarization process, the thickness of the top silicon layer 101 is Yμm, X-0.13<Y<X-0.05, wherein XY is the thickness of the top silicon layer thinned by the oxidation thinning process. Fig.11As shown, when the thickness XY of the top silicon layer 101 thinned by the oxidation thinning process satisfies: 0.05<XY<0.13, after performing the non-contact planarization process, the number of void defects on the surface of the SOI wafer is effectively controlled.
[0052] Preferably, the non-contact planarization process is a heat treatment planarization process. Optionally, the process parameters of the heat treatment planarization process include: a temperature of 1100-1200° C., a time of 30-300 min, and an inert gas including argon. The inert gas may also include hydrogen.
[0053] In addition, optionally, after performing the non-contact planarization process, a step of performing a final thinning process on the SOI wafer is also included, so that the thickness of the top silicon layer 101 is finally 0.01-0.5 μm.
[0054] An embodiment of the present invention also provides an SOI wafer, which is prepared using the SOI wafer preparation method provided in this embodiment. Therefore, there is no void defect on the surface of the SOI wafer, and in a light scattering channel with a size greater than or equal to 65nm, the number of particles on the surface of the SOI wafer is less than 30.
[0055] The method for preparing the SOI wafer provided in the embodiment of the present invention is further described below in combination with several comparative examples.
[0056] [Comparative Example 1]
[0057] Provide silicon ingots grown by Czochralski method, the crystal growth direction is <100> The silicon ingot is edge-rolled to the target diameter and then cut into sections in the direction of <110> .
[0058] The crystal segments are sliced, and after grinding, polishing and cleaning, the final silicon wafers are obtained with a thickness of 773 μm, which are used as device wafers.
[0059] Another crystal segment is provided, and a final silicon wafer is obtained through grinding, polishing and cleaning, with a thickness of 777 μm, as a support sheet.
[0060] The device wafer is thermally oxidized to obtain a buried oxide layer, and the buried oxide layer has a thickness of 0.05 μm.
[0061] The oxidized device wafer is implanted with hydrogen ions at an implantation energy of 27 KeV and an implantation depth of 0.31 μm.
[0062] The device wafer and the support wafer are bonded, and then a peeling transfer process is performed to obtain an SOI wafer. After peeling, the thickness of the top silicon layer is 0.31 μm. The top silicon layer is subjected to oxidation thinning, heat treatment flattening process and final thinning, and the final thickness of the top silicon layer is 0.02 μm.
[0063] Before the heat treatment planarization process, the thickness of the top silicon layer is 0.16 μm, the planarization temperature is 1170° C., the time is 120 min, and the gas is argon.
[0064] [Comparative Example 2]
[0065] Provide silicon ingots grown by Czochralski method, the crystal growth direction is <100> The silicon ingot is edge-rolled to the target diameter and then cut into sections in the direction of <110> .
[0066] The crystal segments are sliced, and after grinding, polishing and cleaning, the final silicon wafers are obtained with a thickness of 773 μm, which are used as SOI device wafers.
[0067] Another crystal segment is provided, and a final silicon wafer is obtained through grinding, polishing and cleaning, with a thickness of 777 μm, as a support sheet.
[0068] The device wafer is thermally oxidized to obtain a buried oxide layer, and the buried oxide layer has a thickness of 0.05 μm.
[0069] The oxidized device wafer is implanted with hydrogen ions at an implantation energy of 27 KeV and an implantation depth of 0.31 μm.
[0070] The device wafer and the support wafer are bonded, and then a peeling transfer process is performed to obtain an SOI wafer. After peeling, the thickness of the top silicon layer is 0.31 μm. The top silicon layer is subjected to oxidation thinning, heat treatment flattening process and final thinning process, and the final thickness of the top silicon layer is 0.02 μm.
[0071] Before the heat treatment planarization process, the thickness of the top silicon layer is 0.21 μm, the planarization temperature is 1170° C., the time is 120 min, and the gas is argon.
[0072] [Comparative Example 3]
[0073] Provide silicon ingots grown by Czochralski method, the crystal growth direction is <100> The silicon ingot is edge-rolled to the target diameter and then cut into sections in the direction of <110> .
[0074] The crystal segments are sliced, and after grinding, polishing and cleaning, the final silicon wafers are obtained with a thickness of 773 μm, which are used as SOI device wafers.
[0075] Another crystal segment is provided, and a final silicon wafer is obtained through grinding, polishing and cleaning, with a thickness of 777 μm, as a support sheet.
[0076] The device wafer is thermally oxidized to obtain a SOI buried oxide layer, and the buried oxide layer has a thickness of 0.05 μm.
[0077] The oxidized device wafer is implanted with hydrogen ions at an implantation energy of 27 KeV and an implantation depth of 0.31 μm.
[0078] The device wafer and the support wafer are bonded, and then a peeling transfer process is performed to obtain an SOI wafer. After peeling, the thickness of the top silicon layer is 0.31 μm. The top silicon layer is subjected to oxidation thinning, heat treatment flattening process and final thinning process, and the final thickness of the top silicon layer is 0.02 μm.
[0079] Before the heat treatment planarization process, the thickness of the top silicon layer is 0.26 μm, the planarization temperature is 1170° C., the time is 120 min, and the gas is argon.
[0080] See also Figures 5 to 10 , the comparison results of the three comparison examples are as follows:
[0081] Table 1
[0082]
[0083] It can be seen from Table 1 that in Comparative Examples 1 and 3, X and Y do not satisfy: X-0.13<Y<X-0.05, and in Comparative Example 2, X and Y satisfy: X-0.13<Y<X-0.05. Compared with Comparative Example 1 and Comparative Example 2, the number of particles on the surface of the SOI wafer is reduced. In the light scattering channel with a size greater than or equal to 65nm (LLS65), the number of surface particles is less than 30, and there are no void-type defects on the surface. It can be seen that the preparation method provided by the embodiment of the present invention can solve the problem of rough SOI surface and reduce surface hole defects.
[0084] In summary, the method for preparing an SOI wafer provided in an embodiment of the present invention includes: providing a first silicon wafer and a second silicon wafer, injecting ions into the first silicon wafer to form an embrittled layer; bonding the first silicon wafer and the second silicon wafer together, and using a thermal reaction to peel off the first silicon wafer along the embrittled layer to form a top silicon layer to obtain an SOI wafer; and, sequentially performing an oxidation thinning process and a non-contact planarization process on the SOI wafer, wherein when performing the oxidation thinning process, the thinning thickness of the top silicon layer is controlled so that before performing the non-contact planarization process, the thickness of the top silicon layer is within a target thickness range. The method for preparing an SOI wafer provided by the present invention controls the thickness of the top silicon layer during the non-contact planarization process, so that the number of surface void defects and surface particles in the prepared SOI wafer is reduced.
[0085] It should be noted that, although the present invention has been disclosed as a preferred embodiment, any person skilled in the art can make many possible changes and modifications to the technical solution of the present invention by using the technical content disclosed above without departing from the scope of the technical solution of the present invention, or modify it into an equivalent embodiment of equivalent changes. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention without departing from the content of the technical solution of the present invention still falls within the scope of protection of the technical solution of the present invention.
Claims
1. A method for preparing a SOI wafer, characterized in that: include: Providing a first silicon wafer and a second silicon wafer, and implanting ions into the first silicon wafer to form an embrittled layer; Bonding the first silicon wafer and the second silicon wafer together, and peeling the first silicon wafer along the embrittled layer by thermal reaction to form a top silicon layer, so as to obtain an SOI wafer; as well as, The SOI wafer is sequentially subjected to an oxidation thinning process and a non-contact planarization process, wherein when the oxidation thinning process is performed, the thinning thickness of the top silicon layer is controlled so that before the non-contact planarization process is performed, the thickness of the top silicon layer is within a target thickness range.
2. The method for preparing an SOI crystal edge according to claim 1, characterized in that: The thickness of the top silicon layer obtained by stripping is X μm. Before performing the non-contact planarization process, the thickness of the top silicon layer is Y μm, X-0.13<Y<X-0.
05.
3. The method for preparing an SOI wafer according to claim 1, wherein: The non-contact planarization process is a thermal treatment planarization process.
4. The method for preparing an SOI wafer according to claim 3, wherein: The process parameters of the thermal treatment planarization process include: The temperature is 1100-1200° C., the time is 30-300 min, and the gas used is an inert gas including argon.
5. The method for preparing an SOI wafer according to claim 1, wherein: The method further comprises: forming an oxide layer on the surface of the first silicon wafer; When ions are implanted into the first silicon wafer, ions are implanted into the first silicon wafer from a side of the first silicon wafer on which the oxide layer is formed to form the embrittled layer.
6. The method for preparing an SOI wafer according to claim 5, characterized in that: The thickness of the oxide layer is less than 0.3 μm.
7. The method for preparing an SOI wafer according to claim 5, wherein: The ion implantation energy when forming the embrittlement layer is 20 to 80 KeV, and the implantation depth is 0.2 to 0.6 μm.
8. The method for preparing an SOI wafer according to claim 1, wherein: When the first silicon wafer and the second silicon wafer are bonded together, the thickness of the buried oxide layer between the first silicon wafer and the second silicon wafer is 0.01-2 μm.
9. The method for preparing an SOI wafer according to claim 1, wherein: The ions implanted into the first silicon wafer are hydrogen ions, or the ions implanted into the first silicon wafer are hydrogen ions and helium ions.
10. An SOI wafer, characterized in that: The SOI wafer is prepared by the preparation method according to any one of claims 1 to 9, the surface of the SOI wafer has no void defects, and the number of particles on the surface of the SOI wafer is less than 30 in a light scattering channel with a size greater than or equal to 65 nm.