Integrated internal line transfer CCD structure and manufacturing method thereof

Abstract

The invention relates to a charge-coupled device manufacturing technology, in particular to an integrated internal line transfer CCD (charge coupled device) structure and a manufacturing method thereof, and the structure comprises a gate medium, a polysilicon gate, a metal front backflow layer, a metal bus, a surface planarization layer and a metasurface structure layer; the polysilicon gate is formed on the gate medium; the metal front backflow layer covers the surface of the polysilicon gate, a contact hole is formed in the metal front backflow layer, and the position of the contact hole corresponds to the upper end face of the polysilicon gate; the metal bus is stacked on the upper end face of the metal front backflow layer, and the metal bus fills the contact hole. The surface planarization layer covers the surface of the metal bus and surrounds the metal front backflow layer; the metasurface structure layer is arranged on the upper end face of the surface planarization layer; a shading structure in an original internal line transfer CCD is replaced, the device process is simplified, the focusing function is added, the device sensitivity is improved, a polarization sensitive structure is introduced, and polarization characteristic detection of a chip is achieved.

Description

Technical Field

[0001] The invention relates to a charge coupled device manufacturing technology, in particular to an integrated internal line transfer CCD structure and a manufacturing method thereof. Background Art

[0002] The pixel structure of the internal transfer CCD can be divided into a bottom part and an upper part; the bottom part includes the functional area in the silicon bottom, and the upper part includes polysilicon electrodes, metal leads and light-shielding structures. A photosensitive area and a storage area are set in the functional area, and both areas are formed by injection. The photosensitive area is used to receive light signals and generate photogenerated electrons. The generated photogenerated electrons are first transferred to the storage area and then transferred to the peripheral amplifier circuit for output. The working mode of the internal transfer CCD requires that the photosensitive area is sensitive to light, and all areas except the photosensitive area must be shielded.

[0003] Typical light shielding structures of existing internal transfer CCDs are as follows: Figure 1 As shown, after the relevant production of the polysilicon gate is completed, a thin dielectric insulating layer is deposited on the polysilicon gate, and then a light shielding layer is formed using metal aluminum (Al) or refractory metal tungsten (W), and then the metal electrode is produced. The light shielding layer is formed near the polysilicon gate, which can effectively shield the oblique incident light and solve the light leakage problem. Finally, in order to achieve better light response, the conventional internal line transfer CCD integrates a microlens structure on the surface to achieve the focusing function. However, when the light shielding layer of the existing structure uses metal tungsten (W) or metal aluminum (Al) as the light shielding metal material, the light shielding process is usually made before or after the reflow layer; if the metal Al structure is used, the step coverage limited by the process is poor, and the light shielding performance is greatly affected. Therefore, it must be made after the reflow process, and the requirements for the reflow process are very high. At the same time, the temperature that the metal Al can withstand is relatively low, which has great restrictions on the subsequent processes. If metal W is used to make the light shielding layer, it can withstand high temperatures and has good coverage. It can be made before the reflow layer, but the stress of the metal W is large, which is easy to cause device deformation and leakage, and the structural requirements of the device are high. In addition, the closer the location is to the polysilicon gate and the photosensitive area of ​​the pixel, the greater the impact of the process on the device, and the more likely the device is to fail. Therefore, the existing light-blocking metal process is both complex and has poor compatibility. Summary of the invention

[0004] In order to solve the above problems, the present invention provides an integrated inline transfer CCD structure and a manufacturing method thereof.

[0005] In the first aspect, the present invention provides an integrated inline transfer CCD structure, including a gate dielectric 1, a polysilicon gate 2, a local planarization layer 3, a metal bus 5, a surface planarization layer 6 and a super surface structure layer 7; the polysilicon gate 2 is formed on the gate dielectric 1; the local planarization layer 3 covers the surface of the polysilicon gate 2, and a contact hole 4 is provided on the local planarization layer 3, and the position of the contact hole 4 corresponds to the upper end surface of the polysilicon gate 2; the metal bus 5 is stacked on the upper end surface of the local planarization layer 3 and fills the contact hole 4; the surface planarization layer 6 covers the surface of the metal bus 5 and surrounds the local planarization layer 3; the super surface structure layer 7 is on the upper end surface of the surface planarization layer 6.

[0006] Furthermore, the gate dielectric 1 is made of SiO2 or SiO2 / Si3N4, and has a thickness of 10nm to 200nm.

[0007] Furthermore, the local planarization layer 3 is made of PSG or BPSG material, and has a thickness of 100 nm to 800 nm.

[0008] Furthermore, the surface planarization layer 6 is made of USG or PSG material, and has a thickness of 500nm to 1000nm.

[0009] Furthermore, the super surface structure layer 7 is made of integrated circuit compatible metal or heavy metal, and its thickness is 50nm to 1000nm.

[0010] In a second aspect, based on the integrated internal line transfer CCD structure proposed in the first aspect, the present invention provides a method for manufacturing an integrated internal line transfer CCD structure, comprising the following steps:

[0011] S1. Using a gate oxidation furnace to make a gate dielectric in a high temperature range of 800°C to 1200°C;

[0012] S2. Using chemical vapor deposition to deposit a polysilicon gate on the upper end surface of the gate dielectric;

[0013] S3. A local planarization layer is formed by chemical vapor deposition on the surface of the polysilicon gate; and a contact hole is provided on the local planarization layer by photolithography or etching process;

[0014] S4. Depositing a metal bus on the upper end surface of the local planarization layer and in the contact hole;

[0015] S5. A surface planarizing layer is formed by depositing a metal bus surface using chemical vapor deposition, and a surface planarizing layer is formed by chemical mechanical polishing of SiO2;

[0016] S6. Forming a super surface structure layer on the surface planarization layer by physical vapor deposition, wherein the super surface structure layer is provided with through holes.

[0017] Furthermore, the chemical mechanical polishing process of SiO2 is combined with a polishing load pressure parameter and a rotation speed parameter, the polishing load pressure parameter has a value range of 3 to 9 psi, and the rotation speed parameter has a value range of 80 to 150 rpm.

[0018] Furthermore, the deposition method used in step S4 is magnetron sputtering, thermal evaporation, or electron beam evaporation.

[0019] Beneficial effects of the present invention:

[0020] The present invention provides an integrated internal line transfer CCD structure, which mainly designs a super surface structure layer on the upper layer of the internal line transfer CCD to form a composite functional layer with focusing, polarization sensitivity and shading; the composite functional layer replaces the shading structure in the original internal line transfer CCD, simplifies the device process, increases the focusing function, improves the device sensitivity, introduces the polarization sensitive structure, and realizes the polarization characteristic detection of the chip.

[0021] The present invention adopts a super-surface focusing structure, which can effectively focus light into a single pixel, thus moving the light shielding layer inside the pixel to the device surface, reducing the difficulty of device manufacturing and avoiding device failure. In addition, the super-surface structure can also detect the polarization state of visible light, increasing the diversity of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 A schematic diagram of a typical light shielding structure of an existing internal transfer CCD;

[0023] Figure 2 A schematic cross-sectional view of the integrated internal line transfer CCD structure provided by the present invention;

[0024] Figure 3 A schematic diagram of the top surface of the integrated internal line transfer CCD structure provided by the present invention;

[0025] Among them, 1-gate dielectric, 2-polysilicon gate, 4-contact hole, 3-local planarization layer, 5-metal bus, 6-surface planarization layer, 7-super surface structure layer. DETAILED DESCRIPTION

[0026] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0027] The light shielding layer of the internal transfer CCD is an important layer to ensure the normal operation of the device. The main purpose of the light shielding layer is to control the transmittance and directionality of light. The metasurface structure is a structure made of graphic metal materials. Through detailed design, it can have the functions of metal opacity and controlling the incidence of light. The metasurface structure is added to the existing internal transfer CCD manufacturing process, and the light shielding layer is removed. This not only improves the light shielding effect of the device, but also further realizes functions such as optical fiber deflection, focusing, and polarization sensitivity, significantly increasing the diversified applications of the internal transfer CCD. Therefore, the present invention provides an integrated internal transfer CCD structure and a manufacturing method thereof.

[0028] The present invention provides an integrated internal transfer CCD structure, such as Figure 2 As shown, it includes a gate dielectric 1, a polysilicon gate 2, a local planarization layer 3, a metal bus 5, a surface planarization layer 6 and a super surface structure layer 7; the polysilicon gate 2 is formed on the gate dielectric 1; the local planarization layer 3 covers the surface of the polysilicon gate 2, and a contact hole 4 is arranged on the local planarization layer 3, and the position of the contact hole 4 corresponds to the upper end surface of the polysilicon gate 2; the metal bus 5 is stacked on the upper end surface of the local planarization layer 3, and the metal bus 5 fills the contact hole 4; the surface planarization layer 6 covers the surface of the metal bus 5 and surrounds the local planarization layer 3; the super surface structure layer 7 is on the upper end surface of the surface planarization layer 6.

[0029] Specifically, the gate dielectric 1 is made of SiO2 or SiO2 / Si3N4, and has a thickness of 10nm to 200nm. The gate dielectric is usually a dense film system formed by a high temperature process, and the temperature is generally 800°C to 1200°C.

[0030] Specifically, the polysilicon gate 2 is made by chemical vapor deposition (CVD) and has a thickness of 100nm to 600nm. The polysilicon gate 2 is also called a polysilicon electrode, which is mainly used as the gate of the MOS tube and the signal transfer electrode of the photosensitive area of ​​the internal line transfer CCD. The polysilicon can be made once or multiple times according to the process capability.

[0031] Specifically, the local planarization layer 3 may be made of PSG or BPSG, deposited by chemical vapor deposition (CVD), and has a thickness of 100 nm to 800 nm. The local planarization layer 3 is used to isolate the polysilicon gate 2 and the metal bus 5 .

[0032] Specifically, the material of the metal bus 5 can be selected from metal aluminum or aluminum alloy, and the deposition method can be magnetron sputtering, thermal evaporation, electron beam evaporation and the like.

[0033] Specifically, Figure 2As shown, between the gate dielectric 1 and the super surface structure layer 7, all areas except the polysilicon gate 2, the local planarization layer 3, and the metal bus 5 are the surface planarization layer 6.

[0034] Specifically, the material of the surface planarization layer 6 can be USG, PSG, etc., and the deposition method is chemical vapor deposition (CVD), and its thickness is 500nm to 1000nm. The function of the surface planarization layer 6 is to isolate the metal bus 5 and the super surface structure layer 7; the thickness optimization of the surface planarization layer 6 must be carried out in combination with the step height and the metal front reflow layer material.

[0035] Specifically, the super surface structure layer 7 can be made of integrated circuit compatible metal (Al, Cu) or heavy metal (Au, Ag, etc.), and the deposition method can be physical vapor deposition (PVD), and its thickness is 50nm to 1000nm. The thickness of the super surface structure layer 7 must be selected by comprehensively considering factors such as light shielding ability, resistivity, and stress.

[0036] The present invention provides a method for manufacturing an integrated internal transfer CCD structure, such as Figure 2 , Figure 3 As shown, the following steps are included:

[0037] S1. Using a gate oxidation furnace to make a gate dielectric in a high temperature range of 800°C to 1200°C;

[0038] Specifically, step S1 also includes active area implantation. The active area in this structure includes the CCD photosensitive region and the attached MOS amplifier region, so the active area implantation includes the source, drain, gate of the MOS amplifier, and the polysilicon under-gate implantation of the photosensitive region. The active area implantation is performed using an ion implanter. For different active area functions, the implantation dose and energy are different. The implantation types are B, P, As, etc. The implantation energy is 50keV to 2000keV, and the implantation dose is 2E11 to 1E16Atoms / cm 2 .

[0039] S2. Using chemical vapor deposition to deposit a polysilicon gate on the upper end surface of the gate dielectric;

[0040] S3. A local planarization layer is formed by chemical vapor deposition on the surface of the polysilicon gate; and a contact hole is provided on the local planarization layer by photolithography or etching process;

[0041] S4. Depositing a metal bus at the contact hole and its surrounding position in the local planarization layer;

[0042] S5. A surface planarization layer is formed by depositing a metal bus surface by chemical vapor deposition, and a surface planarization process is performed by using a SiO2 chemical mechanical polishing (Chemical Mechanical Polish, CMP) process;

[0043] Specifically, the purpose of CMP surface planarization is to obtain the planarization of the surface of the inline transfer CCD chip. The chemical mechanical polishing process of SiO2 is combined with a polishing load pressure parameter and a rotation speed parameter. The polishing load pressure parameter has a value range of 3 to 9 psi, and the rotation speed parameter has a value range of 80 to 150 rpm.

[0044] S6. Forming a super surface structure layer on the surface planarization layer by physical vapor deposition, wherein the super surface structure layer is provided with through holes.

[0045] Specifically, through holes are made on the super surface structure layer by photolithography, etching and other processes, and various etching schemes such as bowl-shaped, sloped, and straight holes can be selected. The through holes are not located on the pixel structure, so they are not drawn in the structural schematic diagram of the present invention.

[0046] Specifically, the sensitivity of the internal transfer CCD needs to be further improved in subsequent processes, and a microlens structure will be further made on its surface.

[0047] In the present invention, unless otherwise clearly stipulated and limited, the terms such as "installation", "setting", "connection", "fixation" and "rotation" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral one; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium; it can be the internal connection of two elements or the interaction relationship between two elements. Unless otherwise clearly defined, ordinary technicians in this field can understand the specific meanings of the above terms in the present invention according to the specific circumstances.

[0048] Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the appended claims and their equivalents.

Claims

1. An integrated inline transfer CCD structure, characterized in that: The invention comprises a gate dielectric (1), a polysilicon gate (2), a local planarization layer (3), a metal bus (5), a surface planarization layer (6) and a super surface structure layer (7); the polysilicon gate (2) is formed on the gate dielectric (1); the local planarization layer (3) covers the surface of the polysilicon gate (2), a contact hole (4) is provided on the local planarization layer (3), and the position of the contact hole (4) corresponds to the upper end surface of the polysilicon gate (2); the metal bus (5) is stacked on the upper end surface of the local planarization layer (3) and fills the contact hole (4); the surface planarization layer (6) covers the surface of the metal bus (5) and surrounds the local planarization layer (3); and the super surface structure layer (7) is on the upper end surface of the surface planarization layer (6).

2. The integrated inline transfer CCD structure according to claim 1, characterized in that: The gate dielectric (1) is made of SiO2 or SiO2 / Si3N4 and has a thickness of 10nm to 200nm.

3. The integrated inline transfer CCD structure according to claim 1, characterized in that: The local planarization layer (3) is made of PSG or BPSG material and has a thickness of 100nm to 800nm.

4. The integrated inline transfer CCD structure according to claim 1, characterized in that: The surface planarization layer (6) is made of USG or PSG material and has a thickness of 500nm to 1000nm.

5. The integrated inline transfer CCD structure according to claim 1, characterized in that: The super surface structure layer (7) is made of integrated circuit compatible metal or heavy metal and has a thickness of 50nm to 1000nm.

6. A method for manufacturing an integrated inline transfer CCD structure, characterized in that: The following steps are involved: S1. Using a gate oxidation furnace to make a gate dielectric in a high temperature range of 800°C to 1200°C; S2. Using chemical vapor deposition to deposit a polysilicon gate on the upper end surface of the gate dielectric; S3. A local planarization layer is formed by chemical vapor deposition on the surface of the polysilicon gate; and a contact hole is provided on the local planarization layer by photolithography or etching process; S4. Depositing a metal bus on the upper end surface of the local planarization layer and in the contact hole; S5. A surface planarizing layer is formed by depositing a metal bus surface using chemical vapor deposition, and a surface planarizing layer is formed by chemical mechanical polishing of SiO2; S6. Forming a super surface structure layer on the surface planarization layer by physical vapor deposition, wherein the super surface structure layer is provided with through holes.

7. The method for manufacturing an integrated internal transfer CCD structure according to claim 6, characterized in that: The chemical mechanical polishing process of SiO2 combines a polishing load pressure parameter and a rotation speed parameter. The polishing load pressure parameter has a value range of 3 to 9 psi, and the rotation speed parameter has a value range of 80 to 150 rpm.

8. The method for manufacturing an integrated internal transfer CCD structure according to claim 6, characterized in that: The deposition method used in step S4 is magnetron sputtering, thermal evaporation, or electron beam evaporation.

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