Display device

Abstract

The invention relates to a display device. A display device according to one embodiment includes: a lower electrode; a rib portion having a pixel opening overlapping the lower electrode and covering an end portion of the lower electrode; a partition wall including a bottom portion disposed on the rib portion, a lower portion disposed on the bottom portion, and an upper portion disposed on the lower portion and protruding from a side surface of the lower portion; an organic layer that is in contact with the lower electrode through the pixel opening and emits light in response to application of a voltage; an upper electrode covering the organic layer and in contact with at least one of the bottom portion and the lower portion; and a transparent conductive oxide layer disposed between the rib portion and the bottom portion.

Description

[0001] Cross-references to related applications

[0002] This application claims priority based on Japanese Patent Application No. 2023-144496 filed on September 6, 2023, and cites all the contents described in the Japanese patent application. Technical Field

[0003] An embodiment of the present invention relates to a display device. Background Art

[0004] In recent years, display devices using organic light emitting diodes (OLEDs) as display elements have been put into practical use. In such display devices, a technology capable of improving the yield is required. Summary of the invention

[0005] In general, according to one embodiment, a display device comprises: a lower electrode; a rib having a pixel opening overlapping with the lower electrode and covering an end of the lower electrode; a partition wall including a bottom portion arranged on the rib, a lower portion arranged on the bottom, and an upper portion arranged on the lower portion and protruding from a side surface of the lower portion; an organic layer contacting the lower electrode through the pixel opening and emitting light in response to application of a voltage; an upper electrode covering the organic layer and contacting at least one of the bottom and the lower portion; and a transparent conductive oxide layer arranged between the rib and the bottom.

[0006] According to another embodiment, a display device comprises: a lower electrode; a rib having a pixel opening overlapping with the above-mentioned lower electrode and covering an end portion of the above-mentioned lower electrode; a partition wall including a bottom portion arranged on the above-mentioned rib portion, a lower portion arranged on the above-mentioned bottom portion, and an upper portion arranged on the above-mentioned lower portion and protruding from a side surface of the above-mentioned lower portion; an organic layer, which is in contact with the above-mentioned lower electrode through the above-mentioned pixel opening and emits light in response to the application of a voltage; an upper electrode, which covers the above-mentioned organic layer and is in contact with at least one of the above-mentioned bottom portion and the above-mentioned lower portion; and a transparent conductive oxide layer, which is arranged between the above-mentioned lower electrode and the above-mentioned rib portion and has an opening overlapping with the above-mentioned pixel opening.

[0007] According to one embodiment, a method for manufacturing a display device includes: forming a lower electrode, forming a rib having a pixel opening overlapping the lower electrode, forming a transparent conductive oxide layer covering the lower electrode and the rib, forming a partition wall on the conductive oxide layer, the partition wall including a bottom located above the rib, a lower portion arranged on the bottom, and an upper portion arranged on the lower portion and protruding from a side surface of the lower portion, after forming the partition wall, removing a portion of the conductive oxide layer exposed from the bottom, forming an organic layer that contacts the lower electrode through the pixel opening and emits light in response to the application of a voltage, and forming an upper electrode that covers the organic layer and contacts at least one of the bottom and the lower portion.

[0008] According to another embodiment, a method for manufacturing a display device includes: forming a lower electrode; forming a transparent conductive oxide layer covering the above-mentioned lower electrode; forming a rib covering the above-mentioned conductive oxide layer and having a pixel opening overlapping with the above-mentioned lower electrode; forming a partition wall, the partition wall including a bottom located above the above-mentioned rib, a lower portion arranged on the above-mentioned bottom, and an upper portion arranged on the above-mentioned lower portion and protruding from the side of the above-mentioned lower portion; after forming the above-mentioned partition wall, removing a portion of the above-mentioned conductive oxide layer exposed from the above-mentioned rib through the above-mentioned pixel opening, forming an organic layer that contacts the above-mentioned lower electrode through the above-mentioned pixel opening and emits light in response to the application of a voltage; forming an upper electrode covering the above-mentioned organic layer and contacting at least one of the above-mentioned bottom and the above-mentioned lower portion.

[0009] According to each embodiment, the yield of the display device can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 It is a diagram showing a configuration example of a display device according to the first embodiment.

[0011] Figure 2 It is a schematic plan view showing an example of the layout of sub-pixels.

[0012] Figure 3 It is along Figure 2 Schematic cross-sectional view of the display device taken along line III-III.

[0013] Figure 4 This is a diagram showing an example of a layer structure that can be applied to an organic layer.

[0014] Figure 5 This is a schematic cross-sectional view showing an enlarged view of the partition wall and its vicinity according to the first embodiment.

[0015] Figure 6 This is a schematic cross-sectional view showing an enlarged view of the bottom portion and the vicinity of the end portion of the conductive oxide layer in the first embodiment.

[0016] Fig. 7A It is a schematic cross-sectional view showing the manufacturing process of the display device according to the first embodiment.

[0017] Figure 7B It means next Fig. 7A A schematic cross-sectional view of the manufacturing process.

[0018] Figure 7C It means next Figure 7B A schematic cross-sectional view of the manufacturing process.

[0019] Fig.7D It means next Figure 7C A schematic cross-sectional view of the manufacturing process.

[0020] Fig. 7E It means next Fig.7D A schematic cross-sectional view of the manufacturing process.

[0021] Figure 7F It means next Fig. 7E A schematic cross-sectional view of the manufacturing process.

[0022] Figure 7G It means next Figure 7F A schematic cross-sectional view of the manufacturing process.

[0023] Figure 7H It means next Figure 7G A schematic cross-sectional view of the manufacturing process.

[0024] Fig.7I It means next Figure 7H A schematic cross-sectional view of the manufacturing process.

[0025] Figure 7J It means next Fig.7I A schematic cross-sectional view of the manufacturing process.

[0026] Figure 7K It means next Figure 7J A schematic cross-sectional view of the manufacturing process.

[0027] Figure 7L It means next Figure 7K A schematic cross-sectional view of the manufacturing process.

[0028] Figure 7M It means next Figure 7L A schematic cross-sectional view of the manufacturing process.

[0029] Fig. 8A It is a schematic cross-sectional view showing a manufacturing process for forming a display element.

[0030] Figure 8B It means next Fig. 8A A schematic cross-sectional view of the manufacturing process.

[0031] Figure 8C It means next Figure 8B A schematic cross-sectional view of the manufacturing process.

[0032] Fig.8D It means next Figure 8C A schematic cross-sectional view of the manufacturing process.

[0033] Fig. 9 This is a schematic cross-sectional view of a display device according to a second embodiment.

[0034] Fig.10 It is a schematic plan view of the rib, the lower electrode, and the conductive layer according to the second embodiment.

[0035] Fig.11 Yes Fig. 9 The partition wall and its vicinity are shown in an enlarged schematic cross-sectional view.

[0036] Fig. 12A It is a schematic cross-sectional view showing a manufacturing process of the display device according to the second embodiment.

[0037] Fig. 12B It means next Fig. 12A A schematic cross-sectional view of the manufacturing process.

[0038] Fig. 12C It means next Fig. 12B A schematic cross-sectional view of the manufacturing process.

[0039] Fig.12D It means next Fig. 12C A schematic cross-sectional view of the manufacturing process.

[0040] Fig.12E It means next Fig.12D A schematic cross-sectional view of the manufacturing process.

[0041] Fig.12F It means next Fig.12E A schematic cross-sectional view of the manufacturing process.

[0042] Figure 12G It means next Fig.12F A schematic cross-sectional view of the manufacturing process.

[0043] Fig.12H It means next Figure 12G A schematic cross-sectional view of the manufacturing process.

[0044] Fig.12IIt means next Fig.12H A schematic cross-sectional view of the manufacturing process.

[0045] Fig.12J It means next Fig.12I A schematic cross-sectional view of the manufacturing process.

[0046] Figure 12K It means next Fig.12J A schematic cross-sectional view of the manufacturing process.

[0047] Figure 12L It means next Figure 12K A schematic cross-sectional view of the manufacturing process.

[0048] Figure 12M It means next Figure 12L A schematic cross-sectional view of the manufacturing process. DETAILED DESCRIPTION

[0049] Several embodiments will be described with reference to the drawings.

[0050] The disclosed content is only an example, and appropriate changes that can be easily thought of by those skilled in the art while maintaining the main idea of ​​the invention are of course included in the scope of the present invention. In addition, with respect to the drawings, in order to make the description clearer, the width, thickness, shape, etc. of each part are sometimes schematically shown compared with the actual method, but this is only an example and does not limit the interpretation of the present invention. In addition, in this specification and each figure, the same reference numerals are marked for the constituent elements that have the same or similar functions as the constituent elements described in the drawings that have appeared, and sometimes repeated detailed descriptions are appropriately omitted.

[0051] It should be noted that, for ease of understanding, mutually orthogonal X-axis, Y-axis and Z-axis are recorded in the drawings as needed. The direction along the X-axis is called the X-direction, the direction along the Y-axis is called the Y-direction, and the direction along the Z-axis is called the Z-direction. The Z-direction is the normal direction of the plane including the X-direction and the Y-direction. In addition, the situation of observing various elements parallel to the Z-direction is called top-down observation.

[0052] The display device of each embodiment is an organic electroluminescent display device having an organic light emitting diode (OLED) as a display element, and can be mounted on various electronic devices such as televisions, personal computers, vehicle-mounted equipment, tablet terminals, smartphones, mobile phone terminals, and wearable terminals.

[0053] [First embodiment]

[0054] Figure 11 is a diagram showing a configuration example of a display device DSP according to the first embodiment. The display device DSP includes an insulating substrate 10. The substrate 10 includes a display area DA for displaying an image and a peripheral area SA surrounding the display area DA. The substrate 10 may be glass or a flexible resin film.

[0055] In the present embodiment, the shape of the substrate 10 in a plan view is a rectangle, however, the shape of the substrate 10 in a plan view is not limited to a rectangle, and may be other shapes such as a square, a circle, or an ellipse.

[0056] The display area DA includes a plurality of pixels PX arranged in a matrix in the X direction and the Y direction. The pixel PX includes a plurality of sub-pixels SP that display different colors. In the present embodiment, it is assumed that the pixel PX includes a blue sub-pixel SP1, a green sub-pixel SP2, and a red sub-pixel SP3. However, the pixel PX may also include a sub-pixel SP of another color such as white together with the sub-pixels SP1, SP2, and SP3 or instead of any of the sub-pixels SP1, SP2, and SP3.

[0057] The sub-pixel SP includes a pixel circuit 1 and a display element DE driven by the pixel circuit 1. The pixel circuit 1 includes a pixel switch 2, a driving transistor 3, and a capacitor 4. The pixel switch 2 and the driving transistor 3 are switching elements composed of, for example, thin film transistors.

[0058] In the display area DA, a plurality of scanning lines GL for supplying scanning signals to the pixel circuits 1 of the sub-pixels SP, a plurality of signal lines SL for supplying video signals to the pixel circuits 1 of the sub-pixels SP, and a plurality of power supply lines PL are arranged. Figure 1 In the example of FIG. 5 , the scanning lines GL and the power lines PL extend in the X direction, and the signal lines SL extend in the Y direction.

[0059] The gate electrode of the pixel switch 2 is connected to the scanning line GL. One of the source electrode and the drain electrode of the pixel switch 2 is connected to the signal line SL, and the other is connected to the gate electrode of the driving transistor 3 and the capacitor 4. In the driving transistor 3, one of the source electrode and the drain electrode is connected to the power line PL and the capacitor 4, and the other is connected to the display element DE.

[0060] It should be noted that the configuration of the pixel circuit 1 is not limited to the illustrated example. For example, the pixel circuit 1 may include more thin film transistors and capacitors.

[0061] Figure 2 1 is a schematic top view showing an example of the layout of sub-pixels SP1, SP2, and SP3. Figure 2In the example of FIG. 1 , the sub-pixels SP2 and SP3 are arranged in the X direction with the sub-pixel SP1. In addition, the sub-pixel SP2 and the sub-pixel SP3 are arranged in the Y direction.

[0062] When the sub-pixels SP1, SP2, and SP3 are arranged in this manner, columns in which the sub-pixels SP2 and SP3 are alternately arranged in the Y direction and columns in which a plurality of sub-pixels SP1 are repeatedly arranged in the Y direction are formed in the display area DA. These columns are alternately arranged in the X direction. It should be noted that the layout of the sub-pixels SP1, SP2, and SP3 is not limited to Figure 2 Example.

[0063] The rib 5 is disposed in the display area DA. The rib 5 has pixel openings AP1, AP2, and AP3 in the sub-pixels SP1, SP2, and SP3, respectively. Figure 2 In the example, the pixel opening AP1 is larger than the pixel opening AP2, and the pixel opening AP2 is larger than the pixel opening AP3. That is, among the sub-pixels SP1, SP2, and SP3, the sub-pixel SP1 has the largest aperture ratio, and the sub-pixel SP3 has the smallest aperture ratio.

[0064] The sub-pixel SP1 includes a lower electrode LE1, an upper electrode UE1, and an organic layer OR1 respectively overlapping with the pixel opening AP1. The sub-pixel SP2 includes a lower electrode LE2, an upper electrode UE2, and an organic layer OR2 respectively overlapping with the pixel opening AP2. The sub-pixel SP3 includes a lower electrode LE3, an upper electrode UE3, and an organic layer OR3 respectively overlapping with the pixel opening AP3.

[0065] The lower electrode LE1, the upper electrode UE1, and the portion of the organic layer OR1 that overlaps with the pixel opening AP1 constitute the display element DE1 of the sub-pixel SP1. The lower electrode LE2, the upper electrode UE2, and the portion of the organic layer OR2 that overlaps with the pixel opening AP2 constitute the display element DE2 of the sub-pixel SP2. The lower electrode LE3, the upper electrode UE3, and the portion of the organic layer OR3 that overlaps with the pixel opening AP3 constitute the display element DE3 of the sub-pixel SP3. The display elements DE1, DE2, and DE3 may further include a cover layer described later. The ribs 5 surround these display elements DE1, DE2, and DE3, respectively.

[0066] A conductive partition wall 6 is disposed on the rib 5. The partition wall 6 overlaps the rib 5 as a whole and has the same planar shape as the rib 5. That is, the partition wall 6 has openings in the sub-pixels SP1, SP2, and SP3, respectively. From another point of view, the rib 5 and the partition wall 6 are lattice-shaped when viewed from above, and surround the sub-pixels SP1, SP2, and SP3, respectively. The partition wall 6 has a function as a wiring for supplying a common voltage to the upper electrodes UE1, UE2, and UE3.

[0067] Figure 3It is along Figure 2 A schematic cross-sectional view of the display device DSP along line III-III in FIG. A circuit layer 11 is arranged on the substrate 10. The circuit layer 11 includes Figure 1 The circuit layer 11 is covered with an organic insulating layer 12. The organic insulating layer 12 functions as a planarizing film that planarizes the unevenness generated in the circuit layer 11.

[0068] The lower electrodes LE1, LE2, and LE3 are arranged on the organic insulating layer 12. The ribs 5 are arranged on the organic insulating layer 12 and the lower electrodes LE1, LE2, and LE3. The ends of the lower electrodes LE1, LE2, and LE3 are covered by the ribs 5. Figure 3 Although not shown in the cross section of FIG. 1 , the lower electrodes LE1 , LE2 , and LE3 are connected to the pixel circuit 1 of the circuit layer 11 through contact holes provided in the organic insulating layer 12 .

[0069] The partition wall 6 includes a conductive bottom portion 60 disposed above the rib portion 5, a conductive lower portion 61 disposed above the bottom portion 60, and an upper portion 62 disposed above the lower portion 61. The upper portion 62 has a greater width than the lower portion 61. Thus, both ends of the upper portion 62 protrude from the side surfaces of the lower portion 61. Such a shape of the partition wall 6 is called a cantilever shape. Figure 3 In the example of FIG. 6 , both end portions of the bottom portion 60 also protrude from the side surfaces of the lower portion 61 .

[0070] The organic layer OR1 covers the lower electrode LE1 through the pixel opening AP1. The upper electrode UE1 covers the organic layer OR1 and is opposite to the lower electrode LE1. The organic layer OR2 covers the lower electrode LE2 through the pixel opening AP2. The upper electrode UE2 covers the organic layer OR2 and is opposite to the lower electrode LE2. The organic layer OR3 covers the lower electrode LE3 through the pixel opening AP3. The upper electrode UE3 covers the organic layer OR3 and is opposite to the lower electrode LE3. The upper electrodes UE1, UE2, and UE3 are in contact with at least one of the bottom 60 and the lower portion 61 of the partition wall 6.

[0071] The display element DE1 includes a cap layer CP1 disposed on the upper electrode UE1. The display element DE2 includes a cap layer CP2 disposed on the upper electrode UE2. The display element DE3 includes a cap layer CP3 disposed on the upper electrode UE3. The cap layers CP1, CP2, and CP3 respectively function as optical adjustment layers for improving the extraction efficiency of light emitted from the organic layers OR1, OR2, and OR3.

[0072] In the following description, the multilayer body including the organic layer OR1, the upper electrode UE1 and the cover layer CP1 is referred to as the stacked film FL1, the multilayer body including the organic layer OR2, the upper electrode UE2 and the cover layer CP2 is referred to as the stacked film FL2, and the multilayer body including the organic layer OR3, the upper electrode UE3 and the cover layer CP3 is referred to as the stacked film FL3.

[0073] A portion of the laminate film FL1 is located above the upper portion 62. This portion is separated from the portion of the laminate film FL1 located around the partition wall 6 (the portion constituting the display element DE1). Similarly, a portion of the laminate film FL2 is located above the upper portion 62, and this portion is separated from the portion of the laminate film FL2 located around the partition wall 6 (the portion constituting the display element DE2). In addition, a portion of the laminate film FL3 is located above the upper portion 62, and this portion is separated from the portion of the laminate film FL3 located around the partition wall 6 (the portion constituting the display element DE3).

[0074] Seal layers SE11, SE12, and SE13 are respectively arranged in sub-pixels SP1, SP2, and SP3. Seal layer SE11 continuously covers cap layer CP1 and partition walls 6 around sub-pixel SP1. Seal layer SE12 continuously covers cap layer CP2 and partition walls 6 around sub-pixel SP2. Seal layer SE13 continuously covers cap layer CP3 and partition walls 6 around sub-pixel SP3.

[0075] exist Figure 3 In the example, the laminated film FL1 and the sealing layer SE11 on the partition wall 6 between the sub-pixels SP1 and SP2 are separated from the laminated film FL2 and the sealing layer SE12 on the partition wall 6. In addition, the laminated film FL1 and the sealing layer SE11 on the partition wall 6 between the sub-pixels SP1 and SP3 are separated from the laminated film FL3 and the sealing layer SE13 on the partition wall 6.

[0076] The sealing layers SE11, SE12, and SE13 are covered by the resin layer RS1. The resin layer RS1 is covered by the sealing layer SE2. The sealing layer SE2 is covered by the resin layer RS2. The resin layers RS1, RS2, and the sealing layer SE2 are continuously provided at least in the entire display area DA, and a part of them also reaches the peripheral area SA.

[0077] A cover member such as a polarizing plate, a touch panel, a protective film or a cover glass may be further disposed on the resin layer RS2. Such a cover member may be bonded to the resin layer RS2 via an adhesive layer such as OCA (Optical Clear Adhesive).

[0078] The organic insulating layer 12 is formed of an organic insulating material such as polyimide. The rib 5 and the sealing layers SE11, SE12, SE13, SE2 are formed of inorganic insulating materials such as silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON) or aluminum oxide (Al2O3). The resin layers RS1 and RS2 are formed of resin materials (organic insulating materials) such as epoxy resin and acrylic resin.

[0079] The lower electrodes LE1, LE2, LE3 include a reflective layer formed of a metal material, which will be described in detail later. The upper electrodes UE1, UE2, UE3 are formed of a metal material such as an alloy of magnesium and silver (MgAg). For example, the lower electrodes LE1, LE2, LE3 are equivalent to anodes, and the upper electrodes UE1, UE2, UE3 are equivalent to cathodes.

[0080] Figure 4 : is a diagram showing an example of a layer structure that can be applied to the organic layers OR1, OR2, and OR3. The organic layers OR1, OR2, and OR3 are composed of a plurality of thin films including a light-emitting layer EML. In the present embodiment, it is assumed that the organic layers OR1, OR2, and OR3 have a structure in which a hole injection layer HIL, a hole transport layer HTL, an electron blocking layer EBL, a light-emitting layer EML, a hole blocking layer HBL, an electron transport layer ETL, and an electron injection layer EIL are sequentially stacked in the Z direction. However, the organic layers OR1, OR2, and OR3 may have other structures such as a so-called series structure including a plurality of light-emitting layers EML.

[0081] The cover layers CP1, CP2, and CP3, for example, have a stacked structure formed by overlapping multiple transparent layers. These transparent layers may include layers formed by inorganic materials and layers formed by organic materials. In addition, these transparent layers have different refractive indices from each other. For example, the refractive indices of these transparent layers are different from the refractive indices of the upper electrodes UE1, UE2, and UE3 and the refractive indices of the sealing layers SE1, SE2, and SE3. It should be noted that at least one of the cover layers CP1, CP2, and CP3 may also be omitted.

[0082] A common voltage is supplied to the partition wall 6. The common voltage is supplied to the upper electrodes UE1, UE2, UE3 respectively in contact with at least one of the bottom portion 60 and the lower portion 61. Pixel voltages corresponding to the image signals of the signal lines SL are supplied to the lower electrodes LE1, LE2, LE3 respectively through the pixel circuits 1 of the sub-pixels SP1, SP2, SP3.

[0083] The organic layers OR1, OR2, and OR3 emit light in response to the application of voltage. Specifically, if a potential difference is formed between the lower electrode LE1 and the upper electrode UE1, the light-emitting layer EML of the organic layer OR1 emits light in a blue wavelength region. If a potential difference is formed between the lower electrode LE2 and the upper electrode UE2, the light-emitting layer EML of the organic layer OR2 emits light in a green wavelength region. If a potential difference is formed between the lower electrode LE3 and the upper electrode UE3, the light-emitting layer EML of the organic layer OR3 emits light in a red wavelength region.

[0084] As another example, the light-emitting layers EML of the organic layers OR1, OR2, and OR3 may emit light of the same color (e.g., white). In this case, the display device DSP may include a color filter that converts the light emitted by the light-emitting layer EML into light of a color corresponding to the sub-pixels SP1, SP2, and SP3. In addition, the display device DSP may also include a layer including quantum dots that are excited by the light emitted by the light-emitting layer EML to generate light of a color corresponding to the sub-pixels SP1, SP2, and SP3.

[0085] Figure 5 This is a schematic cross-sectional view showing the partition wall 6 and its vicinity in an enlarged manner. In this figure, the substrate 10, the circuit layer 11, the resin layers RS1 and RS2, and the sealing layer SE2 are omitted.

[0086] exist Figure 5 In the example, the lower electrode LE1 includes a reflective layer RL, a first cover layer V1 covering the lower surface of the reflective layer RL, and a second cover layer V2 covering the upper surface of the reflective layer RL. The organic layer OR1 is in contact with the second cover layer V2 at the pixel opening AP1.

[0087] The reflective layer RL is formed of, for example, a metal material having excellent light reflectivity, such as silver. The coating layers V1 and V2 are formed of, for example, transparent conductive oxides such as ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), or IGZO (Indium Gallium Zinc Oxide). The structure of the lower electrodes LE2 and LE3 is the same as that of the lower electrode LE1. For example, the ends of the lower electrodes LE1, LE2, and LE3 overlap with the lower portion 61 in the Z direction.

[0088] exist Figure 5 In the example of , the upper portion 62 of the partition wall 6 includes a first top layer 63 disposed on the lower portion 61 and a second top layer 64 covering the first top layer 63. Both ends of the first top layer 63 and the second top layer 64 protrude from the side surface of the lower portion 61. Parts of both ends of the first top layer 63 are exposed from the second top layer 64.

[0089] The bottom 60 is formed of a conductive metal material. Examples of the metal material include titanium (Ti), titanium nitride (TiN), molybdenum (Mo), molybdenum-tungsten alloy (MoW), and molybdenum-niobium alloy (MoNb). The thickness of the bottom 60 is, for example, 10 to 50 nm.

[0090] The lower portion 61 is formed of, for example, a conductive metal material different from that of the bottom portion 60. As the metal material, for example, aluminum (Al), aluminum-neodymium alloy (AlNd), aluminum-yttrium alloy (AlY) or aluminum-silicon alloy (AlSi) can be used. The thickness of the lower portion 61 is, for example, 400 to 1000 nm. It should be noted that the lower portion 61 can also be formed of an insulating material.

[0091] The first top layer 63 is formed of, for example, a metal material. The second top layer 64 is formed of, for example, a transparent conductive oxide. As the metal material forming the first top layer 63, for example, titanium, titanium nitride, molybdenum, tungsten, a molybdenum-tungsten alloy, or a molybdenum-niobium alloy can be used. As the conductive oxide forming the second top layer 64, for example, ITO, IZO, or IGZO can be used. The thickness of the first top layer 63 is, for example, 50 to 300 nm. The thickness of the second top layer 64 is, for example, 20 to 100 nm.

[0092] It should be noted that the bottom portion 60 and the lower portion 61 may also include multiple layers formed of different materials. In addition, the upper portion 62 may be formed of a single layer. The lower portion 61 and the upper portion 62 may include layers formed of insulating materials.

[0093] In the present embodiment, a transparent conductive oxide layer CL is disposed between the rib 5 and the bottom 60. The conductive oxide layer CL can be formed of, for example, amorphous ITO, IZO, or IGZO.

[0094] Note that the conductive oxide (ITO, IZO or IGZO) forming the covering layers V1 and V2 of the lower electrodes LE1, LE2 and LE3 is fired in a manufacturing process described later. Therefore, the covering layers V1 and V2 have higher crystallinity than the conductive oxide layer CL.

[0095] Figure 6 2 is a schematic cross-sectional view showing the bottom 60 and the vicinity of the end of the conductive oxide layer CL in an enlarged manner. Figure 6 In the example of , the end E1 of the bottom 60 protrudes more than the end E2 of the conductive oxide layer CL. Thus, a gap is formed below the end E1. The protrusion length of the end E1 from the end E2 is, for example, 50 nm to 1000 nm. Figure 6 In the example of FIG. 5 , the end portion of the conductive oxide layer CL does not overlap with the lower portion 61 in the Z direction.

[0096] exist Figure 6In the example of , a portion of the organic layer OR1 is also located above the bottom portion 60. The organic layer OR1 is separated from the lower portion 61. The hole injection layer HIL of the organic layer OR1 is cut off at the end portion E1. On the other hand, the hole transport layer HTL is not cut off at the end portion E1. The layers formed above the hole transport layer HTL in the organic layer OR1 (e.g., the electron blocking layer EBL, the light emitting layer EML, the hole blocking layer HBL, the electron transport layer ETL, and the electron injection layer EIL) are also not cut off at the end portion E1. The upper electrode UE1 continuously covers the organic layer OR1 and is in contact with the bottom portion 60 and the lower portion 61.

[0097] If the hole injection layer HIL is conductive with the partition wall 6, leakage current will occur through the hole injection layer HIL, and the display quality may be reduced. Therefore, the hole injection layer HIL is preferably formed in a region that does not overlap with the bottom 60, or as shown in FIG. Figure 6 For example, when the thickness T1 of the conductive oxide layer CL is greater than the thickness T2 of the hole injection layer HIL (T2<T1), the hole injection layer HIL is easily cut at the end E1.

[0098] If the thickness T1 is too large, other layers of the organic layer OR1 and the upper electrode UE1 may also be cut off. When the upper electrode UE1 is cut off, the voltage supply from the partition wall 6 to the upper electrode UE1 is hindered, and the organic layer OR1 may not emit light. Therefore, the thickness T1 is preferably smaller than the total thickness T3 of the hole injection layer HIL and the hole transport layer HTL (T1<T3). As a result, the hole transport layer HTL is not easily cut off at the end E1. As a result, the cut-off of the layers in the organic layer OR1 that are located above the hole transport layer HTL and the upper electrode UE1 can be suppressed.

[0099] As an example, the thickness T1 is 15 to 50 nm. Figure 6 In the embodiment, the conductive oxide layer CL is thinner than the bottom portion 60, but the present invention is not limited to this example.

[0100] The region below the end E1 is filled with the hole transport layer HTL, for example. However, a gap may be formed in at least a portion of this region. Figure 6 In the example of FIG. 5 , the end E2 of the conductive oxide layer CL overlaps with the hole injection layer HIL located on the bottom portion 60 in the Z direction. In addition, the end E2 overlaps with the upper electrode UE1 in the Z direction.

[0101] It should be noted that in Figure 6In the figure, the structure near the end of the stacked film FL1 is focused on, but the stacked films FL2 and FL3 also have the same structure near the end. For example, the thickness of the hole injection layer HIL and the hole transport layer HTL of the organic layers OR2 and OR3 is the same as the thickness of the hole injection layer HIL and the hole transport layer HTL of the organic layer OR1. That is, the hole injection layer HIL of the organic layers OR2 and OR3 is also cut off at the end E1.

[0102] Next, an example of a method for manufacturing the display device DSP according to the present embodiment will be described.

[0103] FIG. 7A to FIG. 7M It is a schematic cross-sectional view showing a manufacturing process before forming display elements DE1, DE2, and DE3. FIG. 8A to FIG. 8D These are schematic cross-sectional views showing the steps of forming the display elements DE1, DE2, and DE3. In these drawings, the substrate 10 and the circuit layer 11 are omitted.

[0104] In order to manufacture the display device DSP, firstly, a circuit layer 11 and an organic insulating layer 12 are formed on a substrate 10. Then, Fig. 7A As shown, a first covering layer V1a formed of a transparent conductive oxide, a reflective layer RLa formed of a metal material, and a second covering layer V2a formed of a transparent conductive oxide are sequentially formed on the organic insulating layer 12. In addition, a resist R1 having a shape corresponding to the lower electrodes LE1, LE2, and LE3 is disposed on the second covering layer V2a.

[0105] The reflective layer RLa, the first covering layer V1a and the second covering layer V2a are layers for processing into the reflective layer RL, the first covering layer V1 and the second covering layer V2. These layers are formed in the entire display area DA and the peripheral area SA by sputtering, for example.

[0106] Next, the reflective layer RLa and the covering layers V1a and V2a are patterned into the shape of the resist R1. Specifically, the portions of the reflective layer RLa and the covering layers V1a and V2a exposed from the resist R1 are removed by wet etching. Figure 7B As shown, lower electrodes LE1, LE2, and LE3 including a reflective layer RL, a first cover layer V1 covering the lower surface of the reflective layer RL, and a second cover layer V2 covering the upper surface of the reflective layer RL are formed.

[0107] After forming the lower electrodes LE1, LE2, LE3, as Figure 7C As shown, the resist R1 is removed. Furthermore, the entire substrate is heated, thereby sintering the conductive oxide constituting the covering layers V1 and V2.

[0108] Next, if Fig.7DAs shown, the rib layer 5a covering the lower electrodes LE1, LE2, and LE3 is formed by CVD (Chemical Vapor Deposition). In addition, a resist R2 having a shape corresponding to the rib 5 is arranged on the rib layer 5a. The rib layer 5a is an inorganic insulating layer used to be processed into the rib 5, and is formed in the entire display area DA and the peripheral area SA.

[0109] Next, the portion of the rib layer 5a exposed from the resist R2 is removed by dry etching. Fig. 7E As shown in FIG. 1 , a rib 5 having pixel openings AP1, AP2, and AP3 overlapping the lower electrodes LE1, LE2, and LE3 is formed. After the rib 5 is formed, as shown in FIG. Figure 7F As shown, the resist R2 is removed.

[0110] It should be noted that, during the dry etching of the rib layer 5 a , part of the resist R2 is also corroded, and its width gradually decreases, thereby making the end portions of the rib 5 along the pixel openings AP1 , AP2 , and AP3 tapered.

[0111] After forming the rib 5, as Figure 7G As shown, a conductive oxide layer CLa, a bottom layer 60a, a lower layer 61a, a first top layer 63a and a second top layer 64a are sequentially formed by sputtering. In addition, a resist R3 having a shape corresponding to the partition wall 6 is disposed on the second top layer 64a. The conductive oxide layer CLa, the bottom layer 60a, the lower layer 61a, the first top layer 63a and the second top layer 64a are layers for processing into the above-mentioned conductive oxide layer CL, the bottom 60, the lower part 61 and the upper part 62 (the first top layer 63 and the second top layer 64), respectively, and are formed in the entire display area DA and the peripheral area SA. The conductive oxide layer CLa covers the lower electrodes LE1, LE2, LE3 and the ribs 5.

[0112] The conductive oxide layer CLa is formed of an amorphous conductive oxide. In order to form such an amorphous conductive oxide layer CLa, it is preferred to sufficiently increase the partial pressure of water vapor in the chamber during the sputtering of the conductive oxide layer CLa. In one example, the partial pressure of water vapor during sputtering when forming the conductive oxide layer CLa is higher than the partial pressure of water vapor during sputtering when forming the coating layers V1 and V2 of the lower electrodes LE1, LE2, and LE3.

[0113] Next, the portion of the second top layer 64a exposed from the resist R3 is removed by wet etching. Figure 7H As shown, a second top layer 64 is formed. Figure 7H In the example of , the width of the second top layer 64 is slightly smaller than that of the resist R3.

[0114] Furthermore, dry etching is performed using the resist R3 as a mask to remove the portion of the first top layer 63a exposed from the resist R3. Fig.7I As shown, a first top layer 63 is formed.

[0115] It should be noted that, in this dry etching, the thickness of the portion of the lower layer 61a exposed from the resist R3 is also reduced. In addition, by this dry etching, a portion of the resist R3 is eroded and its width is reduced.

[0116] Next, the lower layer 61a is wet-etched. As a result, the portion of the lower layer 61a exposed from the resist R3 is removed. In addition, the side surface of the lower layer 61a is eroded, and its width is reduced compared to the top layers 63 and 64. As a result, Figure 7J As shown, a lower portion 61 is formed.

[0117] After the lower portion 61 is formed, the bottom layer 60a is patterned by dry etching. Specifically, the portion of the bottom layer 60a exposed from the resist R3 is removed by dry etching. Figure 7K As shown, a bottom portion 60 is formed. In this dry etching, the width of the bottom portion 60 is reduced to a range below the width of the top portions 63 and 64 and above the width of the lower portion 61 .

[0118] Through the above steps, the partition wall 6 including the bottom 60, the lower part 61 and the upper part 62 (the first top layer 63 and the second top layer 64) is completed. After the partition wall 6 is formed, the conductive oxide layer CLa is patterned by wet etching. Specifically, the portion of the conductive oxide layer CLa exposed from the bottom 60 is removed by the wet etching. Figure 7L As shown in FIG. 1 , a conductive oxide layer CL is formed. In this wet etching, as shown in FIG. Figure 6 As shown, the end E2 of the conductive oxide layer CL is set back from the end E1 of the bottom 60 .

[0119] Since the conductive oxide layer CLa has not been fired before the wet etching, it is amorphous. As an etching solution for such a conductive oxide layer CLa, oxalic acid can be used, for example. It should be noted that the second coating layer V2 of the lower electrodes LE1, LE2, and LE3 is fired at the time of the wet etching and has a higher crystallinity than the conductive oxide layer CLa. Therefore, the etching speed of oxalic acid on the second coating layer V2 is sufficiently slow compared to the conductive oxide layer CLa, and it is not easily corroded. In addition, if wet etching using oxalic acid is used, the ribs 5 formed of silicon nitride, silicon oxide or silicon oxynitride are also not easily corroded.

[0120] During the wet etching of the conductive oxide layer CLa, the second top layer 64 formed of the conductive oxide may also be corroded. Figure 7LAs shown in FIG. 1 , the width of the second top layer 64 is smaller than the width of the first top layer 63. After the conductive oxide layer CL is formed, Figure 7M As shown, the resist R3 is removed.

[0121] Next, a process for forming display elements DE1, DE2, and DE3 is performed. In this embodiment, display element DE1 is formed first, then display element DE2 is formed, and finally display element DE3 is formed. However, the order of forming display elements DE1, DE2, and DE3 is not limited to this example.

[0122] When forming the display element DE1, first, as Fig. 8A As shown in FIG. 1 , a laminated film FL1 and a sealing layer SE11 are formed. Figure 3 As shown, the stacked film FL1 includes an organic layer OR1 contacting the lower electrode LE1 through the pixel opening AP1 , an upper electrode UE1 covering the organic layer OR1 , and a cap layer CP1 covering the upper electrode UE1 .

[0123] The organic layer OR1, the upper electrode UE1 and the cap layer CP1 are formed by evaporation. In addition, the sealing layer SE11 is formed by CVD. The laminate film FL1 is partitioned into a plurality of parts by the cantilevered partition wall 6. The sealing layer SE11 continuously covers the partitioned parts of the laminate film FL1 and the partition wall 6.

[0124] After forming the stacked film FL1 and the sealing layer SE11, as shown in FIG. Fig. 8A As shown in FIG. 1 , a resist R4 is disposed on the sealing layer SE11 . The resist R4 covers the sub-pixel SP1 and a part of the partition wall 6 around it.

[0125] Then, if Figure 8B As shown, the portions of the laminated film FL1 and the sealing layer SE11 exposed from the resist R4 are removed by etching using the resist R4 as a mask. Thus, the display element DE1 is formed in the sub-pixel SP1. For example, the etching includes wet etching and dry etching sequentially performed on the sealing layer SE11, the cap layer CP1, the upper electrode UE1, and the organic layer OR1. After these etchings, the resist R4 is removed.

[0126] The display element DE2 is formed in the same steps as the display element DE1. That is, when forming the display element DE2, the stacked film FL2 and the sealing layer SE12 are formed in the entire display area DA. Figure 3 As shown, the stacked film FL2 includes an organic layer OR2 contacting the lower electrode LE2 through the pixel opening AP2, an upper electrode UE2 covering the organic layer OR2, and a cover layer CP2 covering the upper electrode UE2.

[0127] The organic layer OR2, the upper electrode UE2 and the cap layer CP2 are formed by evaporation. In addition, the sealing layer SE12 is formed by CVD. The laminate film FL2 is partitioned into a plurality of parts by the cantilever partition wall 6. The sealing layer SE12 continuously covers the partitioned parts of the laminate film FL2 and the partition wall 6.

[0128] Next, the laminate film FL2 and the sealing layer SE12 are patterned. Figure 8C As shown, a display element DE2 is formed in the sub-pixel SP2.

[0129] The display element DE3 is formed in the same steps as the display elements DE1 and DE2. That is, when forming the display element DE3, the stacked film FL3 and the sealing layer SE13 are formed in the entire display area DA. Figure 3 As shown, the stacked film FL3 includes an organic layer OR3 in contact with the lower electrode LE3 through the pixel opening AP3, an upper electrode UE3 covering the organic layer OR3, and a cap layer CP3 covering the upper electrode UE3.

[0130] The organic layer OR3, the upper electrode UE3 and the cap layer CP3 are formed by evaporation. In addition, the sealing layer SE13 is formed by CVD. The laminate film FL3 is partitioned into a plurality of parts by the cantilever partition wall 6. The sealing layer SE13 continuously covers the partitioned parts of the laminate film FL3 and the partition wall 6.

[0131] Next, the laminate film FL3 and the sealing layer SE13 are patterned. Fig.8D As shown, a display element DE3 is formed in the sub-pixel SP3.

[0132] After forming display elements DE1, DE2, and DE3, Figure 3 The resin layer RS1, the sealing layer SE2 and the resin layer RS2 are shown. After such steps, the display device DSP is completed.

[0133] In the present embodiment described above, it is possible to obtain the display device DSP including the display elements DE1 , DE2 , DE3 which are separated by the cantilever-shaped partition wall 6 for each sub-pixel SP1 , SP2 , SP3 and are individually sealed.

[0134] In addition, by configuring the conductive oxide layer CL below the partition 6, the yield of the display device DSP can be improved. That is, if the conductive oxide layer CL is not provided, the lower electrodes LE1, LE2, LE3, and the rib 5 may be damaged in the etching for forming the partition 6. In contrast, when the conductive oxide layer CL is provided, the conductive oxide layer CL functions as an etching stop layer for etching for forming the partition 6. Therefore, damage to the lower electrodes LE1, LE2, LE3, and the rib 5 is suppressed.

[0135] It should be noted that even in the case where the conductive oxide layer CL is not provided, by forming the rib 5 from a material having a slow dry etching rate such as silicon oxide or silicon oxynitride, damage to the rib 5 can be suppressed. However, silicon oxide and silicon oxynitride have poorer coverage than silicon nitride. Therefore, it is possible that, for example, a moisture path is generated in the rib 5 near the end of the lower electrode LE1, LE2, and LE3, and other undesirable conditions may occur. In contrast, in the case where the conductive oxide layer CL is provided, for example, silicon nitride having a fast dry etching rate but excellent coverage can be used as the material of the rib 5, and damage to the rib 5 can be suppressed.

[0136] The second coating layer V2 of the lower electrodes LE1, LE2, and LE3 protects the reflective layer RL from the etching for forming the partition wall 6. The thicker the second coating layer V2 is, the more this effect is improved. However, if the second coating layer V2 is thickened, the brightness and luminous efficiency of the display elements DE1, DE2, and DE3 may be reduced. In contrast, if the conductive oxide layer CL is provided on the second coating layer V2 as in the present embodiment, the second coating layer V2 can be formed thinner than in the case where there is no conductive oxide layer CL. As a result, it is expected that the brightness and luminous efficiency of the display elements DE1, DE2, and DE3 will be improved.

[0137] As a method of protecting the lower electrodes LE1, LE2, LE3 from the etching for forming the partition wall 6, it is also possible to form the pixel openings AP1, AP2, AP3 after forming the partition wall 6 instead of forming the pixel openings AP1, AP2, AP3 as in the present embodiment. However, in this case, the number of photolithography steps for processing the rib 5 increases compared to the present embodiment.

[0138] That is, the partition wall 6 is connected to the common voltage supply line through the opening of the rib 5 provided in the peripheral area SA. In order to provide the opening, a photolithography process must be performed on the rib 5 before forming the partition wall 6. Therefore, when forming the pixel openings AP1, AP2, and AP3 after forming the partition wall 6, it is necessary to perform at least two photolithography processes on the rib 5.

[0139] In contrast, when the pixel openings AP1, AP2, and AP3 are provided before forming the partition wall 6 as in the present embodiment, the opening of the peripheral area SA can also be provided simultaneously in the photolithography process. Therefore, compared with the case where the pixel openings AP1, AP2, and AP3 are formed after forming the partition wall 6, the number of photolithography processes can be reduced.

[0140] Furthermore, when the pixel openings AP1, AP2, and AP3 are formed after the partition walls 6 are formed, the resist for processing the ribs 5 may not be uniformly applied due to the cantilevered partition walls 6. In contrast, when the pixel openings AP1, AP2, and AP3 are provided before the partition walls 6 are formed as in the present embodiment, the resist for processing the ribs 5 can be uniformly applied. Fig.7D The resist R2) improves the accuracy of the shape of the rib 5.

[0141] In addition to the above, various appropriate effects can be obtained according to the present embodiment.

[0142] [Second embodiment]

[0143] The second embodiment is described. The same reference numerals are used for the same elements as those in the first embodiment, and their description is omitted. In addition, regarding the configuration and manufacturing process of the display device DSP not particularly mentioned in this embodiment, the same configuration and manufacturing process as those in the first embodiment can be applied.

[0144] Fig. 9 is a schematic cross-sectional view of the display device DSP of this embodiment, and Figure 5 The structure of the partition wall 6 and its vicinity is also shown. Fig. 9 In the example, the conductive oxide layer CL is located at Figure 5 The examples are different.

[0145] That is, in this embodiment, the conductive oxide layer CL is disposed between the lower electrodes LE1 and LE2 and the ribs 5. Fig. 9 Although not shown, a conductive oxide layer CL is also disposed between the lower electrode LE3 and the rib 5. The conductive oxide layer CL covers the peripheral edge of the second covering layer V2 of the lower electrodes LE1, LE2, and LE3. In this embodiment, the bottom 60 of the partition 6 is in contact with the upper surface of the rib 5.

[0146] exist Fig. 9 In the example, the ends of the lower electrodes LE1 and LE2 overlap with the lower portion 61 in the Z direction. In addition, the organic layers OR1 and OR2 are separated from the lower portion 61. In addition, one end of the conductive oxide layer CL overlaps with the lower portion 61 in the Z direction, but the other end does not overlap with the lower portion 61 in the Z direction.

[0147] Fig.10 1 is a schematic plan view of the rib 5, the lower electrodes LE1, LE2, LE3, and the conductive oxide layer CL of the present embodiment. The hatched portion in the figure corresponds to the conductive oxide layer CL.

[0148] The conductive oxide layer CL is disposed in the region where the lower electrodes LE1, LE2, LE3 overlap with the rib 5. That is, the conductive oxide layer CL has openings APc overlapping with the pixel openings AP1, AP2, AP3, respectively. From another viewpoint, the conductive oxide layer CL surrounds the display elements DE1, DE2, DE3, respectively.

[0149] It should be noted that in Fig.10 1, 1 , and 1 , respectively, of the lower electrodes LE1, LE2, and LE3 and three conductive oxide layers CL overlapping these electrodes are shown in FIG. Such conductive oxide layers CL are provided for all the lower electrodes LE1, LE2, and LE3 of the display device DSP.

[0150] Fig.11 Yes Fig. 9 The partition wall 6 and its vicinity are shown in an enlarged schematic cross-sectional view. In this figure, the substrate 10, the circuit layer 11, the organic insulating layer 12, the sealing layer SE11, the resin layers RS1 and RS2, and the sealing layer SE2 are omitted.

[0151] The conductive oxide layer CL is in contact with the upper surface of the second covering layer V2. Fig.11 In the example, the end E3 of the rib 5 along the pixel opening AP1 protrudes more than the end E2 of the conductive oxide layer CL. Thus, a gap is formed below the end E3. The protrusion length of the end E3 from the end E2 is, for example, 50 nm to 1000 nm.

[0152] exist Fig.11 In the example of , the hole injection layer HIL of the organic layer OR1 is cut off at the end E3. Thus, similarly to the first embodiment, leakage current through the hole injection layer HIL can be suppressed.

[0153] On the other hand, the hole transport layer HTL is not cut off at the end E3. The layers formed above the hole transport layer HTL in the organic layer OR1 (such as the electron blocking layer EBL, the light emitting layer EML, the hole blocking layer HBL, the electron transport layer ETL and the electron injection layer EIL) are also not cut off at the end E3.

[0154] As in the first embodiment, the thickness T1 of the conductive oxide layer CL is preferably greater than, for example, the thickness T2 of the hole injection layer HIL (T2 < T1), and less than the total thickness T3 of the hole injection layer HIL and the hole transport layer HTL (T1 < T3). Thus, the hole injection layer HIL is easily cut off at the end E3, and the hole transport layer HTL is not easily cut off at the end E3.

[0155] exist Fig.11 In the example of FIG. 1 , the region below the end E3 is filled with the hole transport layer HTL. However, a gap may be formed in at least a portion of the region. Fig.11 In FIG. 1 , attention is paid to the structure near the end of the stacked film FL1 , but the structure near the end of the stacked films FL2 and FL3 is similar.

[0156] In the present embodiment, the conductive oxide layer CL is formed of, for example, amorphous IZO or IGZO. In addition, the rib 5 is formed of, for example, silicon oxynitride.

[0157] Next, an example of a method for manufacturing the display device DSP according to the present embodiment will be described.

[0158] FIG. 12A to FIG. 12M 1 and 2 are schematic cross-sectional views showing the manufacturing process before forming the display elements DE1, DE2, and DE3. In these figures, the substrate 10 and the circuit layer 11 are omitted. FIG. 8A to FIG. 8D same.

[0159] When manufacturing the display device DSP, first, the circuit layer 11 and the organic insulating layer 12 are formed on the substrate 10. Then, the first covering layer V1a, the reflective layer RLa, and the second covering layer V2a are sequentially formed on the organic insulating layer 12 in the same manner as in the first embodiment.

[0160] In this embodiment, if Fig. 12A As shown in FIG. 1 , a conductive oxide layer CLa is formed on the second covering layer V2a by sputtering. Furthermore, a resist R1 having a shape corresponding to the lower electrodes LE1 , LE2 , and LE3 is disposed on the conductive oxide layer CLa.

[0161] Next, the conductive oxide layer CLa, the reflective layer RLa, and the coating layers V1a and V2a are patterned into the shape of the resist R1. Specifically, the portions of the conductive oxide layer CLa, the reflective layer RLa, and the coating layers V1a and V2a exposed from the resist R1 are removed by wet etching. Fig. 12BAs shown, the lower electrodes LE1, LE2, and LE3 including the reflective layer RL, the first cover layer V1, and the second cover layer V2 are formed. At this time, the entirety of the lower electrodes LE1, LE2, and LE3 are covered with the conductive oxide layer CLa.

[0162] After forming the lower electrodes LE1, LE2, LE3, as Fig. 12C As shown, the resist R1 is removed. Furthermore, the entire substrate is heated, whereby the conductive oxide constituting the covering layers V1 and V2 is fired.

[0163] In the present embodiment, the coating layers V1 and V2 are formed of ITO, and the conductive oxide layer CLa is formed of IZO or IGZO. That is, the coating layers V1 and V2 and the conductive oxide layer CL are formed of different conductive oxides.

[0164] The firing temperature is set to a temperature at which ITO is crystallized but IZO or IGZO is not crystallized. That is, by the firing, the coating layers V1 and V2 are crystallized, but the conductive oxide layer CLa remains amorphous.

[0165] Next, if Fig.12D As shown, the rib layer 5a covering the lower electrodes LE1, LE2, and LE3 is formed by CVD. Moreover, a resist R2 having a shape corresponding to the rib 5 is disposed on the rib layer 5a. In this embodiment, the rib layer 5a is formed of silicon oxynitride.

[0166] Next, the portion of the rib layer 5a exposed from the resist R2 is removed by dry etching. Fig.12E As shown in FIG. 1 , a rib 5 having pixel openings AP1, AP2, and AP3 overlapping the lower electrodes LE1, LE2, and LE3 is formed. After the rib 5 is formed, as shown in FIG. Fig.12F As shown, the resist R2 is removed.

[0167] After forming the rib 5, as Figure 12G As shown, the base layer 60a, the lower layer 61a, the first cap layer 63a and the second cap layer 64a are formed in this order by sputtering. In addition, a resist R3 having a shape corresponding to the partition wall 6 is disposed on the second cap layer 64a.

[0168] Next, the portion of the second top layer 64a exposed from the resist R3 is removed by wet etching. Fig.12H As shown, a second top layer 64 is formed. Fig.12H In the example of , the width of the second top layer 64 is slightly smaller than that of the resist R3.

[0169] Furthermore, dry etching is performed using the resist R3 as a mask to remove the portion of the first top layer 63a exposed from the resist R3. Fig.12I As shown, the first cap layer 63 is formed. As in the first embodiment, in this dry etching, the thickness of the portion of the lower layer 61a exposed from the resist R3 is also reduced.

[0170] Next, wet etching is performed on the lower layer 61a. Thus, the portion of the lower layer 61a exposed from the resist R3 is removed. In addition, the side surface of the lower layer 61a is eroded, and its width is reduced compared to the top layers 63 and 64. Thus, as shown in FIG. Fig.12J As shown, a lower portion 61 is formed.

[0171] After the lower portion 61 is formed, the bottom layer 60a is patterned by dry etching. Specifically, the portion of the bottom layer 60a exposed from the resist R3 is removed by dry etching. Figure 12K As shown, a bottom portion 60 is formed.

[0172] Through the above steps, the partition wall 6 including the bottom 60, the lower part 61 and the upper part 62 is completed. After the partition wall 6 is formed, the conductive oxide layer CLa is patterned by wet etching. Specifically, in the wet etching, the portion of the conductive oxide layer CLa exposed from the rib 5 through the pixel openings AP1, AP2, and AP3 is removed. Figure 12L As shown, a conductive oxide layer CL is formed to cover the peripheral portions of the lower electrodes LE1, LE2, and LE3.

[0173] As in the first embodiment, as an etching solution for the conductive oxide layer CLa, for example, oxalic acid can be used. Fig.11 As shown, the end E2 of the conductive oxide layer CL is set back from the end E3 of the rib 5 along the pixel openings AP1 , AP2 , and AP3 .

[0174] After forming the conductive oxide layer CL, as Figure 12M As shown, the resist R3 is removed. The steps for forming the display elements DE1, DE2, and DE3 performed thereafter are the same as those of the first embodiment.

[0175] Even in the configuration of this embodiment, the lower electrodes LE1, LE2, and LE3 can be protected from the etching for forming the partition wall 6, as in the first embodiment. In addition, the second coating layer V2 can be formed thinner than in the case where there is no conductive oxide layer CL, thereby improving the brightness and luminous efficiency of the display elements DE1, DE2, and DE3. In addition, since the pixel openings AP1, AP2, and AP3 are provided before forming the partition wall 6, the number of photolithography steps for the rib 5 can be reduced.

[0176] It should be noted that, in this embodiment, the rib 5 is not covered by the conductive oxide layer CLa. Therefore, the rib 5 is exposed to the etching of the partition 6. However, as described above, by forming the rib 5 from silicon oxynitride, damage to the rib 5 can be suppressed compared to the case where the rib 5 is formed from silicon nitride.

[0177] As long as the gist of the present invention is included, all display devices and methods of manufacturing the same that can be implemented by a person skilled in the art by appropriately changing the design based on the display device and method of manufacturing the same disclosed in the above embodiments also fall within the scope of the present invention.

[0178] Within the scope of the concept of the present invention, those skilled in the art can think of various variations, and these variations should also be understood to belong to the scope of the present invention. For example, the scheme obtained by adding, deleting or designing the above-mentioned embodiments appropriately by those skilled in the art, or the scheme obtained by adding, omitting or changing the conditions of the processes, as long as they have the gist of the present invention, is also included in the scope of the present invention.

[0179] In addition, regarding other effects brought about by the scheme described in the above-mentioned embodiment, the effects that can be clearly understood from the description of this specification or the technical effects that can be appropriately thought of by those skilled in the art should of course be understood as the effects brought about by the present invention.

Claims

1. A display device comprising: Lower electrode; a rib having a pixel opening overlapping the lower electrode and covering an end portion of the lower electrode; a partition wall including a bottom portion disposed on the rib portion, a lower portion disposed on the bottom portion, and an upper portion disposed on the lower portion and protruding from a side surface of the lower portion; an organic layer that contacts the lower electrode through the pixel opening and emits light in response to application of a voltage; an upper electrode covering the organic layer and contacting at least one of the bottom portion and the lower portion; and A transparent conductive oxide layer is disposed between the rib and the bottom.

2. The display device according to claim 1, wherein: The conductive oxide layer is formed of amorphous ITO, IZO or IGZO.

3. The display device according to claim 1, wherein: The rib is formed of silicon nitride, silicon oxide or silicon oxynitride.

4. The display device according to claim 1, wherein: An end portion of the bottom portion protrudes from an end portion of the conductive oxide layer.

5. The display device according to claim 1, wherein: The organic layer includes a hole injection layer in contact with the lower electrode, The thickness of the conductive oxide layer is greater than the thickness of the hole injection layer.

6. The display device according to claim 5, wherein: The organic layer further includes a hole transport layer covering the hole injection layer. The thickness of the conductive oxide layer is smaller than the total thickness of the hole injection layer and the hole transport layer.

7. The display device according to claim 1, wherein: The lower electrode comprises: a reflective layer formed of a metal material; and The covering layer is formed of a transparent conductive oxide having higher crystallinity than the conductive oxide layer and covers the upper surface of the reflective layer.

8. The display device according to claim 1, wherein: An end of the bottom portion protrudes from an end of the conductive oxide layer, The bottom portion and the lower portion are formed of different materials.

9. The display device according to claim 1, wherein: An end portion of the lower electrode overlaps the lower portion.

10. The display device according to claim 1, wherein: The upper portion includes a first top layer arranged on the lower portion and a second top layer arranged on the first top layer, The first top layer and the second top layer are formed of different materials, An end portion of the first top layer protrudes from an end portion of the second top layer.

11. The display device according to claim 1, wherein: The organic layer is separated from the lower portion.

12. The display device according to claim 1, wherein: The end portion of the conductive oxide layer does not overlap with the lower portion.

13. The display device according to claim 1, wherein: The organic layer includes a hole injection layer in contact with the lower electrode, An end portion of the conductive oxide layer overlaps with the hole injection layer.

14. The display device according to claim 1, wherein: An end portion of the conductive oxide layer overlaps the upper electrode.

15. A display device comprising: Lower electrode; a rib having a pixel opening overlapping the lower electrode and covering an end portion of the lower electrode; a partition wall including a bottom portion disposed on the rib portion, a lower portion disposed on the bottom portion, and an upper portion disposed on the lower portion and protruding from a side surface of the lower portion; an organic layer that contacts the lower electrode through the pixel opening and emits light in response to application of a voltage; an upper electrode covering the organic layer and contacting at least one of the bottom portion and the lower portion; and A transparent conductive oxide layer is disposed between the lower electrode and the rib and has an opening overlapping with the pixel opening.

16. The display device according to claim 15, wherein: The lower electrode comprises: a reflective layer formed of a metal material; and The covering layer is formed of a transparent conductive oxide different from the conductive oxide layer and covers the upper surface of the reflective layer.

17. The display device according to claim 15, wherein: An end portion of the lower electrode overlaps the lower portion.

18. The display device according to claim 15, wherein: The upper portion includes a first top layer arranged on the lower portion and a second top layer arranged on the first top layer, The first top layer and the second top layer are formed of different materials, An end portion of the first top layer protrudes from an end portion of the second top layer.

19. The display device according to claim 15, wherein: The organic layer is separated from the lower portion.

20. The display device according to claim 15, wherein: One end of the conductive oxide layer overlaps with the lower portion, The other end portion of the conductive oxide layer does not overlap with the lower portion.

Images