Time domain multi-channel true convolution circuit based on SRAM (Static Random Access Memory) storage calculation

Abstract

The invention discloses a time-domain multi-channel true convolution circuit based on SRAM (Static Random Access Memory) storage and calculation. The time-domain multi-channel true convolution circuit comprises a digital signal delay array, an SRAM (Static Random Access Memory) storage and calculation module and a time-domain multi-channel true convolution calculation module, n current steering type multipliers, wherein each current steering type multiplier comprises a charge sharing type adder, an SRAM (Static Random Access Memory) array and M current steering type multipliers; the SRAM array is used for storing weight data and sign bit data; each current steering multiplier is used for carrying out multiplication operation on the time mode signal / time mode delay signal and the weight data under sign bit data selection to output a voltage difference value at two ends of the capacitor after the capacitor is charged and discharged; the charge sharing type adder is used for carrying out additive operation on the voltage difference value at the two ends of the capacitor and outputting a capacitor charge sharing result; the thermometer code analog-to-digital converter is used for carrying out analog-to-digital conversion on the charge sharing result to obtain N thermometer code pulses. According to the method, high-reliability and high-energy-efficiency calculation of multiplication and addition operation in convolution is realized.

Description

Technical Field

[0001] The invention belongs to the technical field of SRAM in-memory computing, and in particular relates to a time domain multi-channel true convolution circuit based on SRAM in-memory computing. Background Art

[0002] Convolution circuits are currently widely used in face recognition, speech recognition and other fields. However, under the existing von Neumann architecture system, a large number of multiplication and addition operations in convolution operations greatly consume hardware resources, and the frequent access to storage and computing makes it have problems such as high power consumption and large latency in the deployment of terminal devices. Based on this, researchers have conducted a detailed study of in-memory computing systems and proposed a computing architecture based on memristors, DRAM (Dynamic Random Access Memory), Flash and other memories. However, the process reliability and energy efficiency of these memories need to be improved. Therefore, it is urgent to design a time-domain multi-channel true convolution circuit with high reliability and high energy efficiency. Summary of the invention

[0003] In order to solve the above problems existing in the prior art, the present invention provides a time domain multi-channel true convolution circuit based on SRAM storage calculation. The technical problem to be solved by the present invention is achieved by the following technical solutions:

[0004] An embodiment of the present invention provides a time domain multi-channel true convolution circuit based on SRAM storage and calculation, and the time domain multi-channel true convolution circuit includes:

[0005] An internal timing generation circuit, used for generating a quantization enable signal, a multiplication-addition operation enable signal and a digital delay enable signal;

[0006] A digital signal delay array, used to delay the time mode signal for a fixed time according to the digital delay enable signal to generate M-1 time mode delay signals;

[0007] A current steering type multiplier and adder with N channels, each current steering type multiplier and adder of each channel includes M current steering type multipliers, a charge sharing type adder and an SRAM array; the SRAM array is used to store weight data and sign bit data, the weight data is used to control the size of the current generated by the current steering, and the sign bit data is used to control the direction of the current steering; each current steering type multiplier is used to perform a multiplication operation on the time mode signal / time mode delay signal and the weight data under the selection control of the sign bit data to output the voltage difference between the two ends of the corresponding capacitor after charging and discharging, the time mode signal and M-1 time mode delay signals are used to control the charging and discharging time of the capacitor in the M current steering type multipliers; the charge sharing type adder is used to perform an addition operation on the voltage difference between the two ends of the capacitor output by the M current steering type multipliers under the control of the multiplication and addition operation enable signal to output the corresponding capacitor charge sharing result;

[0008] The thermometer code analog-to-digital converter is used to perform analog-to-digital conversion on the N capacitor charge sharing results according to the thermometer logic under the control of the quantization enable signal to obtain N thermometer code pulses.

[0009] In one embodiment of the present invention, the digital signal delay array includes M-1 digital signal delay units connected in sequence.

[0010] In one embodiment of the present invention, each digital signal delay unit includes a rising edge detector, a falling edge detector, a transistor MP1, a transistor MP2, a transistor MN1, a transistor MN2, a current source I1, a current source I2, a capacitor C11, a capacitor C12, inverters INV1 to INV3, and an AND gate circuit AND1; wherein,

[0011] One end of the rising edge detector and one end of the falling edge detector are connected and serve as the input end of the digital signal delay unit, the other end of the rising edge detector is connected to the gate of the transistor MP1 and the gate of the transistor MN1, the drain of the transistor MP1 is connected to the drain of the transistor MN1, one end of the capacitor C11, and one end of the inverter INV1, the source of the transistor MN1 is connected to the positive electrode of the current source I1, the other end of the falling edge detector is connected to the gate of the transistor MP2 and the gate of the transistor MN2, the drain of the transistor MP2 is connected to the drain of the transistor MN2, one end of the capacitor C12, and one end of the inverter INV1. One end of NV2 is connected, the source of transistor MN2 is connected to the positive electrode of current source I2, the other end of inverter INV2 is connected to one end of inverter INV3, the other end of inverter INV1 is connected to the first input end of AND gate circuit AND1, the other end of inverter INV3 is connected to the second input end of AND gate circuit AND1, and the output end of AND gate circuit AND1 serves as the output end of digital signal delay unit; the source of transistor MP1 and the source of transistor MP2 are both connected to power supply VDD, the negative electrode of current source I1, the negative electrode of current source I2, the other end of capacitor C11 and the other end of capacitor C12 are all grounded.

[0012] In one embodiment of the present invention, the structure of each current steering type multiplier is the same; the mth current steering type multiplier includes a first group of current steering structures and a second group of current steering structures, the first group of current steering structures and the second group of current steering structures respectively include current steering sub-structures of P pieces connected in parallel, and m is 1 to M; wherein the operation of the first group of current steering structures or the second group of current steering structures is determined by the sign bit data.

[0013] In one embodiment of the present invention, each current steering substructure of the first group of current steering structures in the mth current steering type multiplier includes an AND gate circuit AND2, a switch SW11, a transistor MN3 and a current source I3; wherein,

[0014] A first input end of the AND gate circuit AND2 is connected to the SRAM array, a second input end of the AND gate circuit AND2 is connected to the digital signal delay array, an output end of the AND gate circuit AND2 is connected to the control end of the switch SW11, a data input end of the switch SW11 is connected to the SRAM array, an output end of the switch SW11 is connected to the gate of the transistor MN3, a source of the transistor MN3 is connected to the positive electrode of the current source I3, a drain of the transistor MN3 serves as the output end of the mth current steering multiplier, and a negative electrode of the current source I3 is grounded.

[0015] In one embodiment of the present invention, each current steering substructure of the second group of current steering structures in the mth current steering type multiplier includes an AND gate circuit AND3, a switch SW12, a transistor MP3, a current source I4, an inverter INV4 and an inverter INV5; wherein,

[0016] One end of the inverter INV4 is connected to the SRAM array, the other end of the inverter INV4 is connected to the first input end of the AND gate circuit AND3, the second input end of the AND gate circuit AND3 is connected to the digital signal delay array, the output end of the AND gate circuit AND3 is connected to the control end of the switch SW12, the data input end of the switch SW12 is connected to one end of the inverter INV5, the other end of the inverter INV5 is connected to the SRAM array, the output end of the switch SW12 is connected to the gate of the transistor MP3, the source of the transistor MP3 is connected to the positive electrode of the current source I4, the drain of the transistor MP3 is connected to the drain of the transistor MN3, and the negative electrode of the current source I4 is grounded.

[0017] In one embodiment of the present invention, the charge sharing adder includes a capacitor C 1 ~Capacitor C M , switch SW 1 ~Switch SW M-1 ;in,

[0018] Switch SW 1 ~Switch SW M-1 Connect in sequence, switch SW m1 The data input terminal and capacitor C m1 The output terminal of the m1th current steering multiplier is connected to the capacitor C m1 The other end of the switch is grounded, m1 is 1 to M-1, and the switch SW M-1 The output terminal and capacitor C M The output terminal of the Mth current steering multiplier is connected to the switch SW M-1 The output end of the charge sharing adder is used as the output end of the capacitor C M The other end of the switch SW is grounded. 1 ~Switch SW M-1 The control ends are all connected to the internal timing generation circuit.

[0019] In one embodiment of the present invention, the time domain multi-channel true convolution circuit further includes:

[0020] The internal timing generation circuit is also used to generate a capacitor voltage reset signal;

[0021] Each current steering type multiplier and adder also includes a capacitor voltage reset circuit; the capacitor voltage reset circuit is used to pre-charge the capacitor in the corresponding current steering type multiplier under the control of the capacitor voltage reset signal.

[0022] In one embodiment of the present invention, the capacitor voltage reset circuit includes a switch SW' 1 ~Switch SW' M ; Switch SW' 1 ~Switch SW' M The control terminals of the switches SW' are connected to the internal timing generation circuit. m The data input terminal of is connected to the output terminal of the mth current steering multiplier, and the switch SW' 1 ~Switch SW' M The output ends are connected to the pre-charge source VDD1.

[0023] In one embodiment of the present invention, the time domain multi-channel true convolution circuit further includes:

[0024] The internal timing generation circuit is also used to generate a signal generation enable signal;

[0025] A triangular wave generating circuit, used for generating a triangular wave signal under the control of the signal generation enabling signal;

[0026] The time domain modulation circuit is used to modulate the voltage type input signal using the triangle wave signal to generate the time mode signal.

[0027] Beneficial effects of the present invention:

[0028] The time domain multi-channel true convolution circuit based on SRAM storage and calculation proposed by the present invention realizes high reliability and high energy efficiency calculation of multiplication and addition operations in time domain multi-channel convolution. Specifically: the SRAM array is innovatively used to store weight data and sign bit data. In the charging and discharging process of each capacitor of the current steering type multiplier and adder of each channel, the weight data is used to control the size of the current steering current during charging and discharging, and the sign bit data is used to control the direction of the current steering current during charging and discharging. At the same time, the digital signal delay array is used to control the charging and discharging time, so that the weight data and the time mode signal / time mode delay signal are multiplied under the selection control of the sign bit data to obtain the voltage difference between the two ends of the capacitor before and after charging and discharging of each capacitor in the current steering type multiplier and adder of each channel, and then the charge sharing type adder is used to distribute the charge evenly according to the voltage difference between the two ends of the capacitor before and after charging and discharging of each capacitor, and the addition operation is completed. Finally, the thermometer code analog-to-digital converter outputs the thermometer code pulse. Through the above processing process, the present invention can reduce the power consumption and delay of the multiplication and addition operation in the convolution and improve the operation efficiency of the convolution.

[0029] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 It is a structural schematic diagram of a time domain multi-channel true convolution circuit based on SRAM storage and calculation provided by an embodiment of the present invention;

[0031] Figure 2 is a structural schematic diagram of a digital signal delay array provided by an embodiment of the present invention;

[0032] Figure 3 The embodiment of the present invention provides Figure 2 The timing diagram corresponding to the structure shown;

[0033] Figure 4 is a structural schematic diagram of a digital signal delay unit in a digital signal delay array provided in an embodiment of the present invention;

[0034] Figure 5 The embodiment of the present invention provides Figure 5 A timing diagram corresponding to a certain digital signal delay unit in the structure shown;

[0035] Figure 6 is a schematic diagram of the structure of each current steering type multiplier provided by an embodiment of the present invention;

[0036] Figure 7 The embodiment of the present invention provides Figure 6 The timing diagram corresponding to the structure shown;

[0037] Figure 8 is a schematic diagram of the structure of each charge sharing adder provided by an embodiment of the present invention;

[0038] Fig. 9 It is a structural schematic diagram of another time domain multi-channel true convolution circuit based on SRAM storage and calculation provided by an embodiment of the present invention;

[0039] Fig.10 The embodiment of the present invention provides Fig. 9 Schematic diagram of the waveform of the time mode signal output after modulation by the time domain modulation circuit. DETAILED DESCRIPTION

[0040] The present invention is further described in detail below with reference to specific embodiments, but the embodiments of the present invention are not limited thereto.

[0041] See also Figure 1 The embodiment of the present invention provides a time domain multi-channel true convolution circuit based on SRAM storage and calculation, and the time domain multi-channel true convolution circuit includes:

[0042] An internal timing generation circuit, used for generating a quantization enable signal, a multiplication-addition operation enable signal and a digital delay enable signal;

[0043] A digital signal delay array, used to delay the time mode signal for a fixed time according to a digital delay enable signal to generate M-1 time mode delay signals;

[0044] A current steering type multiplier and adder with N channels, wherein the current steering type multiplier and adder of each channel includes M current steering type multipliers, a charge sharing type adder and an SRAM array; the SRAM array is used to store weight data and sign bit data, the weight data is used to control the magnitude of the current generated by the current steering, and the sign bit data is used to control the direction of the current steering; each current steering type multiplier is used to perform a multiplication operation on the time mode signal / time mode delay signal and the weight data under the selection control of the sign bit data to output the voltage difference between the two ends of the corresponding capacitor after charging and discharging, and the time mode signal and M-1 time mode delay signals are used to control the charging and discharging time of the capacitor in the M current steering type multipliers; the charge sharing type adder is used to perform an addition operation on the voltage difference between the two ends of the capacitor output by the M current steering type multipliers under the control of the multiplication and addition operation enable signal to output the corresponding capacitor charge sharing result;

[0045] The thermometer code analog-to-digital converter is used to perform analog-to-digital conversion on the N capacitor charge sharing results according to the thermometer logic under the control of the quantization enable signal to obtain N thermometer code pulses.

[0046] Next, each part of the proposed time-domain multi-channel true convolution circuit based on SRAM storage is introduced in detail.

[0047] The internal timing generation circuit of the embodiment of the present invention is not limited to the design form of the circuit, as long as it can generate the required quantization enable signal, multiplication and addition operation enable signal and digital delay enable signal.

[0048] Furthermore, the digital signal delay array of the embodiment of the present invention is as follows Figure 2 As shown, it includes M-1 digital signal delay units connected in sequence. Figure 3 Indicated Figure 2 The timing corresponding to the structure shown is, Figure 2VSIG_BUF[1] is the time mode signal of the input digital signal delay array, VSIG_BUF <2> VSIG_BUF <1> The time mode delayed signal obtained by a digital signal delay unit, VSIG_BUF[1] and VSIG_BUF <2> The time difference is T, T is set according to actual needs, VSIG_BUF <3> VSIG_BUF <1> The time mode delayed signal obtained by two digital signal delay units, VSIG_BUF[1] and VSIG_BUF <3> The time difference is 2*T, and so on, VSIG_BUF <m>VSIG_BUF <1> The time mode delayed signal obtained by M-1 digital signal delay units, VSIG_BUF[1] and VSIG_BUF <m>The time difference is (M-1)*T. Figure 3 Medium VSIG_BUF <1> , ..., VIG_BUF <m>and Figure 1 VSIG_BUF <1> , ..., VIG_BUF <m>Corresponding.

[0049] Each digital signal delay unit is Figure 4 As shown, it includes a rising edge detector, a falling edge detector, a transistor MP1, a transistor MP2, a transistor MN1, a transistor MN2, a current source I1, a current source I2, a capacitor C11, a capacitor C12, inverters INV1 to INV3, and an AND gate circuit AND1; wherein one end of the rising edge detector and one end of the falling edge detector are connected and serve as the input end of the digital signal delay unit, the other end of the rising edge detector is connected to the gate of the transistor MP1 and the gate of the transistor MN1, the drain of the transistor MP1 is connected to the drain of the transistor MN1, one end of the capacitor C11, and one end of the inverter INV1, the source of the transistor MN1 is connected to the positive electrode of the current source I1, the other end of the falling edge detector is connected to the gate of the transistor MP2 and the gate of the transistor MN2 The gate is connected, the drain of the transistor MP2 is connected to the drain of the transistor MN2, one end of the capacitor C12, and one end of the inverter INV2, the source of the transistor MN2 is connected to the positive electrode of the current source I2, the other end of the inverter INV2 is connected to one end of the inverter INV3, the other end of the inverter INV1 is connected to the first input end of the AND gate circuit AND1, the other end of the inverter INV3 is connected to the second input end of the AND gate circuit AND1, and the output end of the AND gate circuit AND1 serves as the output end of the digital signal delay unit; the source of the transistor MP1 and the source of the transistor MP2 are both connected to the power supply VDD, for example, the voltage of the power supply VDD is 5V, the negative electrode of the current source I1, the negative electrode of the current source I2, the other end of the capacitor C11, and the other end of the capacitor C12 are all grounded. Figure 5 Indicated Figure 4 The timing corresponding to a digital signal delay unit in the structure shown is based on the signal VSIG_BUF input to the first digital signal delay unit. <1> For example: Figure 5 VSIG_BUF_UP is VSIG_BUF <1> Through the output of the rising edge detector, when VSIG_BUF <1> When the rising edge arrives, VSIG_BUF_UP rises from low level to high level; Figure 5 VSIG_BUF_DOWN is VSIG_BUF <1> Through the output of the falling edge detector, when VSIG_BUF <1> When the falling edge arrives, VSIG_BUF_DOWN rises from low level to high level; Figure 5 In the figure, VSIG_BUF_UP passes through the delay unit composed of MP1, MN1, I1, C11, and INV1, and the output is VSIG_BUF_UP_DELAY; in the figure, VSIG_BUF_DOWN passes through the delay unit composed of MP2, MN2, I2, C12, INV2, and INV3, and the output is VSIG_BUF_DOWN_DELAY; Figure 5 In the circuit, VSIG_BUF_UP_DELAY and VSIG_BUF_DOWN_DELAY are output through the AND gate circuit AND1 to VSIG_BUF_DELAY, so as to complete the VISG_BUF <1> Delay operation, it can be seen that VSIG_BUF <1> The time difference from VSIG_BUF_DELAY is T; Figure 5 VSIG_BUF_UP and VSIG_BUF_DOWN will be reset to low level through the internal timing logic circuit, waiting for VSIG_BUF <1> The other time mode delay signals VSIG_BUF[2], VSIG_BUF[3], ..., VSIG_BUF[M-1] adopt similar delay methods, which will not be described in detail here.

[0050] The embodiment of the present invention is Figure 2 and Figure 3 The circuit structure shown in the figure realizes delaying the time mode signal VSIG_BUF[1] by a fixed time according to the digital delay enable signal to generate M-1 time mode delay signals, and using VSIG_BUF[1], VSIG_BUF[2], VSIG_BUF[3], ..., VSIG_BUF[M], a total of M signals, as the charging and discharging time of each capacitor in each subsequent current steering type multiplier.

[0051] Furthermore, the time domain multi-channel true convolution circuit proposed in the embodiment of the present invention includes N current steering type multipliers and adders, and the circuit structures of the N current steering type multipliers and adders are the same; each current steering type multiplier and adder includes M current steering type multipliers, a charge sharing adder and an SRAM array; each current steering type multiplier has the same structure; the mth current steering type multiplier is as follows Figure 6 As shown, it includes a first group of current steering structures and a second group of current steering structures. The first group of current steering structures and the second group of current steering structures respectively include P pieces of current steering sub-structures connected in parallel, and m takes a value of 1 to M; wherein the first group of current steering structures or the second group of current steering structures work is determined by the sign bit data VSEL. For different current steering type multipliers and adders, the weight data VS[n] and the sign bit data VSEL stored in the SRAM array are different; the weight data stored in the SRAM array is recorded as VS[n], n = [P:1], n represents the nth piece of current steering sub-structure, then VS[n] represents the weight data stored in the SRAM array corresponding to the nth piece of current steering sub-structure, it can be seen that: when the weight data VS[n] is stored in the SRAM array, it is P bit storage, the sign bit data is recorded as VSEL, and the sign bit data VSEL in the SRAM array is 1 bit storage.

[0052] In the embodiment of the present invention, each current steer substructure of the first group of current steer structures in the mth current steer type multiplier includes an AND gate circuit AND2, a switch SW11, a transistor MN3 and a current source I3; wherein, the first input end of the AND gate circuit AND2 is connected to the SRAM array, the second input end of the AND gate circuit AND2 is connected to the digital signal delay array, the output end of the AND gate circuit AND2 is connected to the control end of the switch SW11, the data input end of the switch SW11 is connected to the SRAM array, the output end of the switch SW11 is connected to the gate of the transistor MN3, the source of the transistor MN3 is connected to the positive electrode of the current source I3, the drain of the transistor MN3 serves as the output end of the mth current steer type multiplier, and the negative electrode of the current source I3 is grounded. wherein, each current steer of the first group of current steer structures in the mth current steer type multiplier is connected to VSIG_BUF[m] output by the digital signal delay array, Figure 6 FIG. 4 illustrates a situation in which each current steering piece of the first group of current steering structures is connected to VSIG_BUF[1] output by the digital signal delay array.

[0053] In the embodiment of the present invention, each current steering substructure of the second group of current steering structures in the mth current steering type multiplier includes an AND gate circuit AND3, a switch SW12, a transistor MP3, a current source I4, an inverter INV4 and an inverter INV5; wherein, one end of the inverter INV4 is connected to the SRAM array, the other end of the inverter INV4 is connected to the first input end of the AND gate circuit AND3, the second input end of the AND gate circuit AND3 is connected to the digital signal delay array, the output end of the AND gate circuit AND3 is connected to the control end of the switch SW12, the data input end of the switch SW12 is connected to one end of the inverter INV5, the other end of the inverter INV5 is connected to the SRAM array, the output end of the switch SW12 is connected to the gate of the transistor MP3, the source of the transistor MP3 is connected to the positive electrode of the current source I4, the drain of the transistor MP3 is connected to the drain of the transistor MN3, and the negative electrode of the current source I4 is grounded. The current source I4 of each current steering substructure in the second group of current steering structures is the same as the current source I3 of each current steering substructure in the first group of current steering structures; the current magnitude of the nth current steering substructure in the first group of current steering structures is 2 P-n I, I are set according to actual conditions.

[0054] The charge sharing adder in the embodiment of the present invention is as follows: Figure 8 As shown, including capacitor C 1 ~Capacitor C M , switch SW 1 ~Switch SW M-1 ; Among them, switch SW 1 ~Switch SW M-1 Connect in sequence, switch SW m1 The data input terminal and capacitor C m1 The output terminal of the m1th current steering multiplier is connected to the capacitor C m1 The other end of the switch is grounded, m1 is 1 to M-1, and the switch SW M-1 The output terminal and capacitor C M The output terminal of the Mth current steering multiplier is connected to the switch SW M-1 The output end of the charge sharing adder is used as the output end of the capacitor C M The other end of the switch SW is grounded. 1 ~Switch SW M-1 The control terminals are connected to the internal timing generation circuit.

[0055] The time domain multi-channel true convolution circuit in the embodiment of the present invention further includes:

[0056] The internal timing generation circuit is also used to generate a capacitor voltage reset signal, denoted as VRST;

[0057] Each current steering type multiplier and adder also includes a capacitor voltage reset circuit; the capacitor voltage reset circuit is used to pre-charge the capacitor in the corresponding current steering type multiplier under the control of the capacitor voltage reset signal.

[0058] The capacitor voltage reset circuit in the embodiment of the present invention includes a switch SW' 1 ~Switch SW' M ; Switch SW' 1 ~Switch SW' M The control terminals of the switches SW' are connected to the internal timing generation circuit. m The data input terminal of is connected to the output terminal of the mth current steering multiplier, and the switch SW' 1 ~Switch SW' M The output ends of the MOSFETs are connected to the pre-charge power source VDD1, wherein the pre-charge power source VDD1 is VDD / 2.

[0059] Figure 6 When the sign bit data VSEL is at a high level, the switch SW11 is controlled to discharge each capacitor in the current steering type multiplier and adder, and when VSEL is at a low level, the switch SW12 is controlled to charge each capacitor in the current steering type multiplier and adder; Figure 6 The weight data VS[n] stored in the SRAM array is used to control the NMOS tube MN3 and PMOS tube MP3 in the nth current steering substructure to determine the current size of 2 P-n Whether the current source I3 and current source I4 of I are turned on; when VSEL, VSIG_BUF <1> When VSIG_BUF and VS[n] are both high, the discharge current source and the upper plate of the capacitor are turned on, and the capacitor begins to discharge until VSIG_BUF <1> When VSEL is low, VSIG_BUF <1> When VS[n] and VS[n] are both high, the charging current source and the upper plate of the capacitor are turned on, and the capacitor starts to charge until VSIG_BUF <1> When it drops to a low level, the capacitor charging is completed.

[0060] Figure 6 The connection relationship between the first current steering multiplier and the charge sharing adder is shown. The drain output terminal of transistor MN3 provides a capacitor C 1 The voltage difference between the two ends of the capacitor required for charging and discharging, and so on, each current steering type multiplier provides the voltage difference between the two ends of the capacitor required for charging and discharging for the corresponding capacitor; Figure 6 to Figure 8 VSHARE is the multiplication and addition operation enable signal. When the capacitor C 1 ~Capacitor C M After the charge and discharge operation is completed, when it becomes a high level, the charge sharing adder is controlled to charge the capacitor C 1 ~Capacitor C M Perform charge sharing operation to complete addition operation; Figure 8 Medium Capacitor C 1 ~Capacitor C M All are multiplier capacitors, through the switch SW 1 ~Switch SW M-1 The capacitor C 1 ~Capacitor C M Connected in parallel with each other.

[0061] Figure 7 Where CLK is a one-cycle clock signal, which is used as the input of the internal timing generation circuit; VRST is the capacitor voltage reset signal; Figure 7 It can be seen that the timing requirements of CLK, VRST, and VSHARE are such that VSHARE becomes high in every half clock cycle of CLK to complete the addition operation.

[0062] The embodiment of the present invention is based on Figure 6 and Figure 8 The calculation of current steering multiplier and charge sharing adder is realized. The calculation process is divided into two steps: the first step is to precharge each capacitor in each current steering multiplier, for example, to VDD / 2. During precharging, switch SW' 1 ~Switch SW' M Close, switch SW 1 ~Switch SW M-1 The second step is to control the current steering multiplier through the SRAM array to charge and discharge each capacitor. During charging and discharging, the switch SW' 1 ~Switch SW' M Open, the charge and discharge time depends on VSIG_BUF <1> ,......,VSIG_BUF[M] pulse width, the charging and discharging speed depends on the weight data stored in the SRAM array, which controls the magnitude of the current steering current, and the charging and discharging direction depends on the sign bit data stored in the SRAM array, which controls the direction of the current steering current. After the charging and discharging is completed, SW 1 ~Switch SW M-1 Closed, the voltage difference between the two ends of the capacitor before and after charging and discharging is used as the result of the multiplication operation, and the results of all multiplication operations are shared by the charge sharing adder to complete the addition operation. It can be seen that each current steering multiplier in the embodiment of the present invention uses the relationship between the charging and discharging time of the capacitor and the current size and the voltage across the capacitor to realize the multiplication operation, and the multiplication result is stored in the voltage value of the capacitor; the charge sharing adder uses the charge sharing principle between parallel capacitors to realize the addition operation, which is actually an average value operation.

[0063] For further information, see Fig. 9 , the time domain multi-channel true convolution circuit of the embodiment of the present invention further includes:

[0064] The internal timing generation circuit is also used to generate a signal generation enable signal;

[0065] The triangular wave generating circuit is used to generate a triangular wave signal VTRI under the control of a signal generating enable signal; the triangular wave generating circuit can adopt an existing circuit;

[0066] The time domain modulation circuit is used to modulate the voltage input signal using a triangular wave signal to generate a time mode signal; here, the time domain modulation circuit can use a comparator to modulate the voltage input signal VIN at the positive end of the input comparator into a time mode signal VSIG_BUF using the triangular wave signal VTRI at the negative end of the input comparator. <1> , VSIG_BUF <1> It is a PWM (Pulse Width Modulation) wave signal. Fig.10 Indicated Fig. 9 The waveform of the time mode signal output after modulation by the time domain modulation circuit, Fig.10 The medium voltage input signal VIN is an irregular continuous waveform. Fig.10 Medium VSIG_BUF <1> The waveform shown shows that when VIN is greater than VTRI, VSIG_BUF <1> is 1; when VIN is less than VTRI, VSIG_BUF <1> is 0, thus realizing the time domain modulation of VIN.

[0067] The thermometer code analog-to-digital converter of the embodiment of the present invention is as follows Fig. 9 As shown, it includes N quantization pulse circuits, each of which is composed of a comparator and a thermometer logic, and is responsible for performing analog-to-digital conversion on the capacitor charge sharing result output by each charge sharing adder according to the thermometer logic to obtain N thermometer code pulses, and each thermometer code pulse is a Q-bit thermometer code.

[0068] In summary, the time domain multi-channel true convolution circuit based on SRAM storage and calculation proposed in the embodiment of the present invention realizes high reliability and high energy efficiency calculation of multiplication and addition operations in time domain multi-channel convolution. Specifically: the SRAM array is innovatively used to store weight data and sign bit data. In the charging and discharging process of each capacitor of the current steering type multiplier and adder of each channel, the weight data is used to control the magnitude of the current steering current during charging and discharging, and the sign bit data is used to control the direction of the current steering current during charging and discharging. At the same time, the digital signal delay array is used to control the charging and discharging time, so that under the selection control of the sign bit data, the weight data and the time mode signal / time mode delay signal are multiplied to obtain the voltage difference between the two ends of the capacitor before and after charging and discharging of each capacitor in the current steering type multiplier and adder of each channel, and then the charge sharing type adder is used to distribute the charge evenly according to the voltage difference between the two ends of the capacitor before and after charging and discharging of each capacitor, and the addition operation is completed. Finally, the thermometer code pulse is output through the thermometer code analog-to-digital converter. Through the above processing process, the embodiment of the present invention can reduce the power consumption and delay of the multiplication and addition operation in the convolution and improve the operation efficiency of the convolution.

[0069] In the description of the present invention, it should be understood that the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, "plurality" means two or more, unless otherwise clearly and specifically defined.

[0070] Although the present invention is described herein in conjunction with various embodiments, in the process of implementing the claimed invention, those skilled in the art may understand and implement other variations of the disclosed embodiments by viewing the specification and the drawings. In the specification, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude multiple situations. Certain measures are recorded in different embodiments, but this does not mean that these measures cannot be combined to produce good results.

[0071] The above contents are further detailed descriptions of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the protection scope of the present invention.< / m> < / m> < / m> < / m>

Claims

1. A time domain multi-channel true convolution circuit based on SRAM storage and calculation, characterized in that: The time domain multi-channel true convolution circuit comprises: An internal timing generation circuit, used for generating a quantization enable signal, a multiplication-addition operation enable signal and a digital delay enable signal; A digital signal delay array, used to delay the time mode signal for a fixed time according to the digital delay enable signal to generate M-1 time mode delay signals; A current steering type multiplier and adder with N channels, each current steering type multiplier and adder of each channel includes M current steering type multipliers, a charge sharing type adder and an SRAM array; the SRAM array is used to store weight data and sign bit data, the weight data is used to control the size of the current generated by the current steering, and the sign bit data is used to control the direction of the current steering; each current steering type multiplier is used to perform a multiplication operation on the time mode signal / time mode delay signal and the weight data under the selection control of the sign bit data to output the voltage difference between the two ends of the corresponding capacitor after charging and discharging, the time mode signal and M-1 time mode delay signals are used to control the charging and discharging time of the capacitor in the M current steering type multipliers; the charge sharing type adder is used to perform an addition operation on the voltage difference between the two ends of the capacitor output by the M current steering type multipliers under the control of the multiplication and addition operation enable signal to output the corresponding capacitor charge sharing result; The thermometer code analog-to-digital converter is used to perform analog-to-digital conversion on the N capacitor charge sharing results according to the thermometer logic under the control of the quantization enable signal to obtain N thermometer code pulses.

2. The time domain multi-channel true convolution circuit based on SRAM storage and calculation according to claim 1 is characterized in that: The digital signal delay array includes M-1 digital signal delay units connected in sequence.

3. The time domain multi-channel true convolution circuit based on SRAM storage and calculation according to claim 2 is characterized in that: Each digital signal delay unit includes a rising edge detector, a falling edge detector, a transistor MP1, a transistor MP2, a transistor MN1, a transistor MN2, a current source I1, a current source I2, a capacitor C11, a capacitor C12, inverters INV1 to INV3, and an AND gate circuit AND1; wherein, One end of the rising edge detector and one end of the falling edge detector are connected and serve as the input end of the digital signal delay unit, the other end of the rising edge detector is connected to the gate of the transistor MP1 and the gate of the transistor MN1, the drain of the transistor MP1 is connected to the drain of the transistor MN1, one end of the capacitor C11, and one end of the inverter INV1, the source of the transistor MN1 is connected to the positive electrode of the current source I1, the other end of the falling edge detector is connected to the gate of the transistor MP2 and the gate of the transistor MN2, the drain of the transistor MP2 is connected to the drain of the transistor MN2, one end of the capacitor C12, and one end of the inverter INV1. One end of NV2 is connected, the source of transistor MN2 is connected to the positive electrode of current source I2, the other end of inverter INV2 is connected to one end of inverter INV3, the other end of inverter INV1 is connected to the first input end of AND gate circuit AND1, the other end of inverter INV3 is connected to the second input end of AND gate circuit AND1, and the output end of AND gate circuit AND1 serves as the output end of digital signal delay unit; the source of transistor MP1 and the source of transistor MP2 are both connected to power supply VDD, the negative electrode of current source I1, the negative electrode of current source I2, the other end of capacitor C11 and the other end of capacitor C12 are all grounded.

4. The time domain multi-channel true convolution circuit based on SRAM storage and calculation according to claim 1, characterized in that: The structure of each current steering type multiplier is the same; the mth current steering type multiplier includes a first group of current steering structures and a second group of current steering structures, the first group of current steering structures and the second group of current steering structures respectively include P-chip parallel current steering sub-structures, and m is 1 to M; wherein the operation of the first group of current steering structures or the second group of current steering structures is determined by the sign bit data.

5. The time domain multi-channel true convolution circuit based on SRAM storage and calculation according to claim 4 is characterized in that: Each current steering substructure of the first group of current steering structures in the mth current steering type multiplier includes an AND gate circuit AND2, a switch SW11, a transistor MN3 and a current source I3; wherein, A first input end of the AND gate circuit AND2 is connected to the SRAM array, a second input end of the AND gate circuit AND2 is connected to the digital signal delay array, an output end of the AND gate circuit AND2 is connected to the control end of the switch SW11, a data input end of the switch SW11 is connected to the SRAM array, an output end of the switch SW11 is connected to the gate of the transistor MN3, a source of the transistor MN3 is connected to the positive electrode of the current source I3, a drain of the transistor MN3 serves as the output end of the mth current steering multiplier, and a negative electrode of the current source I3 is grounded.

6. The time domain multi-channel true convolution circuit based on SRAM storage and calculation according to claim 5, characterized in that: Each current steering substructure of the second group of current steering structures in the mth current steering type multiplier includes an AND gate circuit AND3, a switch SW12, a transistor MP3, a current source I4, an inverter INV4 and an inverter INV5; wherein, One end of the inverter INV4 is connected to the SRAM array, the other end of the inverter INV4 is connected to the first input end of the AND gate circuit AND3, the second input end of the AND gate circuit AND3 is connected to the digital signal delay array, the output end of the AND gate circuit AND3 is connected to the control end of the switch SW12, the data input end of the switch SW12 is connected to one end of the inverter INV5, the other end of the inverter INV5 is connected to the SRAM array, the output end of the switch SW12 is connected to the gate of the transistor MP3, the source of the transistor MP3 is connected to the positive electrode of the current source I4, the drain of the transistor MP3 is connected to the drain of the transistor MN3, and the negative electrode of the current source I4 is grounded.

7. The time domain multi-channel true convolution circuit based on SRAM storage and calculation according to claim 4, characterized in that: The charge sharing adder includes capacitors C1 to C M , switch SW1 to switch SW M-1 ;in, Switch SW1 to switch SW M-1 Connect in sequence, switch SW m1 The data input terminal and capacitor C m1 The output terminal of the m1th current steering multiplier is connected to the capacitor C m1 The other end of the switch is grounded, m1 is 1 to M-1, and the switch SW M-1 The output terminal and capacitor C M The output terminal of the Mth current steering multiplier is connected to the switch SW M-1 The output end of the charge sharing adder is used as the output end of the capacitor C M The other end of the switch SW1 to the switch SW M-1 The control ends are all connected to the internal timing generation circuit.

8. The time domain multi-channel true convolution circuit based on SRAM storage and calculation according to claim 4, characterized in that: The time domain multi-channel true convolution circuit also includes: The internal timing generation circuit is also used to generate a capacitor voltage reset signal; Each current steering type multiplier and adder also includes a capacitor voltage reset circuit; the capacitor voltage reset circuit is used to pre-charge the capacitor in the corresponding current steering type multiplier under the control of the capacitor voltage reset signal.

9. The time domain multi-channel true convolution circuit based on SRAM storage and calculation according to claim 8, characterized in that: The capacitor voltage reset circuit includes switches SW'1 to SW' M ; Switch SW'1~Switch SW' M The control ends of the switches SW' are connected to the internal timing generation circuit. m The data input terminal of is connected to the output terminal of the mth current steering multiplier, and the switch SW'1 to the switch SW' M The output ends are connected to the pre-charge source VDD1.

10. The time domain multi-channel true convolution circuit based on SRAM storage and calculation according to claim 1, characterized in that: The time domain multi-channel true convolution circuit also includes: The internal timing generation circuit is also used to generate a signal generation enable signal; A triangular wave generating circuit, used for generating a triangular wave signal under the control of the signal generation enabling signal; The time domain modulation circuit is used to modulate the voltage type input signal using the triangle wave signal to generate the time mode signal.

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