Binary translation method and device, electronic equipment and readable storage medium

Abstract

The embodiment of the invention provides a binary translation method and device, electronic equipment and a readable storage medium, and the method comprises the steps: obtaining a dependency relationship between instructions in a target loop body if the target loop body is recognized to exist in a to-be-translated basic block; the obtained dependencies comprise dependencies among the instructions in the same-level iteration and dependencies among the instructions in different-level iterations; if it is recognized that a target instruction group matched with the preset mode exists in the target circulation body, marking is carried out; the instructions in the target instruction group have dependency relationships on the same register, and do not have dependency relationships of other instructions on the register; performing optimization translation on the marked target instruction group; the optimization translation means that the target instruction group is translated into a matched target instruction corresponding to the preset mode, and the instruction number of the target instruction corresponding to the preset mode is smaller than the instruction number in the target instruction group. According to the method, the number of translated instructions can be reduced, and the running efficiency of translated programs is improved.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to a binary translation method, device, electronic device and readable storage medium. Background Art

[0002] Binary translation can convert the binary code of one ISA (Instruction Set Architecture) into the binary code of another ISA. Through binary translation technology, an application of one ISA (source architecture) can be run on another ISA (target architecture).

[0003] During the binary translation process, an instruction under the source architecture may be translated into one or more instructions under the target architecture, which may increase the number of instructions in the translation result and generate a large number of redundant instructions, thereby affecting the running efficiency of the translated program. Summary of the invention

[0004] In view of the above problems, an embodiment of the present invention is proposed to provide a binary translation method that overcomes the above problems or at least partially solves the above problems, which can reduce the number of translated instructions and improve the operating efficiency of the translated program.

[0005] Correspondingly, the embodiment of the present invention also provides a binary translation device, an electronic device, and a computer program product to ensure the implementation and application of the above method.

[0006] In a first aspect, an embodiment of the present invention discloses a binary translation method, the method comprising:

[0007] If it is identified that there is a target loop body in the basic block to be translated, the dependency relationship between instructions in the target loop body is obtained; the dependency relationship obtained includes the dependency relationship between instructions in the same level iteration and the dependency relationship between instructions in different levels iteration;

[0008] If a target instruction group matching a preset pattern is identified in the target loop body, the target instruction group is marked; a target instruction group includes at least two instructions; each instruction in the target instruction group has a dependency relationship on the same register, and no other instructions have a dependency relationship on the register;

[0009] The marked target instruction group is optimized and translated; the optimized translation refers to translating the target instruction group into target instructions corresponding to a matching preset mode, wherein the number of target instructions corresponding to the preset mode is less than the number of instructions in the target instruction group.

[0010] In a second aspect, an embodiment of the present invention discloses a binary translation device, the device comprising:

[0011] A first identification module is used to obtain the dependency relationship between instructions in the target loop body if it is identified that there is a target loop body in the basic block to be translated; the obtained dependency relationship includes the dependency relationship between instructions in the same level iteration and the dependency relationship between instructions in different levels iteration;

[0012] A second identification module is used to mark the target instruction group if it is identified that there is a target instruction group matching a preset pattern in the target loop body; a target instruction group includes at least two instructions; there is a dependency relationship between the instructions in the target instruction group on the same register, and no other instructions have a dependency relationship on the register;

[0013] The optimized translation module is used to optimize the translation of the marked target instruction group; the optimized translation refers to translating the target instruction group into target instructions corresponding to a matching preset mode, and the number of instructions of the target instructions corresponding to the preset mode is less than the number of instructions in the target instruction group.

[0014] In the third aspect, an embodiment of the present invention discloses an electronic device, comprising: a processor, a memory, a communication interface and a communication bus, wherein the processor, the memory and the communication interface communicate with each other through the communication bus; the memory is used to store at least one executable instruction, and the executable instruction enables the processor to execute the steps of the binary translation method as described in any of the above.

[0015] In a fourth aspect, an embodiment of the present invention discloses a readable storage medium, on which a program or instruction is stored, and when the program or instruction is executed by a processor, the binary translation method as described in any of the above can be implemented.

[0016] In a fifth aspect, an embodiment of the present invention discloses a computer program product, including a computer program, which, when executed by a processor, performs the steps of any of the aforementioned binary translation methods.

[0017] The embodiments of the present invention include the following advantages:

[0018] The binary translation method of the embodiment of the present invention can be applied to a dynamic binary translator. During the binary translation process, loop identification is performed. If it is identified that there is a target loop body in the basic block to be translated, the dependency relationship between the instructions in the target loop body is obtained. Based on the obtained dependency relationship, it is identified whether there is a target instruction group that can be optimized for translation in the target loop body. If so, the target instruction group is marked. The target instruction group contains an optimizable instruction sequence. During the translation process, the marked target instruction group can be optimized for translation; the optimized translation refers to translating the target instruction group into a target instruction corresponding to a matching preset mode, and the number of instructions of the target instruction corresponding to the preset mode is less than the number of instructions in the target instruction group. Thus, multiple source instructions (based on the source platform architecture) in the target loop body can be fused and translated into a smaller number of target instructions (based on the target platform architecture), which can reduce the number of translated instructions and improve the running efficiency of the translated program. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 It is a schematic diagram of a binary translation architecture of the present invention;

[0020] Figure 2 is a flowchart of a binary translation method embodiment of the present invention;

[0021] Figure 3 is a schematic diagram of a flow chart for determining a second preset condition in an example of the present invention;

[0022] Figure 4 It is a schematic diagram of the translation result of adding loop iteration reservation to the target loop body in the present invention;

[0023] Figure 5 This is a schematic diagram of the translation result obtained by adding loop iteration reservation to Example 1 of the present invention;

[0024] Figure 6 is a flowchart of binary translation in an example of the present invention;

[0025] Figure 7 is a structural block diagram of an embodiment of a binary translation device of the present invention;

[0026] Figure 8 It is a schematic diagram of the structure of an electronic device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0027] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0028] The terms "first", "second", etc. in the specification and claims of the present invention are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable when appropriate, so that the embodiments of the present invention can be implemented in an order other than those illustrated or described here, and the objects distinguished by "first", "second", etc. are generally of one type, and the number of objects is not limited. For example, the first object can be one or more. In addition, the term "and / or" in the specification and claims is used to describe the association relationship of associated objects, indicating that three relationships can exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the objects associated before and after are in an "or" relationship. In the embodiments of the present invention, the term "multiple" refers to two or more, and other quantifiers are similar.

[0029] Binary translation technology can solve the problem of binary-level applications running across instruction set architectures. Specifically, binary translation technology can convert instruction sequences in one instruction set architecture into instruction sequences in another instruction set architecture.

[0030] Reference Figure 1 , shows a schematic diagram of a binary translation architecture, which includes a disassembler, an optimizer, a translator, and an assembler. First, the source program is input into the disassembler for disassembly and cutting into basic blocks, and the information of each instruction in each basic block is obtained; the optimizer analyzes the information obtained after disassembly, finds out the possible instruction sequences to be optimized, and marks them; the translator translates each instruction according to the information obtained after disassembly, and performs some optimizations during the translation process with the assistance of the marking information provided by the optimizer; the optimized translated instructions are finally sent to the assembler for assembly. A basic block (Translation Block, TB) usually ends with a control flow changing instruction (such as a jump instruction, a function call instruction, etc.).

[0031] In an embodiment of the present invention, the source platform is also referred to as a client platform, and the target platform is also referred to as a host platform or a local platform. The processor of the source platform may be a processor based on a first instruction set architecture. The processor of the target platform may be a processor based on a second instruction set architecture. The second instruction set architecture is a different instruction set architecture from the first instruction set architecture.

[0032] Binary translation includes static binary translation and dynamic binary translation. Static binary translation is to translate binary program A (source program) on the source platform before it is executed, so as to translate binary program A into binary program B (target program) on the target platform. Dynamic binary translation is to translate the executed code fragments when the binary program is running. The binary translation method of the embodiment of the present invention can be applied to the scenario of dynamic binary translation.

[0033] Reference Figure 2 , shows a flowchart of a binary translation method embodiment of the present invention, the method may include the following steps:

[0034] Step 101: if it is identified that a target loop body exists in the basic block to be translated, then the dependency relationship between instructions in the target loop body is obtained; the dependency relationship obtained includes the dependency relationship between instructions in the same level iteration and the dependency relationship between instructions in different levels iteration;

[0035] Step 102: if a target instruction group matching a preset pattern is identified in the target loop body, the target instruction group is marked; a target instruction group includes at least two instructions; each instruction in the target instruction group has a dependency relationship on the same register, and no other instructions have a dependency relationship on the register;

[0036] Step 103, optimizing and translating the marked target instruction group; the optimized translation refers to translating the target instruction group into target instructions corresponding to a matching preset mode, wherein the number of target instructions corresponding to the preset mode is less than the number of instructions in the target instruction group.

[0037] The binary translation method provided by the embodiment of the present invention can be applied to a dynamic binary translator. The dynamic binary translator may include a translation module and an execution module. The translation module is used to read the binary code of the source program and translate it into a target code; the execution module is used to run these target codes to simulate the execution of the source program. Correspondingly, the running process of the source program is also divided into two parts: a translation phase and a running phase. In the translation phase, the binary code of the source program is translated, and after the translation is completed, the control is transferred to the execution module for execution, entering the execution phase. When the execution module encounters a code fragment that has not yet been translated, the control is returned to the translation module for continued translation.

[0038] The binary translation method of the embodiment of the present invention performs translation based on basic blocks. A basic block generally ends with a control flow changing instruction (such as a jump, a function call, etc.).

[0039] In an embodiment of the present invention, the translation module performs loop identification during the binary translation process. If it is identified that there is a target loop body in the basic block to be translated, the dependency relationship between the instructions in the target loop body is obtained. Based on the obtained dependency relationship, it is identified whether there is a target instruction group that can be optimized for translation in the target loop body. If so, the target instruction group is marked. The target instruction group contains an optimizable instruction sequence. During the translation process, the marked target instruction group can be optimized for translation; the optimized translation refers to translating the target instruction group into a target instruction corresponding to a matching preset mode, and the number of instructions of the target instruction corresponding to the preset mode is less than the number of instructions in the target instruction group, which can also be called fusion translation.

[0040] The purpose of the embodiment of the present invention is to fuse and translate multiple source instructions (instructions based on the source platform architecture) in the target loop body into fewer target instructions (instructions based on the target platform architecture), which can reduce the number of translated instructions. For example, if a certain target loop body needs to be iterated 10 times, each instruction in the target loop body needs to be translated 10 times, and each instruction may be translated into one or more instructions under the target platform architecture. The embodiment of the present invention fuses and translates multiple instructions contained in the target instruction group into fewer target instructions by identifying the target instruction group that can be fused and translated in the target loop body. For example, the target instruction group contains two instructions, which can be optimized and translated into one target instruction. When the number of iterations of the loop is large, the number of translated instructions can be greatly reduced, and the operating efficiency of the translated program can be improved.

[0041] The target loop body refers to a loop body that satisfies the first preset condition. The first preset condition includes: the destination address of the jump instruction in the loop body is within the address range of the loop body. That is, the jump instruction in the loop body cannot jump to the outside of the loop body. If there is a target instruction group that matches the preset mode (i.e., the target instruction group that can be optimized for translation) in the target loop body, the target instruction group can be optimized for translation during binary translation. Among them, a target instruction group includes at least two instructions, and the instruction sequence composed of the at least two instructions matches the instruction sequence corresponding to the preset mode. In addition, at least two instructions contained in a target instruction group should also meet the following conditions: there is a dependency relationship between the instructions in the target instruction group on the same register, and there is no dependency relationship between other instructions on the register. The other instructions refer to instructions in the target loop body other than the instructions contained in the target instruction group. For example, assume that a target loop body includes 9 instructions from instruction 1 to instruction 9. The target loop body includes a target instruction group, which includes instruction 3 and instruction 4. Assuming that instruction 3 and instruction 4 have a dependency on the same register (such as v1), the other instructions refer to instruction 1, instruction 2, and 7 instructions from instruction 5 to instruction 9. If there is no instruction that depends on register v1 among these 7 instructions, the target instruction group can be optimized for translation.

[0042] Example 1: The basic block to be translated includes the following code segment:

[0043] 12006efb0:ld a0,0(v0)

[0044] 12006efb4:ld a1,32(v0)

[0045] 12006efb8:daddio v0,v0,128

[0046] 12006efbc:sltu v1,a0,a1

[0047] 12006efd0:bnez v1,12006efe0

[0048] 12006efd4:nop

[0049] 12006efd8:nor a3,a0,zero

[0050] 12006efdc:and a3,a3,a1

[0051] 12006efe0:sltuv2,v0,a2

[0052] 12006efe4:bnezv2,12006efb0

[0053] The code segment shown in Example 1 contains two sltu instructions and two bnez instructions. The first sltu instruction and the first bnez instruction are recorded as sltu1 and bnez1 respectively, and the second sltu instruction and the second bnez instruction are recorded as sltu2 and bnez2 respectively. Assume that there is a preset mode of "sltu+bnez". The instruction sequence corresponding to the preset mode includes sltu instructions and bnez instructions in order. The sltu instructions and bnez instructions may be adjacent or not. When the translator recognizes sltu1, it will identify whether there is a bnez instruction. At this time, it will be found that there are two bnez instructions, that is, "sltu1+bnez1" matches the preset mode "sltu+bnez", and "sltu1+bnez2" also matches the preset mode "sltu+bnez". For "sltu1+bnez1", since bnez1 and sltu1 have a dependency on the same register (register v1), and no other instructions have a dependency on the register v1, "sltu1+bnez1" can form a target instruction group and the target instruction group can be marked. For "sltu1+bnez2", since bnez2 and sltu1 do not have a dependency on the same register, "sltu1+bnez2" cannot form a target instruction group and cannot be optimized and translated.

[0054] Similarly, it can be recognized that the above code segment also includes the target instruction group "nor+and" and the target instruction group "sltu2+bnez2". That is, the translator can recognize the following three groups of target instruction groups: "sltu1+bnez1", "nor+and" and "sltu2+bnez2", and mark them respectively.

[0055] During the translation process, the translator can optimize the translation of the marked target instruction group. For example, in Example 1, the target instruction corresponding to the preset mode "sltu+bnez" is the blt instruction, then the two instructions in the target instruction group "sltu1+bnez1" can be translated into one target instruction blt. The target instruction corresponding to the preset mode "nor+and" is andn, then the two instructions in the target instruction group "nor+and" can be translated into one target instruction andn. The two instructions in the target instruction group "sltu2+bnez2" can be translated into one target instruction blt. This can reduce the number of translated instructions.

[0056] The embodiment of the present invention identifies the target instruction group contained in the target loop body through pattern matching. There is a dependency relationship on the same register between the instructions in a target instruction group, and there is no dependency relationship on the register by other instructions. Therefore, multiple instructions in the target instruction group can be optimized and translated into target instructions corresponding to a preset mode matching the target instruction group, and the number of instructions of the target instructions corresponding to the preset mode is less than the number of instructions in the target instruction group. Through the optimized translation of the embodiment of the present invention, multiple source instructions can be fused and translated into a smaller number of target instructions, which can reduce the number of translated instructions and improve the operating efficiency of the translated program.

[0057] In an optional embodiment of the present invention, the step of identifying that a target loop body exists in a basic block to be translated may include:

[0058] Step S11, determining whether there is a loop body in the basic block;

[0059] Step S12: If it is determined that there is a loop body in the basic block, determine whether the loop body satisfies a first preset condition; the first preset condition includes: the destination address of the jump instruction in the loop body is within the address range of the loop body;

[0060] Step S13: If it is determined that the loop body satisfies the first preset condition, it is determined that a target loop body exists in the basic block.

[0061] For a basic block to be translated, first, it is possible to determine whether there is a loop body in the basic block according to the jump address corresponding to the last jump instruction in the basic block. Since a TB usually ends with a control flow change instruction (such as a jump instruction, a function call instruction, etc.), if the last instruction of the basic block is a jump instruction, it is possible to determine whether the destination address of the jump instruction is less than the address of the current instruction, that is, to determine whether the jump instruction is a forward jump. If so, it can be determined that there is a loop body in the basic block.

[0062] For example, in the basic block shown in Example 1, the last instruction is a jump instruction (bnez), and the destination address of the jump instruction is 12006efb0, which is smaller than the address of the current instruction 12006efe4. The jump instruction is used to jump to the first instruction in the basic block, so it is a forward jump. It can be determined that there is a loop body in the basic block, and 12006efb0 is considered to be the beginning of the loop body.

[0063] Then, it is determined whether the loop body satisfies a first preset condition; the first preset condition includes: the destination address of the jump instruction in the loop body is within the address range of the loop body.

[0064] Example 1 contains two jump instructions, the destination address of the first jump instruction is 12006efe0, which is within the address range 12006efb0 to 12006efe4 of the loop body shown in Example 1. The destination address of the second jump instruction is 12006efb0, which is also within the address range 12006efb0 to 12006efe4 of the loop body shown in Example 1. Therefore, the jump instruction in the loop body shown in Example 1 will not jump to the outside of the loop body, and the first preset condition is met, which is the target loop body.

[0065] Example 2: The basic block to be translated includes the following code segment:

[0066] 120005c50:daddiu v0,v0,88

[0067] 120005c54:ld a0,0(v0)

[0068] 120005c58:ld a1,32(v0)

[0069] 120005c58:sltu v1,a0,a1

[0070] 120005c5c:bnez v1,120005d10

[0071] 120005c60:nop

[0072] 120005c64:sltu v2,v0,a2

[0073] 120005c68:bnez v2,120005c50

[0074] In the basic block shown in Example 2, the destination address of the last jump instruction is 120005c50, which is less than the address 120005c68 of the current instruction. It can be determined that there is a loop body in the basic block. Next, it is determined whether the loop body meets the first preset condition. Example 2 also contains two jump instructions. The destination address of the first jump instruction is 120005d10. The destination address is not within the address range 120005c50 to 120005c68 of the loop body shown in Example 2, that is, the jump instruction may jump to other locations outside the loop body. Therefore, the loop body shown in Example 2 does not meet the first preset condition and is not the target loop body. The code segment cannot be optimized and translated.

[0075] Example 1 satisfies the first preset condition and is a target loop body, so it can be further determined whether there is a target instruction group matching the preset pattern in the target loop body. In the process of determining the target instruction group, the dependency relationship between instructions needs to be used. Therefore, when the target loop body is identified, the dependency relationship between instructions in the target loop body needs to be obtained.

[0076] In an optional embodiment of the present invention, obtaining the dependency relationship between instructions in the target loop body may include:

[0077] Step S21, analyzing the dependency relationship between the instructions in the target loop body based on the registers that the instructions in the target loop body depend on;

[0078] Step S22, generating a dependency graph with instructions in the target loop body as nodes and dependencies of instructions on the same register as edges;

[0079] Step S23, using a two-dimensional array to save the dependency graph, wherein the lower triangular elements of the two-dimensional array represent the dependency between instructions in the same level of iteration, and the upper triangular elements of the two-dimensional array represent the dependency between instructions in different levels of iteration;

[0080] Step S24: Delete invalid dependencies in the dependency graph.

[0081] The embodiment of the present invention analyzes the dependency relationship between the instructions in the target loop body based on the registers that the instructions in the target loop body depend on, and generates a dependency graph with the instructions as nodes and the dependency relationships as edges. The dependency graph can be saved using a two-dimensional array.

[0082] In the embodiment of the present invention, the dependency relationship between two instructions may include: no dependency, WAW (Write After Write), RAW (Read After Write) and WAR (Write After Read).

[0083] Among them, WAW means that instruction 1 first writes the value to the target register, and instruction 2 then writes the value to the target register. Instruction 1 and instruction 2 form a WAW dependency relationship, or it is called that there is a WAW dependency relationship from instruction 2 to instruction 1. RAW means that instruction 1 first writes the value to the target register, and instruction 2 then reads the value from the target register. Instruction 1 and instruction 2 form a RAW dependency relationship, or it is called that there is a RAW dependency relationship from instruction 2 to instruction 1. WAR means that instruction 1 first reads the value from the target register, and instruction 2 then writes the value to the target register. Instruction 1 and instruction 2 form a WAR dependency relationship, or it is called that there is a WAR dependency relationship from instruction 2 to instruction 1.

[0084] An embodiment of the present invention may generate a dependency graph through a preset algorithm. Exemplarily, the preset algorithm may include the following three steps: a) initializing a two-dimensional array; b) identifying dependencies based on registers (such as register numbers) that each instruction in the target loop body depends on, constructing a dependency graph and saving it using a two-dimensional array; c) deleting invalid dependencies in the dependency graph.

[0085] The embodiment of the present invention uses a two-dimensional array to store dependency relationships. For example, 0 can represent no dependency, 1 represents WAW, 2 represents RAW, and 3 represents WAR. Initializing the two-dimensional array is to set the value of the two-dimensional array to 0.

[0086] In order to quickly generate a dependency graph, in step b), the dependencies between instructions can be determined based on register numbers rather than register values. As a result, invalid dependencies may be added. For example, instruction 1 first writes a value to register 1, instruction 2 then writes a value to register 1, and finally instruction 3 reads a value from register 1. Step b) will add a RAW dependency from instruction 3 to instruction 1, and a RAW dependency from instruction 3 to instruction 2. However, in fact, there is no RAW dependency from instruction 3 to instruction 1, and this dependency is an invalid dependency.

[0087] Example 3: The basic block to be translated includes the following code segment:

[0088] 12006efb8:sltuv1,a2,a3

[0089] 12006efbc:sltuv1,a0,a1

[0090] 12006efd0:bnezv1,12006efb8

[0091] In the code segment shown in Example 3, the first instruction is called instruction 1, the second instruction is called instruction 2, the third instruction is called instruction 3, and register v1 is called register 1. Step b) will add a RAW dependency relationship from instruction 3 to instruction 1, and a RAW dependency relationship from instruction 3 to instruction 2. However, when the above code segments are executed sequentially, the value read in v1 when instruction 3 is running is actually the value written by instruction 2, which has nothing to do with instruction 1. Therefore, the RAW dependency relationship from instruction 3 to instruction 1 added in step b) is an invalid dependency relationship and can be deleted.

[0092] Step c) is used to identify whether there are invalid dependencies in the dependency graph generated in step b), and delete the invalid dependencies.

[0093] In an embodiment of the present invention, a two-dimensional array is used to store a dependency graph. The upper triangle and the lower triangle of the two-dimensional array refer to specific element sets in the two-dimensional array. In an embodiment of the present invention, the upper triangle elements include all elements above the main diagonal. The upper triangle elements satisfy the condition i < j, where i is the row number and j is the column number. The lower triangle elements include all elements below the main diagonal. The lower triangle elements satisfy the condition i > j. Exemplarily, the two-dimensional array is represented by D[][]. The value of the element D[j][k] represents the dependency relationship between instruction k and instruction j after it, and the value of the element D[k][j] represents the dependency relationship between instruction j and instruction k after it. Therefore, the lower triangle elements in the two-dimensional array D[][] can represent the dependency relationships between instructions in the same-level iteration of the target loop body, and the upper triangle elements in the two-dimensional array D[][] can represent the dependency relationships between instructions in different-level iterations of the target loop body.

[0094] In one example, assume that a generated dependency graph is represented by the two-dimensional array shown in Table 1.

[0095] Table 1

[0096] i\j Instruction 1 Instruction 2 Directive 3 Instruction 1 0 WAW WAR Instruction 2 WAW 0 WAR Directive 3 RAW RAW 0

[0097] Assume that in one loop iteration, the order of instruction execution is instruction 1, instruction 2, and instruction 3. Let i represent the row number (in this example, i = 1, 2, 3), and let j represent the column number (in this example, j = 1, 2, 3). In the two-dimensional array, the following three cases can be included:

[0098] Case 1: When i = j, it represents the dependency relationship between two identical instructions. In an embodiment of the present invention, it is considered that there is no dependency relationship between identical instructions. In Table 1, the dependency relationship between instruction 1 and instruction 1 is 0 (no dependency relationship), the dependency relationship between instruction 2 and instruction 2 is 0, and the dependency relationship between instruction 3 and instruction 3 is 0.

[0099] Case 2: When i > j, that is, the lower triangle elements in the dependency graph, it represents the dependency relationship between instructions in the same-level iteration. Taking i = 3 and j = 1 as an example, that is, the lower triangle element D[3][1]. D[3][1] represents the dependency relationship between instruction 1 and instruction 3 after it. That is, after instruction 1 is executed and when it comes to instruction 3, the dependency relationship from instruction 3 to instruction 1. For example, in a certain iteration, instruction 1 first writes a value to register v1, and then instruction 3 reads the value from register v1. Then the value of element D[3][1] is RAW, that is, there is a RAW dependency relationship from instruction 3 to instruction 1.

[0100] Case 3: When i < j, that is, the upper triangular elements in the dependence graph, which represent the dependence relationships between instructions in different-level iterations. Taking i = 1 and j = 3 as an example, that is, the upper triangular element D[1][3]. D[1][3] represents the dependence relationship between instruction 3 and instruction 1 after it. That is, after instruction 3 is executed and when it comes to instruction 1, there is a dependence relationship from instruction 1 to instruction 3. For the upper triangular elements, j is greater than i. Therefore, after instruction j is executed, it is inevitable that instruction i can only be executed in the next iteration, spanning two iterations in between. Therefore, the upper triangular elements can be used to represent the dependence relationships between loop iterations. As shown in Table 1, assume that instruction 3 first reads a value from register v1, and when it comes to instruction 1 in the next iteration, instruction 1 writes a value to register v1. Then there is a WAR dependence relationship from instruction 1 to instruction 3, and the value of element D[1][3] in Table 1 is WAR.

[0101] In Example 1, the finally generated dependence graph (invalid dependence relationships have been removed) is shown in Table 2.

[0102] Table 2

[0103]

[0104]

[0105] In Table 2, both i and j start counting from 0. "None" in Table 2 indicates no dependence, and it can also be represented by 0 or other symbols.

[0106] After identifying that there is a target loop body in the basic block and generating a dependence graph, it can be determined whether there is a target instruction group that matches a preset pattern in the target loop body. If it is identified that there is a target instruction group that matches a preset pattern in the target loop body, then mark the target instruction group; at least two instructions are included in a target instruction group; there is a dependence relationship on the same register between the instructions in the target instruction group, and there is no dependence relationship of other instructions on this register.

[0107] In an alternative embodiment of the present invention, the identifying that there is a target instruction group that matches a preset pattern in the target loop body may include:

[0108] Step S21: Determine whether there is an instruction group that matches a preset pattern in the target loop body through pattern matching;

[0109] Step S22: If it is determined that there is an instruction group that matches a preset pattern in the target loop body, then determine whether there is a dependence relationship on the same register between the instructions in the instruction group;

[0110] Step S23: If it is determined that there is a dependency relationship between the instructions in the instruction group on the same register, determine whether the instruction group satisfies a second preset condition; the second preset condition includes: for the same register that the instructions in the instruction group depend on, no other instructions have a dependency relationship on the register;

[0111] Step S24: If it is determined that the instruction group meets the second preset condition, it is determined that there is a target instruction group matching the preset mode in the target loop body.

[0112] The preset mode is a pre-set instruction sequence (or instruction group) that conforms to specific rules. Specifically, the preset mode can be used to translate the instruction sequence of the source platform architecture into the instruction sequence of the target platform architecture, and the number of instructions contained in the translated instruction sequence is less than that before the translation. The preset mode can be a translation rule. For the target instruction group that conforms to the preset mode, it can be translated according to the rules corresponding to the preset mode, and the semantics before and after the translation are the same.

[0113] For example, the preset mode "sltu+bnez" means that the instruction sequence consisting of the two instructions sltu and bnez can be translated into the one instruction blt; for another example, the preset mode "slt+movz" means that the instruction sequence consisting of the two instructions slt and movz can be translated into the one instruction blt; etc. The embodiment of the present invention does not limit the preset mode.

[0114] For the basic block to be translated, after the translator recognizes the existence of the target loop body, it identifies whether there is an instruction group matching the preset pattern in the target loop body; if it is determined that there is an instruction group matching the preset pattern in the target loop body, it is determined whether there is a dependency relationship on the same register between the instructions in the instruction group; if it is determined that there is a dependency relationship on the same register between the instructions in the instruction group, such as in Example 1, it is identified that the instruction group "sltu1+bnez1" matches the preset pattern "sltu+bnez", and there is a dependency relationship on the same register (v1) between sltu1 and bnez1, then it is further determined whether the instruction group meets the second preset condition; the second preset condition includes: for the same register that each instruction in the instruction group depends on, there is no dependency relationship on the register by other instructions. If it is determined that the instruction group meets the second preset condition, it is determined that the instruction group is a target instruction group that can be optimized for translation and can be marked.

[0115] Furthermore, the embodiment of the present invention can quickly obtain the dependency relationship between instructions based on the constructed dependency graph, and then determine whether there is a dependency relationship on the same register between the instructions in the instruction group.

[0116] For example, in Example 1, the instruction group "sltu1+bnez1" matching the preset mode "sltu+bnez" is identified, and by querying the generated dependency graph (as shown in Table 2), it can be known that there is a dependency relationship between sltu1 and bnez1 on the same register. For example, the value of element D[4][3] in Table 2 is RAW, indicating that there is a RAW dependency relationship between sltu1 and bnez1 in the instruction group "sltu+bnez", and there is a dependency relationship on the same register. Therefore, it can be further determined whether the instruction group "sltu1+bnez1" meets the second preset condition, that is, for the same register that sltu1 and bnez1 depend on, whether there are other instructions that have a dependency relationship on the register. For the instruction group "sltu1+bnez2", although it matches the preset mode "sltu+bnez", by querying the dependency graph shown in Table 2, it can be seen that there is no dependency on the same register between bnez2 and sltu1. Therefore, "sltu1+bnez2" cannot constitute a target instruction group.

[0117] In an optional embodiment of the present invention, the determining whether the instruction group satisfies the second preset condition may include:

[0118] Determine whether the instruction group satisfies condition 1: determine whether the target register has been read before a new value is written between the last instruction in the instruction group and the loop exit of the target loop body; if it has not been read, condition 1 is satisfied; otherwise, condition 1 is not satisfied; the target register is the same register that each instruction in the instruction group depends on;

[0119] Determine whether the instruction group satisfies condition 2: determine whether the target register has been read before a new value is written between the loop entry of the target loop body and the first instruction in the instruction group; if not, condition 2 is satisfied; otherwise, condition 2 is not satisfied;

[0120] Determine whether the instruction group satisfies condition three: determine whether the target register has been operated between the instructions in the instruction group, if not, condition three is satisfied, otherwise condition three is not satisfied;

[0121] If it is determined that the instruction group matching the preset mode satisfies the first, second and third conditions at the same time, it is determined that the instruction group satisfies the second preset condition; otherwise, it is determined that the instruction group does not satisfy the second preset condition.

[0122] In an embodiment of the present invention, the target instruction group in the target loop body can be optimized for translation because each instruction in the target instruction group has the same register that it depends on, and no other instruction depends on the register, so the value of the register can be discarded to achieve fusion translation, that is, a large number of source instruction sequences are optimized for translation into a small number of target instruction sequences. However, for the same register that each instruction in the target instruction group depends on, if there are other instructions that also depend on the register, then the optimized translation cannot be achieved by discarding the value of the register, otherwise it may cause other instructions that depend on the register to execute errors. Therefore, the target instruction group marked in the embodiment of the present invention should meet the second preset condition.

[0123] Example 4: The basic block to be translated includes the following code segment:

[0124] 12000401c:sdv1,100(v0)

[0125] 120004020:sdzero,104(v0)

[0126] 120004024:daddiov0,v0,120

[0127] 120004028:sltuv1,v0,a0

[0128] 12000402c:bnez v1,12000401c

[0129] In Example 4, the basic block can be identified as the target loop body, and the instruction group "sltu+bnez" matching the preset pattern can be identified. There is a dependency relationship between the sltu instruction and the bnez instruction on the same register (v1). If the second preset condition is not considered, the sltu instruction and the bnez instruction in Example 4 are marked as the target instruction group and optimized during translation, and the following translation results can be obtained:

[0130] 0xffef13c3bcst.d $r18,$r17,72(0x64)

[0131] 0xffef13c3c0st.d $r0,$r17,104(0x68)

[0132] 0xffef13c3c4addi.d$r17,$r17,120(0x78)

[0133] 0xffef13c3ccblt$r17,$r4,-12#0xffef13c3bc

[0134] In Example 4, if the second preset condition is not considered, the sltu instruction and the bnez instruction are translated into a blt instruction. In Example 4, there is a dependency relationship between the sltu instruction and the bnez instruction on the same register (v1), but the first sd instruction also depends on the register (v1), and the instruction group composed of the sltu instruction and the bnez instruction does not meet the second preset condition. In this case, the instruction group "sltu+bnez" is still optimized and translated. In the above translation result, register R17 corresponds to register V0 before translation, register R4 corresponds to register A0 before translation, and register R18 corresponds to register V1 before translation. It can be seen that register R18 is not used in the blt instruction obtained after the optimized translation. This is because the blt instruction can jump directly by comparing the values ​​of registers R17 and R4, and there is no need to save the intermediate result (i.e., the value of v1). Therefore, the value of register V1 after the optimized translation is discarded during the optimization process.

[0135] In Example 4, the sd instruction at address 12000401c needs to use the value of register v1, so the value of v1 generated in the first iteration will be used by the sd instruction in the second iteration. After the optimized translation, the value of register v1 is discarded, and the blt instruction does not save the value of register r18 (corresponding to v1). Then, in the second iteration, the value of r18 read by the first st.d instruction will be an incorrect value. Therefore, to ensure the correctness of instruction execution, the sltu instruction and bnez instruction in Example 4 should not be used as the target instruction group for optimized translation.

[0136] In an embodiment of the present invention, the marked target instruction group should meet the second preset condition to ensure that the value of the register discarded during the optimization translation process is not relied on by other instructions, that is, the value of the discarded register is not used in the subsequent execution process.

[0137] The second preset condition may specifically include three conditions: condition one, condition two and condition three. For an instruction group that matches the preset mode, if condition one, condition two and condition three are met at the same time, it can be determined that the instruction group meets the second preset condition and can be optimized and translated as a target instruction group; otherwise, it is determined that the instruction group does not meet the second preset condition and cannot be optimized and translated as a target instruction group.

[0138] For ease of description, the same register that each register in the instruction group that matches the preset pattern depends on is called a discarded value register (or target register), because subsequent optimized translation will achieve fusion translation by discarding the value of this register to reduce the number of translated instructions.

[0139] Among them, condition 1 is used to determine whether there are other instructions in the same level iteration that have dependencies on the discard value register. Specifically, it can be determined whether the discard value register has been read before the new value is written between the last instruction in the instruction group (such as instruction b) and the loop exit of the target loop body. If it has not been read, condition 1 is met, otherwise condition 1 is not met.

[0140] Condition 2 is used to determine whether there is a dependency relationship between other instructions on the discarded value register between different levels of iteration. Specifically, it can be determined whether the target register has been read before the new value is written between the loop entry of the target loop body and the first instruction in the instruction group (such as instruction a). If it has not been read, condition 2 is satisfied, otherwise condition 2 is not satisfied.

[0141] Condition 3 is used to determine whether there is a dependency relationship between other instructions in the instruction group on the discard value register. Specifically, it can be determined whether the target register has been operated between the instructions in the instruction group. If it has not been operated, condition 3 is satisfied, otherwise condition 3 is not satisfied. The operation includes reading or writing.

[0142] Furthermore, conditions 1, 2, and 3 can all be quickly judged through the dependency graph generated in the above steps. Specifically, the dependency graph can be traversed to determine whether there is a RAW dependency from D[b+1][b] to D[max][b] in the dependency graph. If not, condition 1 is satisfied, otherwise condition 1 is not satisfied; during the traversal, determine whether there is a RAW dependency from D[0][a] to D[a-1][a] in the dependency graph. If not, condition 2 is satisfied, otherwise condition 2 is not satisfied; during the traversal, determine whether there is a RAW dependency from D[a+1][a] to D[b-1][a] or a WAW dependency from D[a+1][a] to D[b-1][a] in the dependency graph. If neither of these two dependencies exists, condition 3 is satisfied, otherwise condition 3 is not satisfied.

[0143] In Example 1, the instruction groups that can be identified to match the preset mode include: "sltu1+bnez1", "nor+and" and "sltu2+bnez2".

[0144] For the instruction group "sltu1+bnez1", determine whether condition 1 is satisfied. The instructions in the instruction group "sltu1+bnez1" have a dependency on the same register (v1), that is, the discarded value register is v1. The dependency graph (as shown in Table 2) can be traversed, specifically the lower triangular elements of the dependency graph, and it is found that except for instruction 4 (bnez1), there is no other instruction that has a dependency on v1, so condition 1 is satisfied.

[0145] For the instruction group "sltu1+bnez1", it is determined whether condition 2 is satisfied. The dependency graph (as shown in Table 2) can be traversed, specifically the upper triangular elements of the dependency graph can be traversed, and it is found that there is no RAW dependency, so condition 2 is satisfied.

[0146] For the instruction group "sltu1+bnez1", determine whether condition three is met. Since the two instructions sltu1 and bnez1 are adjacent and there are no other instructions between them, condition three is met. It should be noted that if the instructions in the instruction group are not adjacent, the dependency graph can be traversed, specifically the lower triangular elements of the dependency graph. Assuming that the instruction group includes instructions a and b, determine whether there is a RAW dependency from D[a+1][a] to D[b-1][a] or a WAW dependency from D[a+1][a] to D[b-1][a] to determine whether condition three is met.

[0147] For the instruction groups "nor+and" and "sltu2+bnez2", according to the above method, it can be determined that the instruction groups "nor+and" and "sltu2+bnez2" both meet the second preset condition. Therefore, these three instruction groups can be marked as target instruction groups and optimized during translation.

[0148] It should be noted that if there are instruction groups that do not meet the second preset condition, optimized translation can be performed only on the instruction groups that meet the second preset condition, while ordinary translation can be performed on the instruction groups that do not meet the second preset condition, and the translation methods between the instruction groups do not affect each other.

[0149] In a specific implementation, the second preset condition can be determined and the target instruction group can be marked in the following two ways:

[0150] Method 1: After identifying that there is an instruction group matching the preset pattern in the target loop body and determining that there is a dependency relationship on the same register between the instructions in the instruction group, it can be further determined whether the instruction group meets the second preset condition. If so, the instruction group is marked as the target instruction group; if not, it is not marked.

[0151] In the second method, when it is identified that there is an instruction group matching the preset pattern in the target loop body, and it is determined that there is a dependency relationship between the instructions in the instruction group on the same register, the instruction group is marked as the target instruction group, which is called preliminary marking. After all the target instruction groups in the target loop body are preliminarily marked, it is determined one by one whether each of the preliminarily marked target instruction groups meets the second preset condition, and the target instruction groups that do not meet the second preset condition are removed from the mark.

[0152] Reference Figure 3 , shows a schematic diagram of a flow chart for determining the second preset condition in an example. Figure 3 As shown, judging whether each group of target instruction groups preliminarily marked meets the second preset condition may specifically include the following steps:

[0153] A1: Obtain a group of target instruction groups that have been marked but have not been judged for the second preset condition, and determine a target register, where the target register is a discarded value register of the target instruction group in the case of optimized translation;

[0154] A2: Determine whether the instructions in the target instruction group are adjacent. If so, execute step A3; if not, execute step A6;

[0155] A3: Determine whether the target instruction group satisfies condition 1 based on the target register; if condition 1 is satisfied, execute step A4; if condition 1 is not satisfied, execute step A7;

[0156] A4: Determine whether the target instruction group satisfies condition 2 based on the target register; if condition 2 is satisfied, execute step A5; if condition 2 is not satisfied, execute step A7;

[0157] A5: retain the mark of the target instruction group;

[0158] A6: Determine whether the target instruction group satisfies condition three based on the target register; if condition three is satisfied, execute step A3; if condition three is not satisfied, execute step A7;

[0159] A7: Remove the mark of the target instruction group.

[0160] The embodiment of the present invention does not limit the way in which target instruction groups that can be optimized for translation are marked. A target loop body may include one or more target instruction groups, and the instructions in the same target instruction group may be adjacent or non-adjacent. During the translation process, each instruction to be translated can be stored in a data structure, and a flag bit can be added to the data structure to indicate whether the instruction is an instruction that can be optimized for translation in a certain target instruction group. Exemplarily, the flag bit is initially a default value, such as the default value of -1, indicating that the instruction cannot be optimized for translation and can only be translated normally. If the flag bit of a certain instruction is set to n, it means that the instruction is an instruction that can be optimized for translation in the target instruction group n. n is a positive integer.

[0161] In one example, for a certain target loop body, it is assumed that it is identified to contain two groups of target instruction groups, respectively referred to as target instruction group 1 and target instruction group 2. The flag bit of each instruction in target instruction group 1 can be set to 1, and the flag bit of each instruction in target instruction group 2 can be set to 2. Therefore, during translation, if the flag bit of a certain instruction to be translated is identified as 1, it can be determined that the instruction is an instruction in target instruction group 1, and the optimized translation can be performed according to the preset mode corresponding to target instruction group 1; if the flag bit of a certain instruction to be translated is identified as 2, it can be determined that the instruction is an instruction in target instruction group 2, and the optimized translation can be performed according to the preset mode corresponding to target instruction group 2; if the flag bit of a certain instruction to be translated is identified as -1, it can be determined that the instruction cannot be optimized for translation.

[0162] During the translation process, for each instruction in the marked target instruction group, all instructions except the last instruction are skipped and not translated. When the last instruction is translated, it is translated into a target instruction corresponding to a preset mode matching the target instruction group.

[0163] Exemplarily, the steps for optimizing the translation of a marked target instruction group in an embodiment of the present invention may be as follows: read an instruction to be translated; determine whether the instruction is marked, and if the instruction is marked, determine whether the instruction is the last instruction in the target instruction group; if the instruction is the last instruction in the target instruction group, translate it into a target instruction corresponding to a preset mode matching the target instruction group, and read the next instruction to be translated; if the instruction is not the last instruction in the target instruction group, skip the instruction, that is, do not translate the instruction, and read the next instruction to be translated; if the instruction is not marked, perform a normal translation on the instruction, and read the next instruction to be translated.

[0164] In an optional embodiment of the present invention, the target loop body includes N iterations, and the optimizing translation of the marked target instruction group may include:

[0165] According to loop-related information of the target loop body, in the first N-1 iterations of the target loop body, the marked target instruction group is optimized translated, and in the Nth iteration of the target loop body, the marked target instruction group is normally translated; the loop-related information includes loop boundaries, loop increments and loop steps.

[0166] In a specific implementation, the target instruction group is optimized and translated, and multiple source instructions can be translated into fewer target instructions. In this process, the value of the same register that each instruction in the target instruction group depends on will be discarded. For example, in Example 1, the discarded value register is v1. If the value of v1 will not be used in subsequent execution, the optimized translation discarding the value of v1 will not affect the correctness of subsequent instruction execution. If the value of v1 will still be used in subsequent execution, the optimized translation discarding the value of v1 may affect the correctness of subsequent instruction execution.

[0167] To ensure the correctness of the execution of the translated instructions, the embodiment of the present invention can increase the loop iteration reservation to maintain the discard value register at the end of the loop to ensure the correctness of the subsequent instruction execution.

[0168] The embodiment of the present invention modifies the loop code at the assembly level and maintains the discard value register. Specifically, for a target loop body including N iterations, in the first N-1 iterations, the marked target instruction group is optimized and translated, and in the last iteration (the Nth iteration), the marked target instruction group is translated normally, and the discard value register is maintained in the last iteration of the loop by means of loop iteration reservation to ensure the correctness of subsequent instruction execution.

[0169] Loop iteration reservation can be performed based on loop related information of the target loop body. Therefore, before performing loop iteration reservation on the target loop body, the embodiment of the present invention obtains loop related information of the target loop body, where the loop related information includes loop boundary, loop increment and loop step.

[0170] In an optional embodiment of the present invention, the method may further include:

[0171] Step S31, starting from the loop exit of the target loop body, performing a reverse depth-first search based on the target dependency relationship to identify loop-related instructions in the target loop body; the target dependency relationship means that the previous instruction performs a write operation on a register, and the next instruction performs a read operation on the register;

[0172] Step S32: Obtain loop-related information of the target loop body based on the identified loop-related instructions.

[0173] The embodiment of the present invention takes the loop exit of the target loop body as the starting point, and performs a reverse depth-first search based on the target dependency (write-after-read dependency). Based on the write-after-read dependency, the value transfer relationship of the instructions in the instruction stream can be obtained. Therefore, the loop-related instructions in the target loop body can be reversed in the process of the depth-first search. The loop exit refers to the instruction to jump out of the loop. In a loop body, the operation performed in each iteration is the same, and only one iteration needs to be traversed to obtain loop-related information. Therefore, the depth-first search only needs to search the lower triangular elements in the dependency graph.

[0174] Example 5: The basic block to be translated includes the following code segment:

[0175] 120004020:sdzero,104(v0)

[0176] 120004024:daddiuv0,v0,120

[0177] 120004028:sltuv1,v0,a0

[0178] 12000402c:bnezv1,120004020

[0179] Depth-first search means that for a certain instruction, the dependency graph is first searched for the first register that the instruction depends on, and the dependency relationship between the instruction and other instructions on the first register is found. After the search of the first register is completed, the dependency graph is searched for the second register that the instruction depends on, and the dependency relationship between the instruction and other instructions on the second register is found, and so on.

[0180] Take the sltu instruction in Example 5 as an example. The sltu instruction needs to read registers v0 and a0. According to the read-after-write dependency, a reverse depth-first search is performed, which means that all instructions related to register v0 are searched first, and then all instructions related to register a0 are searched.

[0181] Specifically, in Example 5, the bnez instruction is the loop exit. With this instruction as the starting point, a reverse depth-first search is performed based on the write-after-read dependency. The bnez instruction write-after-read depends on the sltu instruction, and the sltu instruction write-after-read depends on the daddiu instruction. Through the write-after-read dependency, the value transfer relationship of the instructions in the instruction stream can be obtained. The bnez instruction determines whether to jump based on the value of register v1. If the value of v1 is 1, it jumps (executes 120004030), and if the value of v1 is 0, it executes sequentially (executes 120004020). The value of v1 is obtained according to the sltu instruction. The sltu instruction sets the value of register v1 by comparing the value of register v0 with the value of register a0. If the value of v0 is less than the value of a0, the value of v1 is set to 1, otherwise the value of v1 is set to 0. The value of v0 depends on the daddiu instruction. The daddiu instruction increases the value of v0 by 120 in each iteration. The value of a0 does not depend on other instructions, so the value of a0 does not change during runtime. That is, at runtime, the value of v0 continues to increase, while the value of a0 remains unchanged, causing the value of v0 to be less than the value of a0 in the first few iterations, and the loop will not be jumped out. However, as the value of v0 increases, the value of v0 will eventually be greater than or equal to the value of a0, at which point the value of v1 will be set to 1, thereby jumping out of the loop.

[0182] In Example 5, through depth-first search, the following loop-related instructions can be identified: sltu instruction and daddiu instruction.

[0183] Next, it is determined whether the identified loop-related instructions contain loop-related information such as loop boundaries, loop increments, and loop step lengths. If so, the loop-related information is obtained for use in the subsequent loop iteration reservation. The loop boundary refers to the condition for the end of the loop. When the loop boundary is met, the loop ends. The loop boundary can be a fixed value, or a variable or expression. For example, the loop boundary can be the number of loop iterations, reaching a certain value, or satisfying a certain condition. The loop increment refers to the variable defined in the loop statement, which is used to control the number of executions of the loop body and the value of the variable. The loop increment is actually a special counter used to control the number of executions of the loop statement. Its value can be a value within a specific range, or it can be an increase or decrease of a certain value. The loop step length refers to the change in the loop increment at each loop iteration, which determines the number of executions of the loop and the value range of the loop increment. The loop step length can be any integer value, which can be a positive number, a negative number, or zero, and can be used to control the increase or decrease of the loop increment, thereby achieving the purpose of the loop.

[0184] In Example 5, it is recognized that the value of register a0 is unchanged, so the value of register a0 is the loop boundary. The value of register v0 is constantly increasing, so the value of register v0 is the loop increment. Since the value of register v0 is increased by 120 each time, it can be determined that the loop step is 120. It can be understood that in actual applications, the loop increment can also be constantly decreasing.

[0185] In Example 1, the loop exit (the instruction that jumps out of the loop) is the bnez2 instruction, so starting from this instruction, a reverse depth-first search is performed on the dependency graph according to the RAW dependency. As shown in Table 2, the first RAW dependency is first searched for the value of element D[9][8]. D[9][8] indicates that there is a RAW dependency between instruction 8 and instruction 9. The loop-related instruction obtained is instruction 8. Instruction 8 is parsed. Instruction 8 depends on registers v0 and a2. For v0, it is parsed that the value of v0 depends on the daddiu instruction, and the value of v0 keeps increasing. For a2, it is parsed that no instruction depends on a2, and the value of a2 remains unchanged. Therefore, it can be determined that the value of a2 is the loop boundary and the value of v0 is the loop increment. The next RAW dependency is the value of element D[8][2], which is the depth-first search. D[8][2] indicates that there is a RAW dependency between instruction 2 and instruction 8. The loop-related instruction is instruction 2, which is parsed. It is found that instruction 2 increases the value of v0 by 128, which further indicates that the loop increment is stored in v0 and the loop step is 128. This way, loop-related information such as loop boundary, loop increment, and loop step is obtained.

[0186] In an optional embodiment of the present invention, in the first N-1 iterations of the target loop body, performing optimized translation on the marked target instruction group, and in the Nth iteration of the target loop body, performing non-optimized translation on the marked target instruction group, may include:

[0187] Performing a first translation on the target loop body to obtain a first translation code block; the first translation refers to performing an optimized translation on the target instruction group marked in the target loop body, and performing a normal translation on other instructions;

[0188] Performing a second translation on the target loop body to obtain a second translation code block; the second translation refers to performing a common translation on all instructions in the target loop body; the first instruction in the second translation code block is a newly added instruction, which is used to restore the loop boundary;

[0189] Generate an entry code block; the entry code block is used to modify the loop boundary of the target loop body according to the loop step, and control the first N-1 iterations of the target loop body to jump to the entry of the first translation code block according to the loop increment and the modified loop boundary, and control the Nth iteration to jump to the entry of the second translation code block.

[0190] In order to avoid the problem that after the target instruction group in the target loop body is optimized and translated, the register values ​​discarded by the optimized translation will be used in the subsequent instruction execution, resulting in instruction execution errors, the embodiment of the present invention performs loop iteration reservation during the optimized translation, and in the first N-1 iterations of the target loop body, the marked target instruction group is optimized and translated, and in the Nth iteration of the target loop body, the marked target instruction group is non-optimized (i.e., ordinary translation) is performed, so as to restore the register values ​​discarded by the optimized translation in the first N-1 iterations in the last iteration, thereby ensuring that the subsequent instructions are executed correctly.

[0191] Reference Figure 4 , which shows a schematic diagram of the translation result of adding loop iteration reservation to the target loop body according to an embodiment of the present invention. Figure 4 The translation result shown includes three parts: an entry code block, a first translation code block and a second translation code block. Among them, the entry code block is used to reduce loop boundaries and control jumps according to conditions. The first translation code block is an optimized translated code body obtained by optimizing the translation of the target loop body. Specifically, the first translation code block contains the target instruction group marked in the target loop body for optimized translation, and the target instructions obtained by ordinary translation of other unmarked instructions in the target loop body. The first translation code block is used to execute the optimized translated code body, and jump back during the first N-1 iterations, and jump to the second translation code block during the Nth iteration. The second translation code block is a normal translated code body obtained by ordinary translation of the target loop body. Specifically, the second translation code block contains the target instructions obtained by ordinary translation of all instructions in the target loop body. The first target instruction in the second translation code block is a newly added instruction, which is used to restore the loop boundary. The second translation code block is used to execute the normal translated code body, maintain the discarded value register, and jump out of the loop.

[0192] Taking Example 1 as an example, for the first iteration, the source instructions in Example 1 are translated one by one. Instructions 0, 1, and 2 are all unmarked, and ordinary translation is performed in sequence. When translating to instruction 3 (sltu1 instruction), since instruction 3 and instruction 4 (bnez1 instruction) are marked as target instruction groups, the target instruction group composed of instruction 3 and instruction 4 is optimized and translated into a blt instruction. Continue to translate the next instruction. Instruction 5 is a nop instruction (empty instruction). Empty instructions are not translated. Continue to translate the next instruction. Instruction 6 (nor instruction) and instruction 7 (and instruction) are marked as target instruction groups and optimized and translated into an andn instruction. Continue to translate the next instruction. Instruction 8 (sltu2 instruction) and instruction 9 (bnez2 instruction) are marked as target instruction groups and optimized and translated into a blt instruction. The translation of the first iteration is thus completed, and the translation result of the first iteration (the first translation code block) is obtained as follows:

[0193] 0xffef126044ld.d$r4,$r17,0(0x0)

[0194] 0xffef126048ld.d$r5,$r17,32(0x20)

[0195] 0xffef12604caddi.d$r17,$r17,128(0x80)

[0196] 0xffef126050blt$r4,$r5,8#0xffef126058

[0197] 0xffef126054andn$r7,$r5,$r4

[0198] 0xffef126058blt$r17,$r6 -16#0xffef126044

[0199] Assuming that the number of iterations N of the loop body of Example 1 is 3, the translation results of the first iteration and the second iteration are the same, as shown above. In the last iteration (such as the third iteration), all instructions in the target loop body are translated normally, and the translation result of the last iteration (the second translation code block) is as follows:

[0200] 0xffef12605caddi.d$r6,$r6,128(0x80)

[0201] 0xffef126060ld.d$r4,$r17,0(0x0)

[0202] 0xffef126064ld.d$r5,$r17,32(0x20)

[0203] 0xffef126068addi.d$r17,$r17,128(0x80)

[0204] 0xffef12606c sltu$r18,$r4,$r5

[0205] 0xffef126070bne$r18,$r0,12#0xffef12607c

[0206] 0xffef126074nor$r7,$r4,$r0

[0207] 0xffef126078and$r7,$r7,$r5

[0208] 0xffef12607c sltu$r19,$r7,$r6

[0209] 0xffef126080bne$r19,$r0,-32#0xffef126060

[0210] In the translation result of the last iteration, the first instruction is a newly added instruction for restoring the loop boundary, and the following are translation results obtained by performing ordinary translation on the source instructions one by one. The embodiment of the present invention realizes optimized translation of the first N-1 iterations of the target loop body by modifying the loop boundary, and realizes ordinary translation of the Nth iteration by restoring the loop boundary.

[0211] Specifically, an embodiment of the present invention generates an entry code block when translating a target loop body; the entry code block is used to modify the loop boundary of the target loop body so that the first N-1 iterations of the target loop body jump to the entry of the first translation code block, and the Nth iteration jumps to the entry of the second translation code block.

[0212] The entry code block is used to modify loop boundaries and control jumps. The modification of loop boundaries refers to reducing the loop boundaries of the target loop body by one loop step. The control jump refers to judging whether to jump to the entry execution of the first translation code block or to jump to the entry execution of the second translation code block according to the loop increment and the modified loop boundary.

[0213] Taking Example 1 as an example, the following entry code block can be generated:

[0214] 0xffef12603csubi.d$r6,$r6,128(0x80)

[0215] 0xffef126040blt$r6,$r17,24#0xffef12605c

[0216] The entry code block includes two new instructions. The first instruction is used to modify the loop boundary, reducing the original loop boundary (such as the value of register a2) by a loop step (such as 128); the second instruction is used to control the jump, that is, to determine whether to jump to the entry (0xffef126044) of the first translation code block or to jump to the entry (0xffef12605c) of the second translation code block according to the loop increment and the modified loop boundary.

[0217] Reference Figure 5 , shows a schematic diagram of the translation result obtained by adding loop iteration reservation to Example 1 of the present invention. Figure 5 The translation result shown includes the following three parts: an entry code block, a first translation code block, a second translation code block and an entry code block. Among them, the entry code block contains two target instructions newly added according to the loop-related information of the target loop body, which are used to modify the loop boundary and control jumps. The first translation code block contains the target instructions obtained by optimizing the translation of the target instruction group marked in the target loop body and performing ordinary translation on other instructions in the target loop body. The second translation code block contains the target instructions obtained by performing ordinary translation on all instructions in the target loop body, and the first target instruction in the second translation code block is a newly added instruction, which is used to restore the loop boundary.

[0218] Reference Figure 6 , shows a schematic diagram of a binary translation process in an example of the present invention, including the following steps:

[0219] B1: Get the basic block to be translated;

[0220] B2: Perform loop identification on the basic block to be translated. If the target loop body exists, execute step B4; if the target loop body does not exist, execute step B8;

[0221] The target loop body meets the following two conditions: first, it meets the loop, that is, the last jump instruction of the basic block is a forward jump; second, it meets the first preset condition, that is, the jump instruction inside the loop body cannot jump outside the loop body. Generate a dependency graph for the target loop body.

[0222] B3: Count the target instruction groups in the target loop body and mark them;

[0223] The instruction sequence in the target instruction group matches the instruction sequence corresponding to the preset mode. The instructions in a target instruction group may be adjacent or non-adjacent.

[0224] B4: Determine whether the marked target instruction group meets the second preset condition, and remove the mark of the target instruction group that does not meet the second preset condition;

[0225] When the target instruction group satisfies the first condition, the second condition and the third condition at the same time, the target instruction group satisfies the second preset condition; otherwise, the target instruction group does not satisfy the second preset condition.

[0226] B5: Does the marked target instruction group exist? If yes, execute step B6; if no, execute step B8;

[0227] B6: loop iteration reservation processing;

[0228] Starting from the loop exit, based on the dependency graph, a reverse depth-first search is performed according to the write-after-read dependency to obtain loop-related information of the target loop body, including loop boundaries, loop increments, and loop steps. The loop-related information obtained can be used to reserve loop iterations during the optimization translation process.

[0229] B7: optimize the translation of the basic block;

[0230] For a target loop body of N iterations, in the first N-1 iterations of the target loop body, the marked target instruction group is optimized and translated, and in the Nth iteration of the target loop body, the marked target instruction group is non-optimized and translated.

[0231] B8: Optimization ends;

[0232] B9: perform normal translation on the basic block;

[0233] All instructions in the basic block are translated in sequence.

[0234] B10: The translation of this basic block is completed.

[0235] Furthermore, in a specific implementation, a judgment step may be added to judge whether the discarded value register generated by optimizing and translating the marked target instruction group will be used in subsequent execution. If it is determined that the discarded value register will not be used in subsequent execution, there is no need to increase the loop iteration reservation, that is, the optimization translation is performed for N iterations. If it is determined that the discarded value register will be used in subsequent execution, the loop iteration reservation is increased.

[0236] Furthermore, if it can be determined that the register value discarded during the optimized translation of the marked target instruction group will not be used later, then loop iteration reservation processing does not need to be performed. Exemplarily, a step can be added to determine whether the discarded value register will be used later. For example, for the target instruction group 1 in Example 1, if the optimized translation causes the value of register v1 to be discarded during the optimized translation, then a section of subsequent code can be loaded to determine whether the subsequent code has been read before the value of v1 is overwritten by the new value. If v1 has been read before the new value is written, it means that the subsequent code will use the value of v1; then it is necessary to add loop iteration reservation processing during the optimized translation. If v1 has not been read and then overwritten by the new value, it means that the subsequent code will not use v1, and loop iteration reservation processing does not need to be added. The length of the loaded subsequent code will affect the accuracy of the judgment and the performance of the translator, so a fixed length that balances the two can be set.

[0237] Of course, in a specific implementation, in order to ensure the correctness of subsequent instruction execution, it is possible to not determine whether the discarded value register will be used later, and to add the step of loop iteration reservation processing. The embodiment of the present invention does not limit this.

[0238] In summary, the binary translation method of the embodiment of the present invention can be applied to a dynamic binary translator. During the binary translation process, loop identification is performed. If it is identified that there is a target loop body in the basic block to be translated, the dependency relationship between the instructions in the target loop body is obtained. Based on the obtained dependency relationship, it is identified whether there is a target instruction group that can be optimized for translation in the target loop body. If so, the target instruction group is marked. The target instruction group contains an optimizable instruction sequence. During the translation process, the marked target instruction group can be optimized for translation; the optimized translation refers to translating the target instruction group into a target instruction corresponding to a matching preset mode, and the number of instructions of the target instruction corresponding to the preset mode is less than the number of instructions in the target instruction group. Thus, multiple source instructions (based on the source platform architecture) in the target loop body can be fused and translated into a smaller number of target instructions (based on the target platform architecture), which can reduce the number of translated instructions and improve the running efficiency of the translated program.

[0239] It should be noted that, for the sake of simplicity, the method embodiments are described as a series of action combinations, but those skilled in the art should be aware that the embodiments of the present invention are not limited by the order of the actions described, because according to the embodiments of the present invention, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all preferred embodiments, and the actions involved are not necessarily required by the embodiments of the present invention.

[0240] Reference Figure 7, shows a structural block diagram of a binary translation device embodiment of the present invention, the device may include:

[0241] The first identification module 201 is used to obtain the dependency relationship between instructions in the target loop body if it is identified that there is a target loop body in the basic block to be translated; the obtained dependency relationship includes the dependency relationship between instructions in the same level iteration and the dependency relationship between instructions in different levels iteration;

[0242] The second identification module 202 is used to mark the target instruction group if a target instruction group matching a preset pattern is identified in the target loop body; a target instruction group includes at least two instructions; there is a dependency relationship between the instructions in the target instruction group on the same register, and no other instructions have a dependency relationship on the register;

[0243] The optimized translation module 203 is used to optimize the translation of the marked target instruction group; the optimized translation refers to translating the target instruction group into target instructions corresponding to a matching preset mode, and the number of instructions of the target instructions corresponding to the preset mode is less than the number of instructions in the target instruction group.

[0244] Optionally, the first identification module 201 includes:

[0245] A loop body identification submodule, used to determine whether there is a loop body in the basic block;

[0246] The first condition judgment submodule is used to judge whether the loop body satisfies a first preset condition if it is determined that the loop body exists in the basic block; the first preset condition includes: the destination address of the jump instruction in the loop body is within the address range of the loop body; if it is determined that the loop body satisfies the first preset condition, it is determined that the target loop body exists in the basic block.

[0247] Optionally, the target loop body includes N iterations, and the optimization translation module 203 is specifically used to:

[0248] According to loop-related information of the target loop body, in the first N-1 iterations of the target loop body, the marked target instruction group is optimized translated, and in the Nth iteration of the target loop body, the marked target instruction group is normally translated; the loop-related information includes loop boundaries, loop increments and loop steps.

[0249] Optionally, the optimized translation module 203 includes:

[0250] A first translation submodule is used to perform a first translation on the target loop body to obtain a first translation code block; the first translation refers to optimizing the translation of the target instruction group marked in the target loop body and performing a normal translation on other instructions;

[0251] A second translation submodule is used to perform a second translation on the target loop body to obtain a second translation code block; the second translation refers to a common translation of all instructions in the target loop body; the first instruction in the second translation code block is a newly added instruction, which is used to restore the loop boundary;

[0252] An entry processing submodule is used to generate an entry code block; the entry code block is used to modify the loop boundary of the target loop body according to the loop step, and to control the first N-1 iterations of the target loop body to jump to the entry of the first translation code block according to the loop increment and the modified loop boundary, and to control the Nth iteration to jump to the entry of the second translation code block.

[0253] Optionally, the device further comprises:

[0254] A loop-related information acquisition module is used to take the loop exit of the target loop body as the starting point and perform a reverse depth-first search based on the target dependency relationship to identify the loop-related instructions in the target loop body; the target dependency relationship refers to: the previous instruction performs a write operation on a register, and the next instruction performs a read operation on the register; based on the identified loop-related instructions, the loop-related information of the target loop body is acquired.

[0255] Optionally, the first identification module 201 includes:

[0256] A dependency analysis submodule, used for analyzing the dependency between the instructions in the target loop body based on the registers on which the instructions in the target loop body depend;

[0257] A dependency graph building submodule is used to generate a dependency graph using the instructions in the target loop body as nodes and the dependencies of the instructions on the same register as edges;

[0258] A dependency graph saving submodule, used to save the dependency graph using a two-dimensional array, wherein the lower triangular elements of the two-dimensional array represent the dependency between instructions in the same level of iteration, and the upper triangular elements of the two-dimensional array represent the dependency between instructions in different levels of iteration;

[0259] The invalid deletion submodule is used to delete invalid dependencies in the dependency graph.

[0260] Optionally, the second identification module 202 includes:

[0261] A pattern matching submodule, used for determining whether there is an instruction group matching a preset pattern in the target loop body through pattern matching;

[0262] A dependency judgment submodule, for judging whether there is a dependency relationship on the same register between the instructions in the instruction group if it is determined that there is an instruction group matching the preset pattern in the target loop body;

[0263] A second condition judgment submodule is used to judge whether the instruction group satisfies a second preset condition if it is determined that there is a dependency relationship between the instructions in the instruction group on the same register; the second preset condition includes: for the same register that the instructions in the instruction group depend on, there is no dependency relationship between other instructions on the register;

[0264] The target determination submodule is used to determine whether there is a target instruction group matching a preset mode in the target loop body if it is determined that the instruction group meets the second preset condition.

[0265] Optionally, the second condition judgment submodule includes:

[0266] a condition 1 judgment unit, used to judge whether the target register has been read before the new value is written between the last instruction in the instruction group and the loop exit of the target loop body; if it has not been read, condition 1 is satisfied, otherwise condition 1 is not satisfied; the target register is the same register that each instruction in the instruction group depends on;

[0267] A condition 2 judgment unit is used to judge whether the target register has been read before a new value is written between the loop entry of the target loop body and the first instruction in the instruction group. If it has not been read, condition 2 is satisfied, otherwise condition 2 is not satisfied;

[0268] A condition three judging unit, used for judging whether the target register has been operated between the instructions in the instruction group, if not, the condition three is satisfied, otherwise the condition three is not satisfied;

[0269] The second condition judgment unit is used to determine that the instruction group matching the preset mode satisfies the second preset condition if it is determined that the instruction group meets the first, second and third conditions at the same time; otherwise, it is determined that the instruction group does not meet the second preset condition.

[0270] The binary translation device of the embodiment of the present invention can be applied to a dynamic binary translator. During the binary translation process, loop identification is performed. If it is identified that there is a target loop body in the basic block to be translated, the dependency relationship between the instructions in the target loop body is obtained. Based on the obtained dependency relationship, it is identified whether there is a target instruction group that can be optimized for translation in the target loop body. If so, the target instruction group is marked. The target instruction group contains an optimizable instruction sequence. During the translation process, the marked target instruction group can be optimized for translation; the optimized translation refers to translating the target instruction group into a target instruction corresponding to a matching preset mode, and the number of instructions of the target instruction corresponding to the preset mode is less than the number of instructions in the target instruction group. Thus, multiple source instructions (instructions based on the source platform architecture) in the target loop body can be fused and translated into a smaller number of target instructions (instructions based on the target platform architecture), which can reduce the number of translated instructions and improve the running efficiency of the translated program.

[0271] As for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0272] Reference Figure 8 , is a schematic diagram of the structure of an electronic device provided by an embodiment of the present invention. Figure 8 As shown, the electronic device includes: a processor, a memory, a communication interface and a communication bus, and the processor, the memory and the communication interface communicate with each other through the communication bus; the memory is used to store at least one executable instruction, and the executable instruction enables the processor to execute the steps of the binary translation method of the above-mentioned embodiment.

[0273] An embodiment of the present invention provides a non-transitory computer-readable storage medium. When instructions in the storage medium are executed by a program or a processor of a terminal, the terminal is enabled to perform the steps of the binary translation method of the aforementioned embodiment.

[0274] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0275] It will be appreciated by those skilled in the art that the embodiments of the present invention may be provided as methods, devices, or computer program products. Therefore, the embodiments of the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the embodiments of the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes.

[0276] The embodiments of the present invention are described with reference to the flowcharts and / or block diagrams of the methods, terminal devices (systems), and computer program products according to the embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of the processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing terminal device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing terminal device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0277] These computer program instructions may also be stored in a computer readable memory capable of directing a computer or other programmable data processing terminal device to operate in a predictable manner, so that the instructions stored in the computer readable memory produce a manufactured product including an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0278] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal device so that a series of operating steps are executed on the computer or other programmable terminal device to produce a computer-implemented process, thereby providing instructions for executing on the computer or other programmable terminal device to implement the process. Figure 1 A process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.

[0279] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or terminal device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or terminal device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or terminal device including the elements.

[0280] Specific examples are used herein to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for those skilled in the art, according to the idea of ​​the present invention, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present invention.

Claims

1. A binary translation method, characterized in that: The method comprises: If it is identified that there is a target loop body in the basic block to be translated, the dependency relationship between instructions in the target loop body is obtained; the dependency relationship obtained includes the dependency relationship between instructions in the same level iteration and the dependency relationship between instructions in different levels iteration; If a target instruction group matching a preset pattern is identified in the target loop body, the target instruction group is marked; a target instruction group includes at least two instructions; each instruction in the target instruction group has a dependency relationship on the same register, and no other instructions have a dependency relationship on the register; The marked target instruction group is optimized and translated; the optimized translation refers to translating the target instruction group into target instructions corresponding to a matching preset mode, wherein the number of target instructions corresponding to the preset mode is less than the number of instructions in the target instruction group.

2. The method according to claim 1, characterized in that The step of identifying that a target loop body exists in a basic block to be translated includes: Determine whether there is a loop body in the basic block; If it is determined that there is a loop body in the basic block, then determining whether the loop body satisfies a first preset condition; the first preset condition includes: the destination address of the jump instruction in the loop body is within the address range of the loop body; If it is determined that the loop body satisfies the first preset condition, it is determined that a target loop body exists in the basic block.

3. The method according to claim 1, characterized in that The target loop body includes N iterations, and the optimized translation of the marked target instruction group includes: According to loop-related information of the target loop body, in the first N-1 iterations of the target loop body, the marked target instruction group is optimized translated, and in the Nth iteration of the target loop body, the marked target instruction group is normally translated; the loop-related information includes loop boundaries, loop increments and loop steps.

4. The method according to claim 3, characterized in that The step of optimizing and translating the marked target instruction group in the first N-1 iterations of the target loop body, and performing non-optimizing and translating the marked target instruction group in the Nth iteration of the target loop body comprises: Performing a first translation on the target loop body to obtain a first translation code block; the first translation refers to performing an optimized translation on the target instruction group marked in the target loop body, and performing a normal translation on other instructions; Performing a second translation on the target loop body to obtain a second translation code block; the second translation refers to performing a common translation on all instructions in the target loop body; the first instruction in the second translation code block is a newly added instruction, which is used to restore the loop boundary; Generate an entry code block; the entry code block is used to modify the loop boundary of the target loop body according to the loop step, and control the first N-1 iterations of the target loop body to jump to the entry of the first translation code block according to the loop increment and the modified loop boundary, and control the Nth iteration to jump to the entry of the second translation code block.

5. The method according to claim 1, characterized in that The method further comprises: Taking the loop exit of the target loop body as a starting point, a reverse depth-first search is performed based on a target dependency relationship to identify loop-related instructions in the target loop body; the target dependency relationship refers to: a previous instruction performs a write operation on a register, and a subsequent instruction performs a read operation on the register; The loop-related information of the target loop body is obtained based on the identified loop-related instructions.

6. The method according to any one of claims 1 to 4, characterized in that: The obtaining of dependencies between instructions in the target loop body includes: Analyzing the dependency relationship between the instructions in the target loop body based on the registers that the instructions in the target loop body depend on; Generate a dependency graph by taking instructions in the target loop body as nodes and taking dependencies of instructions on the same register as edges; Using a two-dimensional array to store the dependency graph, the lower triangular elements of the two-dimensional array represent the dependency between instructions in the same level of iteration, and the upper triangular elements of the two-dimensional array represent the dependency between instructions in different levels of iteration; Delete invalid dependencies in the dependency graph.

7. The method according to any one of claims 1 to 4, characterized in that: The identifying that there is a target instruction group matching a preset pattern in the target loop body includes: By pattern matching, determining whether there is an instruction group matching a preset pattern in the target loop body; If it is determined that there is an instruction group matching the preset pattern in the target loop body, determining whether there is a dependency relationship on the same register between the instructions in the instruction group; If it is determined that there is a dependency relationship between the instructions in the instruction group on the same register, then determine whether the instruction group meets a second preset condition; the second preset condition includes: for the same register that the instructions in the instruction group depend on, there is no dependency relationship between other instructions on the register; If it is determined that the instruction group satisfies the second preset condition, it is determined that there is a target instruction group matching the preset mode in the target loop body.

8. The method according to claim 7, characterized in that The determining whether the instruction group satisfies a second preset condition includes: Determine whether the target register has been read before a new value is written between the last instruction in the instruction group and the loop exit of the target loop body; if it has not been read, condition one is satisfied; otherwise, condition one is not satisfied; the target register is the same register that each instruction in the instruction group depends on; Determine whether the target register has been read before a new value is written between the loop entry of the target loop body and the first instruction in the instruction group; if not, condition 2 is satisfied; otherwise, condition 2 is not satisfied; Determine whether the target register has been operated between the instructions in the instruction group; if not, condition three is satisfied; otherwise, condition three is not satisfied; If it is determined that the instruction group matching the preset mode satisfies the first, second and third conditions at the same time, it is determined that the instruction group satisfies the second preset condition; otherwise, it is determined that the instruction group does not satisfy the second preset condition.

9. A binary translation device, characterized in that: The device comprises: A first identification module is used to obtain the dependency relationship between instructions in the target loop body if it is identified that there is a target loop body in the basic block to be translated; the obtained dependency relationship includes the dependency relationship between instructions in the same level iteration and the dependency relationship between instructions in different levels iteration; A second identification module is used to mark the target instruction group if it is identified that there is a target instruction group matching a preset pattern in the target loop body; a target instruction group includes at least two instructions; there is a dependency relationship between the instructions in the target instruction group on the same register, and no other instructions have a dependency relationship on the register; The optimized translation module is used to optimize the translation of the marked target instruction group; the optimized translation refers to translating the target instruction group into target instructions corresponding to a matching preset mode, and the number of instructions of the target instructions corresponding to the preset mode is less than the number of instructions in the target instruction group.

10. An electronic device, characterized in that: include: A processor, a memory, a communication interface and a communication bus, wherein the processor, the memory and the communication interface communicate with each other via the communication bus; The memory is used to store at least one executable instruction, and the executable instruction enables the processor to execute the steps of the binary translation method according to any one of claims 1 to 8.

11. A readable storage medium, characterized in that: The readable storage medium stores a program or instruction, and when the program or instruction is executed by a processor, the steps of the binary translation method according to any one of claims 1 to 8 are implemented.

12. A computer program product, comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the binary translation method according to any one of claims 1 to 8 are implemented.

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