Data processing method and related device
By setting the status bits in the shadow buffer to determine the timing of data synchronization and reading, the problem of data reentry in the prior art is solved and the accuracy of data reading is achieved.
Patent Information
- Application Number
- CN202411677537.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-21
- Publication Date
- 2025-03-11
AI Technical Summary
In the prior art, the acquisition and copying of data services are asynchronous, resulting in data reentry problems when data in shadow buffers are used simultaneously, resulting in data cache and read errors.
By setting the status bits in the shadow buffer, we can determine whether the status bits of all shadow buffers are read or written, and then decide whether to perform data synchronization or data reading to ensure that data synchronization and data reading are mutually exclusive and avoid data reentry.
The status bits of the shadow buffer determine the timing of data synchronization and reading, ensuring the accuracy of data reading, and avoiding data cache and read errors.
Smart Images
Figure CN119597682A_ABST
Abstract
Description
Technical Field
[0001] The embodiments of the present application relate to the field of computers, and in particular to a data processing method and related devices. Background Art
[0002] In the computer field, to use the data in the physical buffer, it is usually necessary to directly read the physical buffer to obtain the required data, but this is inefficient and requires a long waiting time. In order to quickly read the required data, it is necessary to use the shadow buffer. First, the data in the physical buffer is copied to the shadow buffer, and the user program then obtains the relevant data from the shadow buffer.
[0003] In the process of implementing the invention, the inventors found that there are at least the following problems in the prior art. In the existing scheme, the data acquisition service and the data copy service are asynchronous services, and the two services are not mutually exclusive. When the data acquisition service and the data copy service use the data in the shadow cache at the same time, there will be a problem of data re-entry, that is, the data corresponding to the two services are not consistent, resulting in data caching and reading errors. Summary of the invention
[0004] The embodiments of the present application provide a data processing method and related devices for avoiding data caching and reading errors.
[0005] A first aspect of an embodiment of the present application provides a data processing method, which is applied to a system, wherein the system includes a plurality of physical buffers and a plurality of shadow buffers, and the method includes:
[0006] receiving a data reading instruction for data to be read;
[0007] Determine whether all status bits of the shadow buffers are in a read state according to the data read instruction;
[0008] If so, synchronizing the data cached in the multiple physical buffers to the multiple shadow buffers, and updating the status bits of the multiple shadow buffers;
[0009] Determine whether all status bits of the shadow buffers are in a written state;
[0010] If all are in the written state, a read operation is performed on the target shadow buffer to obtain the data to be read, and the state bit of the target shadow buffer is updated to the read state. The target shadow buffer is the shadow buffer that caches the data to be read.
[0011] Optionally, if the system is set with parameters, a physical heartbeat value and a shadow heartbeat value, before determining whether all status bits of the shadow buffers are in a written state, the method further includes:
[0012] If not, performing a preset operation according to the physical heartbeat value and the shadow heartbeat value to jump out of the deadlock;
[0013] After updating the status bits of the plurality of shadow buffers and before determining whether the status bits of all the shadow buffers are in a written state, the method further includes:
[0014] Increase the physical heartbeat value by one;
[0015] After determining whether all status bits of the shadow buffers are in a written state, the method further includes:
[0016] If not all are in the written state, a preset operation is performed according to the physical heartbeat value and the shadow heartbeat value to jump out of the deadlock;
[0017] After performing a read operation on the target shadow buffer to obtain the data to be read, the method further includes:
[0018] If all the status bits of the target shadow buffer are in the read state, the shadow heartbeat value is increased by one; if not all the status bits of the target shadow buffer are in the read state, wait for timeout to increase the shadow heartbeat value by one.
[0019] Optionally, if the shadow heartbeat value is equal to the physical heartbeat value, performing a preset operation according to the physical heartbeat value and the shadow heartbeat value includes:
[0020] Execute a target step, wherein the target step is to synchronize the data cached in the multiple physical buffers to the multiple shadow buffers, and update the status bits of the multiple shadow buffers to a written state.
[0021] Optionally, if the shadow heartbeat value is less than the physical heartbeat value, performing a preset operation according to the physical heartbeat value and the shadow heartbeat value includes:
[0022] Wait for timeout to update the status bits of all the shadow buffers to the read status and increase the shadow heartbeat value by one.
[0023] Optionally, if the shadow heartbeat value is greater than the physical heartbeat value, performing a preset operation according to the physical heartbeat value and the shadow heartbeat value includes:
[0024] Update the status bits of all the shadow buffers to a read status.
[0025] Optionally, after updating the status bits of the plurality of shadow buffers and before determining whether the status bits of all the shadow buffers are in a written state, the method further includes:
[0026] Determining whether the data cached in the plurality of physical caches and the data cached in the plurality of shadow caches are the same;
[0027] If they are the same, then executing the step of determining whether the status bits of all the shadow buffers are all in the written state;
[0028] If they are not the same, the status bits of all the shadow buffers are updated to the read status.
[0029] Optionally, performing a read operation on the target shadow buffer to obtain the data to be read includes:
[0030] Performing a read operation on the target shadow buffer to obtain target data;
[0031] Determining whether the target data is the same as the data to be read;
[0032] If they are the same, the target data is determined as the data to be read;
[0033] If they are not the same, the status bits of all the shadow buffers are updated to the read status.
[0034] A second aspect of an embodiment of the present application provides a data processing device, which is applied to a system, wherein the system includes a plurality of physical buffers and a plurality of shadow buffers, including:
[0035] A receiving unit, used for receiving a data reading instruction for data to be read;
[0036] A judging unit, used for judging whether the status bits of all the shadow buffers are all in a read state according to the data reading instruction;
[0037] A synchronization unit, configured to synchronize the data cached in the plurality of physical buffers to the plurality of shadow buffers and update the status bits of the plurality of shadow buffers when the status bits of all the shadow buffers are in a read state;
[0038] The judging unit is further used to judge whether the status bits of all the shadow buffers are all in the written state;
[0039] The reading unit is used to perform a read operation on the target shadow buffer when the status bits of all the shadow buffers are in the written state, obtain the data to be read, and update the status bit of the target shadow buffer to the read state. The target shadow buffer is a shadow buffer that caches the data to be read.
[0040] A third aspect of an embodiment of the present application provides a data processing device, including:
[0041] CPU, memory and input / output interface;
[0042] The memory is a short-term storage memory or a persistent storage memory;
[0043] The central processing unit is configured to communicate with the memory and execute instructions in the memory to perform the aforementioned method.
[0044] A fourth aspect of an embodiment of the present application provides a computer-readable storage medium, comprising instructions, which, when executed on a computer, enable the computer to execute the aforementioned method.
[0045] It can be seen from the above technical solutions that the embodiments of the present application have the following advantages:
[0046] First, a data read instruction for the data to be read is received, and then the status bits of all shadow buffers are judged according to the data read instruction whether they are all in the read state. If so, the data cached in the multiple physical buffers are synchronized to the multiple shadow buffers, and the status bits of the multiple shadow buffers are updated. Then, it is judged whether the status bits of all shadow buffers are all in the written state. If they are all in the written state, a read operation is performed on the target shadow buffer to obtain the data to be read, and the status bit of the target shadow buffer is updated to the read state. There are two situations for the status bit of the shadow buffer, one is the read state, and the other is the written state. Data synchronization is performed when the status bits of all shadow buffers are all in the read state, and data reading is performed when the status bits of all shadow buffers are all in the written state. Whether to perform data synchronization or data reading is determined by the status bits of the shadow buffer, so that data synchronization and data reading are mutually exclusive. Only one of data synchronization and data reading can be executed in the same time period, so there will be no problem of data re-entry, and the accuracy of data reading is guaranteed. BRIEF DESCRIPTION OF THE DRAWINGS
[0047] Figure 1 This is a schematic diagram of the framework disclosed in this application;
[0048] Figure 2 A schematic diagram of an embodiment of a data processing method disclosed in this application;
[0049] Figure 3 A schematic diagram of another embodiment of a data processing method disclosed in this application;
[0050] Figure 4 A schematic diagram of an embodiment of a data processing device disclosed in the present application;
[0051] Figure 5 A schematic diagram of another embodiment of a data processing device disclosed in the present application;
[0052] Figure 6 This is a schematic diagram of another embodiment of a data processing device disclosed in this application. DETAILED DESCRIPTION
[0053] The present application is further described in detail below in conjunction with the accompanying drawings.
[0054] The embodiments of the present application provide a data processing method and related devices for avoiding data caching and reading errors.
[0055] The shadow cache technology can be used to obtain the required data more quickly. In the existing solution, the data in the physical cache can be copied to the shadow cache first, and then read from the shadow cache. However, the data acquisition service and the data copy service are asynchronous services. When the two non-mutually exclusive services use the data in the shadow cache at the same time, data caching and reading errors will occur. In order to solve the above problems, the present application provides a data processing method and related devices, which can determine whether to synchronize or read data through the status bit of the shadow cache. The two services are mutually exclusive, and there will be no problem of data re-entry, thereby ensuring the accuracy of data reading. Please refer to Figure 1 The system involved in this application includes multiple physical buffers and multiple shadow buffers. The multiple physical buffers constitute a data buffer area, and the multiple shadow buffers constitute a shadow buffer area. A specific register is provided to store the status bits of the shadow buffers for judgment.
[0056] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.
[0057] The terms "first", "second", "third", "fourth", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments described herein can be implemented in an order other than that illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.
[0058] The following is a description of a data processing method of the present application. Figure 2 An embodiment of a data processing method of the present application is applied to a system, the system includes multiple physical buffers and multiple shadow buffers, and the method includes:
[0059] 201. Receive a data reading instruction for data to be read;
[0060] Receive a data read instruction for the data to be read. The data to be read may be data in a specified storage location or data in a specified field, etc., for subsequent query and reading, which is not limited here. The data read instruction may be sent by a user program or sent by an external device to a data processing device via a network, and may be set according to actual needs, which is not limited here.
[0061] 202. Determine whether the status bits of all shadow buffers are all in the read state according to the data read instruction. If so, execute step 203. If not, return to execute step 202.
[0062] Specifically, the system will be provided with a register for storing the status bit of the shadow buffer, and the data of the register can be changed at any time. There are two types of status bits of the shadow buffer, one is the read state, and the other is the written state. In one implementation, when in the read state, the value of the status bit of the shadow buffer is 0, and when in the written state, the value of the status bit of the shadow buffer is 1. It can be detected whether the values of the status bits of all shadow buffers are all 0, and if it is judged to be yes, the next step is performed.
[0063] 203. Synchronize the data cached in the multiple physical buffers to the multiple shadow buffers, and update the status bits of the multiple shadow buffers;
[0064] If the status bits of all shadow buffers are all in the read state, the data cached in the multiple physical buffers are synchronized to the multiple shadow buffers, and the status bits of the multiple shadow buffers are updated. Specifically, all the data (including the data to be read) in the multiple physical buffers are synchronized to the multiple shadow buffers, that is, copied to the shadow buffers, and the status bits of the multiple shadow buffers are updated, that is, the registers storing the status bits of the shadow buffers are operated to update the status bits of the multiple shadow buffers to the written state, but errors may occur in the actual updating process, so subsequent detection and judgment are required.
[0065] 204. Determine whether the status bits of all shadow buffers are all in the written state. If so, execute step 205. If not, return to execute step 204.
[0066] Specifically, the register storing the status bits of all shadow buffers is read to make a judgment. In one embodiment, if the value of the status bit of the shadow buffer is 0 in the read state and the value of the status bit of the shadow buffer is 1 in the written state, it can be judged whether the values of the status bits of all shadow buffers are 1. If the values are all 1, a data reading service is executed to obtain the data to be read.
[0067] 205. Perform a read operation on the target shadow buffer to obtain the data to be read, and update the status bit of the target shadow buffer to a read status.
[0068] The target shadow buffer is read to obtain the data to be read, and the status bit of the target shadow buffer is updated to the read state, wherein the target shadow buffer is a shadow buffer that caches the data to be read. Specifically, the shadow buffer caches all the data in the physical buffer, and the shadow buffer that caches the data to be read is the target shadow buffer. It is only necessary to read the target shadow buffer to obtain the data to be read, and update its status bit to the read state, and the current cycle ends, waiting for the next cycle to start.
[0069] In the embodiment of the present application, a data read instruction for the data to be read is first received, and then the status bits of all shadow buffers are determined according to the data read instruction whether they are all in the read state. If so, the data cached in the multiple physical buffers are synchronized to the multiple shadow buffers, and the status bits of the multiple shadow buffers are updated, and then it is determined whether the status bits of all shadow buffers are all in the written state. If they are all in the written state, a read operation is performed on the target shadow buffer to obtain the data to be read, and the status bit of the target shadow buffer is updated to the read state. There are two situations for the status bit of the shadow buffer, one is the read state, and the other is the written state. When the status bits of all shadow buffers are all in the read state, data synchronization is performed, and when the status bits of all shadow buffers are all in the written state, data reading is performed. Whether to perform data synchronization or data reading is determined by the status bits of the shadow buffer, so that data synchronization and data reading are mutually exclusive. Only one of data synchronization and data reading can be executed in the same time period, so there will be no problem of data reentry, and the accuracy of data reading is guaranteed.
[0070] In order to verify the integrity and correctness of the data involved in the two businesses of data synchronization and data reading, verification will be performed. At the same time, in order to avoid deadlock in data reading or data synchronization, two parameters are introduced, namely the physical heartbeat value and the shadow heartbeat value. Figure 3 Another embodiment of a data processing method of the present application is applied to a system, the system includes multiple physical buffers and multiple shadow buffers, the system is set with parameters, a physical heartbeat value and a shadow heartbeat value, and the method includes:
[0071] 301. Receive a data reading instruction for data to be read;
[0072] Receive a data read instruction for the data to be read. The data to be read may be data in a specified storage location or data in a specified field, etc., for subsequent query and reading, which is not limited here. The data read instruction may be sent by a user program or sent by an external device to a data processing device via a network, and may be set according to actual needs, which is not limited here.
[0073] 302. Determine whether the status bits of all shadow buffers are all in the read state according to the data read instruction. If so, execute step 303; if not, execute step 308;
[0074] Specifically, the system will be provided with a register for storing the status bit of the shadow buffer, and the data of the register can be changed at any time. There are two types of status bits of the shadow buffer, one is the read state, and the other is the written state. In one embodiment, when in the read state, the value of the status bit of the shadow buffer is 0, and when in the written state, the value of the status bit of the shadow buffer is 1. It can be detected whether the values of the status bits of all shadow buffers are all 0, and if so, the next step is performed.
[0075] 303. Synchronize the data cached in the multiple physical buffers to the multiple shadow buffers, and update the status bits of the multiple shadow buffers;
[0076] If the status bits of all shadow buffers are all in the read state, the data cached in the multiple physical buffers are synchronized to the multiple shadow buffers, and the status bits of the multiple shadow buffers are updated. Specifically, all the data (including the data to be read) in the multiple physical buffers are synchronized to the multiple shadow buffers, that is, copied to the shadow buffers, and the status bits of the multiple shadow buffers are updated, that is, the registers storing the status bits of the shadow buffers are operated to update the status bits of the multiple shadow buffers to the written state, but errors may occur in the actual updating process, so subsequent detection and judgment are required.
[0077] 304. Determine whether the data cached in the multiple physical caches and the data cached in the multiple shadow caches are the same. If not, execute step 305. If yes, execute step 306.
[0078] Specifically, the data can be compared one by one, or compared according to a verification algorithm, which is not limited here. There are multiple algorithms for verification in the verification algorithm. In one embodiment, a cyclic redundancy check (CRC) can be used to determine whether the two are the same. Specifically, the CRC check code corresponding to the data cached in multiple physical buffers is calculated, and then the CRC check code corresponding to the data cached in multiple shadow buffers is calculated to determine whether the two CRC check codes are the same. If they are the same, it means that the data cached in the multiple physical buffers and the data cached in the multiple shadow buffers are the same, and the data is completely synchronized and accurate. If they are not the same, it means that the data cached in the multiple physical buffers and the data cached in the multiple shadow buffers are not the same, and the data is incomplete or inaccurate.
[0079] 305. Update the status bits of all shadow buffers to a read status;
[0080] If the data cached in the multiple physical buffers is different from the data cached in the multiple shadow buffers, the status bits of all shadow buffers are updated to the read state. Specifically, if the data of the two are different, it means that the data synchronization service has an error. At this time, the process is terminated, and the status bits of all shadow buffers are forcibly updated to the read state, ending this cycle and waiting for the next cycle.
[0081] 306. Increase the physical heartbeat value by one;
[0082] If the data cached in the multiple physical buffers is the same as the data cached in the multiple shadow buffers, it means that the verification is passed, and the physical heartbeat value is increased by one, indicating that the data synchronization service is completed once.
[0083] 307. Determine whether the status bits of all shadow buffers are all in the written state. If not, execute step 308. If yes, execute step 309.
[0084] Specifically, the register storing the status bits of all shadow buffers is read to make a judgment. In one embodiment, if the value of the status bit of the shadow buffer is 0 in the read state and the value of the status bit of the shadow buffer is 1 in the written state, it can be judged whether the values of the status bits of all shadow buffers are 1. If the values are all 1, a data reading service is executed to obtain the data to be read.
[0085] 308. Execute a preset operation according to the physical heartbeat value and the shadow heartbeat value to jump out of the deadlock;
[0086] Perform a preset operation according to the physical heartbeat value and the shadow heartbeat value to jump out of the deadlock. Specifically, the physical heartbeat value and the shadow heartbeat value will be compared, and then the corresponding operation will be performed. In one embodiment, if the shadow heartbeat value is equal to the physical heartbeat value, the data synchronization service is performed, that is, the data cached in multiple physical buffers are synchronized to multiple shadow buffers, and the status bits of multiple shadow buffers are updated to the written state. In another embodiment, if the shadow heartbeat value is less than the physical heartbeat value, wait for timeout to update the status bits of all shadow buffers to the read state, and add one to the shadow heartbeat value. Among them, a time threshold can be set in advance. When the shadow heartbeat value is less than the physical heartbeat value, the operation will be suspended. When the time exceeds the time threshold, the status bits of all shadow buffers are automatically updated, and the shadow heartbeat value is added by one. In another embodiment, if the shadow heartbeat value is greater than the physical heartbeat value, the status bits of all shadow buffers are updated to the read state. Among them, the situation that the shadow heartbeat value is greater than the physical heartbeat value is an abnormal situation and will not occur under normal circumstances. The abnormal situation is jumped out by forcibly refreshing the status bits of all shadow buffers to the read state, ending this cycle and waiting for the next cycle.
[0087] 309. Perform a read operation on the target shadow buffer to obtain the data to be read, and update the status bit of the target shadow buffer to a read status;
[0088] A read operation is performed on the target shadow buffer to obtain the data to be read, and the status bit of the target shadow buffer is updated to the read state, wherein the target shadow buffer is a shadow buffer that caches the data to be read. The shadow buffer caches all the data in the physical buffer, and the shadow buffer that caches the data to be read is the target shadow buffer. It is only necessary to read the target shadow buffer to obtain the data and update its status bit to the read state.
[0089] In order to ensure the accuracy of the data, the read data can be verified. In one embodiment, a read operation is performed on the target shadow buffer. After obtaining the target data, it is necessary to determine whether the target data is the same as the data to be read. If they are the same, the target data is determined as the data to be read. If they are not the same, the status bits of all shadow buffers are updated to the read state. Specifically, a CRC check algorithm can be used for verification. Based on the CRC check algorithm, the CRC check code corresponding to the target data is calculated, and then the CRC check code corresponding to the data to be read cached by the target shadow buffer is calculated. The two CRC check codes are compared. If they are the same, it means that the target data is the data to be read. If they are different, it means that the target data is not the data to be read, and the data read is defective or inaccurate. The status bit of the shadow buffer is forced to be refreshed to the read state, and the current cycle ends, waiting for the next cycle.
[0090] 310. If all the status bits of the target shadow buffer are in the read state, the shadow heartbeat value is increased by one; if not all the status bits of the target shadow buffer are in the read state, wait for timeout to increase the shadow heartbeat value by one.
[0091] After reading the data to be read, change the shadow heartbeat value as appropriate. If the status bits of the target shadow buffer are all in the read state, add one to the shadow heartbeat value; if the status bits of the target shadow buffer are not all in the read state, wait for timeout to add one to the shadow heartbeat value. Specifically, if the status bits of the target shadow buffer are all in the read state, it means that complete access has been achieved and the data to be read has been read completely, and the shadow heartbeat value is added by one. If the status bits of the target shadow buffer are not all in the read state, it means that some of the target shadow buffers have not been read, and the data to be read has not been read completely, which may be that the reading has not been completed, or there may be a reading error. Wait for timeout, and then add one to the shadow heartbeat value.
[0092] In the present embodiment, the status bit of the shadow buffer has two situations, one is the read state, and the other is the written state. Data synchronization is performed only when the status bits of all shadow buffers are all in the read state, or the physical heartbeat value is equal to the shadow heartbeat value. Data reading is performed only when the status bits of all shadow buffers are all in the written state. In this way, data synchronization and data reading are mutually exclusive. Only one of data synchronization and data reading can be executed in the same time period, so there will be no problem of data reentry, and the accuracy of data reading is guaranteed. In addition, the physical heartbeat value and the shadow heartbeat value are introduced, and the corresponding operation is performed by comparing the two values, and the deadlock situation is jumped out as soon as possible, which improves the processing efficiency. The present application also uses a check code to check the integrity and accuracy of the data, which ensures the integrity and accuracy of the data. In addition, the access distribution of the cache can be monitored through the status bit of the shadow buffer, which is convenient for users.
[0093] A data processing method in an embodiment of the present application is described above, and a data processing device in an embodiment of the present application is described below. Figure 4 An embodiment of a data processing device in an embodiment of the present application is applied to a system, wherein the system includes a plurality of physical buffers and a plurality of shadow buffers, including:
[0094] A receiving unit 401 is used to receive a data reading instruction for data to be read;
[0095] A judging unit 402, configured to judge whether all status bits of the shadow buffers are in a read state according to the data read instruction;
[0096] A synchronization unit 403, configured to synchronize the data cached in the plurality of physical buffers to the plurality of shadow buffers and update the status bits of the plurality of shadow buffers when the status bits of all the shadow buffers are in a read state;
[0097] The judging unit 402 is further used to judge whether the status bits of all the shadow buffers are all in the written state;
[0098] The reading unit 404 is used to perform a read operation on the target shadow buffer when the status bits of all the shadow buffers are in the written state, obtain the data to be read, and update the status bit of the target shadow buffer to the read state. The target shadow buffer is the shadow buffer that caches the data to be read.
[0099] In the embodiment of the present application, the receiving unit 401 first receives a data read instruction for the data to be read, and then the judging unit 402 judges whether the status bits of all shadow buffers are all in the read state according to the data read instruction. If so, the synchronization unit 403 synchronizes the data cached in the multiple physical buffers to the multiple shadow buffers, and updates the status bits of the multiple shadow buffers, and then judges whether the status bits of all shadow buffers are all in the written state. If all are in the written state, the reading unit 404 performs a read operation on the target shadow buffer to obtain the data to be read, and updates the status bit of the target shadow buffer to the read state. There are two situations for the status bit of the shadow buffer, one is the read state, and the other is the written state. When the status bits of all shadow buffers are all in the read state, data synchronization is performed, and when the status bits of all shadow buffers are all in the written state, data reading is performed. Whether to perform data synchronization or data reading is determined by the status bits of the shadow buffer, so that data synchronization and data reading are mutually exclusive. Only one of data synchronization and data reading can be executed in the same time period, so there will be no problem of data reentry, and the accuracy of data reading is guaranteed.
[0100] A data processing device in an embodiment of the present application is described in detail below. Figure 5 Another embodiment of a data processing device according to an embodiment of the present application is applied to a system, wherein the system includes a plurality of physical buffers and a plurality of shadow buffers, including:
[0101] A receiving unit 501 is used to receive a data reading instruction for data to be read;
[0102] A judging unit 502, configured to judge whether all status bits of the shadow buffers are in a read state according to the data read instruction;
[0103] A synchronization unit 503, configured to synchronize the data cached in the plurality of physical buffers to the plurality of shadow buffers and update the status bits of the plurality of shadow buffers when the status bits of all the shadow buffers are in a read state;
[0104] The judging unit 502 is further used to judge whether the status bits of all the shadow buffers are all in the written state;
[0105] The reading unit 504 is used to perform a read operation on the target shadow buffer when the status bits of all the shadow buffers are in the written state, obtain the data to be read, and update the status bit of the target shadow buffer to the read state. The target shadow buffer is the shadow buffer that caches the data to be read.
[0106] If the system is provided with parameters, a physical heartbeat value and a shadow heartbeat value, before determining whether all status bits of the shadow buffers are in a written state, the method further includes:
[0107] If not, performing a preset operation according to the physical heartbeat value and the shadow heartbeat value to jump out of the deadlock;
[0108] After the status bits of the plurality of shadow buffers are updated, the data processing device further includes a processing unit 505, which is specifically configured to:
[0109] Increase the physical heartbeat value by one;
[0110] Also used for:
[0111] If not all are in the written state, a preset operation is performed according to the physical heartbeat value and the shadow heartbeat value to jump out of the deadlock;
[0112] Also used for:
[0113] If all the status bits of the target shadow buffer are in the read state, the shadow heartbeat value is increased by one; if not all the status bits of the target shadow buffer are in the read state, wait for timeout to increase the shadow heartbeat value by one.
[0114] If the shadow heartbeat value is equal to the physical heartbeat value, the processing unit 505 is specifically configured to:
[0115] Execute a target step, wherein the target step is to synchronize the data cached in the multiple physical buffers to the multiple shadow buffers, and update the status bits of the multiple shadow buffers to a written state.
[0116] If the shadow heartbeat value is less than the physical heartbeat value, the processing unit 505 is specifically configured to:
[0117] Wait for timeout to update the status bits of all the shadow buffers to the read status and increase the shadow heartbeat value by one.
[0118] If the shadow heartbeat value is greater than the physical heartbeat value, the processing unit 505 is specifically configured to:
[0119] Update the status bits of all the shadow buffers to a read status.
[0120] The processing unit 505 is further configured to:
[0121] Determining whether the data cached in the plurality of physical caches and the data cached in the plurality of shadow caches are the same;
[0122] If they are the same, then executing the step of determining whether the status bits of all the shadow buffers are all in the written state;
[0123] If they are not the same, the status bits of all the shadow buffers are updated to the read status.
[0124] The reading unit 504 is specifically used for:
[0125] Performing a read operation on the target shadow buffer to obtain target data;
[0126] Determining whether the target data is the same as the data to be read;
[0127] If they are the same, the target data is determined as the data to be read;
[0128] If they are not the same, the status bits of all the shadow buffers are updated to the read status.
[0129] The functions and processes performed by each unit in the data processing device of this embodiment are similar to those described above. Figures 2 to 3 The functions and processes performed by the data processing device are similar and will not be repeated here.
[0130] Figure 6 It is a schematic diagram of the structure of a data processing device provided in an embodiment of the present application. The data processing device 600 may include one or more central processing units (CPU) 601 and a memory 605. The memory 605 stores one or more application programs or data.
[0131] The memory 605 may be a volatile storage or a persistent storage. The program stored in the memory 605 may include one or more modules, each of which may include a series of instruction operations in the data processing device 600. Furthermore, the central processing unit 601 may be configured to communicate with the memory 605 and execute a series of instruction operations in the memory 605 on the data processing device 600.
[0132] The data processing device 600 may also include one or more power supplies 602, one or more wired or wireless network interfaces 603, one or more input and output interfaces 604, and / or one or more operating systems, such as Windows ServerTM, Mac OS XTM, UnixTM, LinuxTM, FreeBSDTM, etc.
[0133] The CPU 601 can execute the aforementioned Figures 2 to 3 The operations performed by the data processing device in the illustrated embodiment will not be described in detail herein.
[0134] An embodiment of the present application also provides a computer-readable storage medium, including instructions, which, when executed on a computer, enable the computer to execute the method in the aforementioned embodiment.
[0135] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.
[0136] It should be noted that, although the steps in the flowcharts involved in the embodiments are drawn in sequence according to the instructions of the arrows, unless otherwise clearly stated in this document, there is no strict order restriction on the execution of these steps, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowcharts involved in the embodiments may include multiple steps or multiple stages, and these steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least a part of the steps or stages in other steps.
[0137] In the several embodiments provided in the present application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of units is only a logical function division. There may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, devices or units, which can be electrical, mechanical or other forms.
[0138] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
[0139] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.
[0140] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for a computer device (which can be a personal computer, server, or network device, etc.) to perform all or part of the steps of the various embodiments of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, read-only memory), random access memory (RAM, random access memory), disk or optical disk, etc. Various media that can store program codes.
Claims
1. A data processing method, characterized in that: Applied to a system, the system comprising a plurality of physical buffers and a plurality of shadow buffers, the method comprising: receiving a data reading instruction for data to be read; Determine whether all status bits of the shadow buffers are in a read state according to the data read instruction; If so, synchronizing the data cached in the multiple physical buffers to the multiple shadow buffers, and updating the status bits of the multiple shadow buffers; Determine whether all status bits of the shadow buffers are in a written state; If all are in the written state, a read operation is performed on the target shadow buffer to obtain the data to be read, and the state bit of the target shadow buffer is updated to the read state. The target shadow buffer is the shadow buffer that caches the data to be read.
2. The data processing method according to claim 1, characterized in that: If the system is set with parameters, a physical heartbeat value and a shadow heartbeat value, before determining whether all status bits of the shadow buffers are in a written state, the method further includes: If not, performing a preset operation according to the physical heartbeat value and the shadow heartbeat value to jump out of the deadlock; After updating the status bits of the plurality of shadow buffers and before determining whether the status bits of all the shadow buffers are in a written state, the method further includes: Increase the physical heartbeat value by one; After determining whether all status bits of the shadow buffers are in a written state, the method further includes: If not all are in the written state, a preset operation is performed according to the physical heartbeat value and the shadow heartbeat value to jump out of the deadlock; After performing a read operation on the target shadow buffer to obtain the data to be read, the method further includes: If all the status bits of the target shadow buffer are in the read state, the shadow heartbeat value is increased by one; if not all the status bits of the target shadow buffer are in the read state, wait for timeout to increase the shadow heartbeat value by one.
3. The data processing method according to claim 2, characterized in that: If the shadow heartbeat value is equal to the physical heartbeat value, performing a preset operation according to the physical heartbeat value and the shadow heartbeat value includes: Execute a target step, wherein the target step is to synchronize the data cached in the multiple physical buffers to the multiple shadow buffers, and update the status bits of the multiple shadow buffers to a written state.
4. The data processing method according to claim 2, characterized in that: If the shadow heartbeat value is less than the physical heartbeat value, performing a preset operation according to the physical heartbeat value and the shadow heartbeat value includes: Wait for timeout to update the status bits of all the shadow buffers to the read status and increase the shadow heartbeat value by one.
5. The data processing method according to claim 2, characterized in that: If the shadow heartbeat value is greater than the physical heartbeat value, performing a preset operation according to the physical heartbeat value and the shadow heartbeat value includes: Update the status bits of all the shadow buffers to a read status.
6. The data processing method according to claim 1, characterized in that: After updating the status bits of the plurality of shadow buffers and before determining whether the status bits of all the shadow buffers are in a written state, the method further includes: Determining whether the data cached in the plurality of physical caches and the data cached in the plurality of shadow caches are the same; If they are the same, then executing the step of determining whether the status bits of all the shadow buffers are all in the written state; If they are not the same, the status bits of all the shadow buffers are updated to the read status.
7. The data processing method according to claim 1, characterized in that: The step of performing a read operation on the target shadow buffer to obtain the data to be read includes: Performing a read operation on the target shadow buffer to obtain target data; Determining whether the target data is the same as the data to be read; If they are the same, the target data is determined as the data to be read; If they are not the same, the status bits of all the shadow buffers are updated to the read status.
8. A data processing device, characterized in that: Applied to a system, the system comprising a plurality of physical buffers and a plurality of shadow buffers, including: A receiving unit, used for receiving a data reading instruction for data to be read; A judging unit, used for judging whether the status bits of all the shadow buffers are all in a read state according to the data reading instruction; A synchronization unit, configured to synchronize the data cached in the plurality of physical buffers to the plurality of shadow buffers and update the status bits of the plurality of shadow buffers when the status bits of all the shadow buffers are in a read state; The judging unit is further used to judge whether the status bits of all the shadow buffers are all in the written state; The reading unit is used to perform a read operation on the target shadow buffer when the status bits of all the shadow buffers are in the written state, obtain the data to be read, and update the status bit of the target shadow buffer to the read state. The target shadow buffer is a shadow buffer that caches the data to be read.
9. A data processing device, characterized in that: include: CPU, memory and input / output interface; The memory is a short-term storage memory or a persistent storage memory; The central processing unit is configured to communicate with the memory and execute instructions in the memory to perform the method according to any one of claims 1 to 7.
10. A computer-readable storage medium, characterized in that: The method comprises instructions, which, when executed on a computer, cause the computer to execute the method according to any one of claims 1 to 7.