Memory system and manufacturing method and operation method thereof

Abstract

The embodiment of the invention provides a memory system and a manufacturing method and an operation method thereof. The memory system includes: a plurality of memory banks, each memory bank including a plurality of memory banks; a plurality of memory control logics, each memory control logic coupled to each memory bank in a corresponding memory bank; at least part of the memory libraries in each memory bank are used as shared libraries, and the shared libraries are further coupled to at least one of the other memory control logics adjacent to one memory control logic; the memory system is configured to: complete a configuration of shielding a coupling between at least partially corrupted memory banks in a memory bank and a memory control logic, and selecting a coupling between memory banks in a shared bank corresponding to at least one other memory control logic; therefore, the capacity of the memory system is improved after the configuration is completed.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and relates to but is not limited to a memory system and a manufacturing method and an operating method thereof. Background Art

[0002] The logic chip and multiple memory chips are integrated into a multi-layer stacked chip, and the overall yield of the multi-layer stacked chip is affected by the yield of multiple memories. It is possible that a memory chip in the multi-layer stacked chip does not meet the ratio requirement and becomes a waste chip, resulting in a decrease in the yield of the multi-layer stacked chip, so it is expected to improve the yield of the multi-layer stacked chip. Summary of the invention

[0003] In view of this, embodiments of the present application provide a memory system and a manufacturing method and an operating method thereof.

[0004] In a first aspect, an embodiment of the present application provides a memory system, which includes: multiple memory groups, each memory group includes multiple memory libraries; multiple memory control logics, each memory control logic is coupled to each memory library in a corresponding memory group; at least part of the memory libraries in each memory group are used as shared libraries, and the shared libraries are also coupled to at least one other memory control logic adjacent to the one memory control logic; the memory system is configured to: complete the following configuration, shield the coupling between at least part of the damaged memory libraries in a memory group and a memory control logic, and select the coupling between the memory libraries in the shared library corresponding to at least one other memory control logic; so that the capacity of the memory system is increased after the configuration is completed.

[0005] In some embodiments, the memory system is configured to: shield the coupling between a memory banks out of M damaged memory banks in a memory group and a memory control logic, and select the coupling between a memory banks in a shared bank corresponding to at least one other memory control logic; and / or shield the coupling between b memory banks out of N memory banks in a shared bank of a memory group and a memory control logic; select the coupling between at least one other memory control logic and b memory banks; so that the number of memory banks coupled to a memory control logic and the number of memory banks coupled to at least one other memory control logic are both greater than (4K-M); wherein the maximum number of damaged memory banks in multiple memory groups is M, the number of memory banks in the shared bank is N, the number of memory banks in the memory group is 4K, a≤M, b≤N, 0≤M≤4K, and a, M, N, and K are all natural numbers.

[0006] In some embodiments, each memory group includes a first group and a second group; each memory control logic includes a first logic circuit and a second logic circuit; the first group serves as a shared library and is coupled to the second logic circuit and the first logic circuit of at least one other memory control logic through a multi-way selection circuit; the second group is coupled to the second logic circuit; the first logic circuit is coupled to the shared library corresponding to at least one other memory control logic through a multi-way selection circuit.

[0007] In some embodiments, a plurality of memory groups include a first memory group, a second memory group, and a third memory group; a plurality of memory control logics include a first memory control logic, a second memory control logic, and a third memory control logic; the first memory control logic is coupled to the corresponding first memory group, the second memory control logic is coupled to the corresponding second memory group, and the third memory control logic is coupled to the corresponding third memory group; a shared library is coupled to at least one other memory control logic adjacent to a memory control logic, including: a shared library of a second memory group is coupled to a first memory control logic adjacent to the second memory control logic; wherein a first group of the second memory group is coupled to a second logic circuit of the second memory control logic and a first logic circuit of the first memory control logic through a multiplexer circuit; a second group of the second memory group is coupled to a second logic circuit of the second memory control logic; and the first logic circuit of the second memory control logic is coupled to a plurality of The way selection circuit is coupled to the first group of the third memory group; the memory system is configured to: shield the coupling between a memory banks out of the damaged M memory banks in the second memory group and the second logic circuit of the second memory control logic; select the first logic circuit of the second memory control logic to be coupled to a memory banks in the first group of the third memory group through the multi-way selection circuit; shield the coupling between a memory banks in the first group of the third memory group and the second logic circuit of the third memory control logic; and / or, shield the coupling between b memory banks out of the first group of N memory banks in the second memory group and the second logic circuit of the second memory control logic; select the first logic circuit of the first memory control logic to be coupled to b memory banks in the first group of the second memory group through the multi-way selection circuit; so that the number of memory banks coupled to the first memory control logic, the second memory control logic and the third memory control logic is greater than (4K-M).

[0008] In some embodiments, a plurality of memory groups include a first memory group, a second memory group, and a third memory group; a plurality of memory control logics include a first memory control logic, a second memory control logic, and a third memory control logic; the first memory control logic is coupled to the corresponding first memory group, the second memory control logic is coupled to the corresponding second memory group, and the third memory control logic is coupled to the corresponding third memory group; a shared library is coupled to at least one other memory control logic adjacent to a memory control logic, including: a shared library of the second memory group is coupled to the first memory control logic and / or the third memory control logic adjacent to the second memory control logic; wherein the first group of the second memory group is coupled to the second logic circuit of the second memory control logic, the first logic circuit of the first memory control logic, and the first logic circuit of the third memory control logic through a multiplex selection circuit; the second group of the second memory group is coupled to the second logic circuit of the second memory control logic; the first logic circuit of the second memory control logic is coupled to the first group of the first memory group and the third memory control logic through a multiplex selection circuit. The memory system is configured to: shield the coupling between a memory banks out of the damaged M memory banks in the second memory group and the second logic circuit of the second memory control logic; select the first logic circuit of the second memory control logic to be coupled to a memory banks in the first group of the first memory group and / or the first group of the third memory group through a multiplexer circuit; shield the coupling between a memory banks in the first group of the first memory group and / or the first group of the third memory group and the second logic circuit of the first memory control logic and / or the second logic circuit of the third memory control logic; and / or, shield the coupling between b memory banks out of the first group of N memory banks in the second memory group and the second logic circuit of the second memory control logic; select the first logic circuit of the first memory control logic and / or the first logic circuit of the third memory control logic to be coupled to b memory banks in the first group of the second memory group through a multiplexer circuit; so that the number of memory banks coupled to the first memory control logic, the second memory control logic and the third memory control logic is greater than (4K-M).

[0009] In some embodiments, the number of memory banks in the shared library is positively correlated with yield information; the yield information includes an average of yield values ​​of multiple memory groups; and the yield value includes good or bad information of memory banks in each simulated memory group.

[0010] In some embodiments, the number of memory banks in a shared library ranges from 2 to 2K.

[0011] In some embodiments, the memory system also includes a non-volatile memory; the non-volatile memory is configured to store configuration information; the configuration information includes first configuration information and second configuration information; wherein the first configuration information is used to complete a first configuration; the first configuration includes enabling / enabling non-each memory control logic to be coupled to each memory library in a corresponding memory group; wherein the second configuration information is used to complete a second configuration; the second configuration includes selecting a shared library to be coupled to a memory control logic, or selecting a shared library to be coupled to a memory control logic in at least one other memory control logic adjacent to the memory control logic.

[0012] In some embodiments, the memory system also includes a remapping register and a multiplexer register; the memory system is also configured to: in response to startup of the memory system, read first configuration information and second configuration information from the non-volatile memory; write the first configuration information and the second configuration information into the remapping register and the multiplexer register, respectively; complete the first configuration according to the first configuration information stored in the remapping register, and complete the second configuration according to the second configuration information stored in the multiplexer register.

[0013] In some embodiments, a memory system includes a logic chip and multiple memory chips stacked on the logic chip and interconnected with the logic chip; wherein the logic chip includes multiple memory control logics; wherein the multiple memory chips include multiple memory groups; each memory chip includes multiple memory libraries; each memory group includes one or more memory libraries in each memory chip.

[0014] In a second aspect, an embodiment of the present application provides a method for manufacturing a memory system, the manufacturing method comprising: providing a multi-layer stacked chip; the multi-layer stacked chip comprises a logic chip and a plurality of memory chips stacked on the logic chip and interconnected with the logic chip; wherein the logic chip comprises a plurality of memory control logics; wherein the plurality of memory chips comprises a plurality of memory groups; each memory chip comprises a plurality of memory libraries; each memory group comprises one or more memory libraries in each memory chip; a plurality of memory groups, each memory group comprises a plurality of memory libraries; a plurality of memory control logics, each memory control logic is coupled to each memory library in a corresponding memory group; at least part of the memory libraries in each memory group are used as shared libraries, and the shared libraries are also coupled to at least one other memory control logic adjacent to a memory control logic; testing the multi-layer stacked chip to generate yield information of the multi-layer stacked chip; the yield information comprises the memory libraries in each memory group library; generate and export configuration information according to whether the yield information satisfies preset conditions; the configuration information includes first configuration information and second configuration information; wherein the first configuration information is used to complete the first configuration; the first configuration includes enabling / enabling non-each memory control logic to be coupled to each memory library in a corresponding memory group; wherein the second configuration information is used to complete the second configuration; the second configuration includes selecting a shared library to be coupled to a memory control logic, or selecting a shared library to be coupled to a memory control logic in at least one other memory control logic adjacent to a memory control logic; write the configuration information into the non-volatile memory of the multi-layer stacked chip; the first configuration information of the non-volatile memory is used to complete the first configuration, and the second configuration information stored in the non-volatile memory is used to complete the second configuration, so that the yield of the multi-layer stacked chip after completing the first configuration and the second configuration is greater than the yield of the multi-layer stacked chip before completing the first configuration and the second configuration.

[0015] In some embodiments, the multi-layer stacked chip is tested to generate yield information of the multi-layer stacked chip, including: performing a memory built-in self-test on the multi-layer stacked chip to generate fail bit data for each memory bank; based on the fail bit data of each memory bank, using offline software to calculate and generate good or bad information for each memory bank; based on the good or bad information of each memory bank, generating good or bad information for each memory group; based on the good or bad information of each memory group, generating yield information of the multi-layer stacked chip.

[0016] In some embodiments, configuration information is generated and exported based on the yield information satisfying preset conditions, including: using an offline software algorithm to calculate an optimal allocation algorithm based on the yield information satisfying preset conditions; generating configuration information based on successful calculation of the optimal allocation algorithm; and exporting the configuration information.

[0017] In some embodiments, according to the yield information not satisfying the preset conditions, the configuration information adopts the default configuration; or, according to the calculation failure of the optimal allocation algorithm, the multi-layer stacked chip is marked as a waste chip.

[0018] In a third aspect, an embodiment of the present application provides an operating method of a memory system, the operating method comprising: starting the memory system; wherein the memory system comprises a plurality of memory groups and a plurality of memory control logics; each memory group comprises a plurality of memory libraries; each memory control logic is coupled to each memory library in a corresponding memory group; at least part of the memory libraries in each memory group are used as shared libraries, and the shared libraries are also coupled to at least one other memory control logic adjacent to a memory control logic; in response to starting the memory system, reading configuration information from a non-volatile memory of the memory system; the configuration information comprises first configuration information and second configuration information; wherein the first configuration information is used to complete a first configuration; the first configuration comprises enabling / enabling non-volatile memory of each storage The device control logic is coupled to each memory bank in a corresponding memory group; wherein the second configuration information is used to complete the second configuration; the second configuration includes selecting the shared bank to be coupled to a memory control logic, or selecting the shared bank to be coupled to a memory control logic in at least one other memory control logic adjacent to the memory control logic; writing the first configuration information and the second configuration information into a remapping register and a multiplexer select register of the memory system respectively; completing the first configuration according to the first configuration information stored in the remapping register, and completing the second configuration according to the second configuration information stored in the multiplexer select register, so that the yield of the memory system after completing the first configuration and the second configuration is greater than the yield of the memory system before completing the first configuration and the second configuration.

[0019] In each embodiment of the present application, at least part of the memory libraries in each memory group serve as shared libraries, and the memory libraries in the shared libraries can be shared between adjacent memory groups, so that the memory system can maximize the capacity of the memory group of each system unit by shielding the coupling between at least part of the damaged memory libraries in a memory group and a memory control logic, and selecting the coupling between the memory libraries in the shared libraries corresponding to at least one other memory control logic, thereby facilitating the use of the memory system and improving the yield of the memory system. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 A three-dimensional schematic diagram of a multi-layer stacked chip;

[0021] Figure 2 for Figure 1 A planar schematic diagram of a mapping relationship between partial circuits of a multi-layer stacked chip;

[0022] Figure 3A three-dimensional schematic diagram of a memory system including a logic chip and a plurality of stacked memory chips provided in an embodiment of the present application;

[0023] Figure 4 for Figure 3 A planar schematic diagram of a mapping relationship between various circuit components of a system unit;

[0024] Figure 5 for Figure 3 A planar schematic diagram of a mapping relationship between various circuit components of a plurality of system units;

[0025] Figure 6 A planar schematic diagram of a mapping relationship between various circuit components of multiple system units of another memory system provided by an embodiment of the present application;

[0026] Figure 7 A schematic diagram of detailed operation steps of a method for manufacturing a memory system provided in an embodiment of the present application;

[0027] Figure 8 A flowchart of an operating method of a memory system provided in an embodiment of the present application. DETAILED DESCRIPTION

[0028] The following is a clear and complete description of the technical solutions in the embodiments of the present application in combination with the embodiments of the present application and the accompanying drawings. The described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0029] In the following description, a large number of specific details are given to provide a more thorough understanding of the present application. However, it is obvious to those skilled in the art that the present application can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present application, some technical features known in the art are not described; that is, all features of the actual embodiments are not described here, and well-known functions and structures are not described in detail.

[0030] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0031] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present application, the first element, component, region, layer or part discussed below can be represented as the second element, component, region, layer or part. And when the second element, component, region, layer or part is discussed, it does not indicate that the present application necessarily has the first element, component, region, layer or part.

[0032] Spatially relative terms such as "under", "beneath", "below", "under", "above", "above", etc., may be used here for convenience of description to describe the relationship between an element or feature shown in the figure and other elements or features. It should be understood that in addition to the orientation shown in the figure, the spatial relationship terms are intended to also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is turned over, then the elements or features described as "under other elements" or "under it" or "under it" will be oriented as "on" other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device can be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0033] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be limiting of the present application. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0034] In order to thoroughly understand the present application, detailed steps and detailed structures will be presented in the following description to illustrate the technical solution of the present application. The preferred embodiments of the present application are described in detail below, but in addition to these detailed descriptions, the present application may also have other implementation methods.

[0035] Figure 1 A three-dimensional schematic diagram of a multi-layer stacked chip. Figure 2 for Figure 1 A planar schematic diagram of the mapping relationship between partial circuits of a multi-layer stacked chip.

[0036] refer to Figure 1 and Figure 2 , a multi-layer stacked chip 10, such as a three-dimensional (3D) dynamic random access memory (Dynamic Random Access Memory, DRAM), can integrate at least one logic chip 100 and multiple memory chips 200 (for example, including a first memory chip 201, a second memory chip 202, a third memory chip 203, and a fourth memory chip 204) into a multi-layer stacked chip (hereinafter also referred to as a memory system) 10 through a hybrid bonding (HB) process and a through silicon via (TSV) technology. The overall yield of the multi-layer stacked chip 10 is affected by the yield of multiple memory chips 200. The multi-layer stacked chip 10 includes multiple system units, for example, a system unit 10-1 composed of a memory control logic 100-1 and a memory group 200-1, and another system unit 10-N composed of a memory control logic 100-N and a memory group 200-N. The capacity of the memory group of each system unit affects the yield of the memory system. It should be noted that, Figure 1 and Figure 2 Components / layers / materials / structures marked with the same reference numerals may refer to Figure 3 and Figure 4 The same or familiar parts / layers / materials / structures can be understood for reference only and will not be described in detail here.

[0037] The capacity of the memory group corresponding to the memory control logic may be different, and the memory system is not easy to use. The memory system requires that each memory control logic has the same storage space, that is, each memory control logic corresponds to the same number of memory banks. In production, the defect of the memory bank (bad memory bank) is inevitable. In order to ensure that each memory control logic has the same storage space (corresponding to the same number of good memory banks), all are used according to the lowest storage space (corresponding to the minimum number of good memory banks in the memory group after removing the bad memory bank), resulting in a decrease in the available capacity of the memory group corresponding to the memory control logic. For example, the memory group 200-1 corresponding to the memory control logic 100-1 does not meet the ratio requirement, even if the other memory groups meet the ratio requirement (for example, the memory group 200-N corresponding to the memory control logic 100-N meets the ratio requirement), resulting in a decrease in the available capacity of the memory group corresponding to the memory control logic, making the multi-layer stacked chip a waste. That is to say, due to the defective memory groups corresponding to the memory control logic, at the memory system level, it may be seen that the memory groups corresponding to the memory control logic have different capacities (or storage spaces). It is possible that the memory groups of a memory chip cannot meet the proportion requirements and the multi-layer stacked chips are waste, thereby resulting in a decrease in the yield of the multi-layer stack.

[0038] In view of this, an embodiment of the present application provides a memory system and a manufacturing method and an operating method thereof, in which at least part of the memory libraries in each memory group are used as shared libraries. The memory libraries in the shared libraries can be shared between adjacent memory groups, so that the available capacity of the memory groups of each system unit is maximized, which facilitates the use of the memory system and improves the yield of the memory system.

[0039] Figure 3 A three-dimensional schematic diagram of a memory system including a logic chip and a plurality of stacked memory chips provided in an embodiment of the present application. Figure 4 for Figure 3 A planar schematic diagram of the mapping relationship between various circuit components of a system unit.

[0040] refer to Figure 3 and Figure 4In a first aspect, an embodiment of the present application provides a memory system 12, which includes: a plurality of memory groups, each memory group includes a plurality of memory libraries; a plurality of memory control logics, each memory control logic is coupled to each memory library in a corresponding memory group; at least part of the memory libraries in each memory group are used as shared libraries, and the shared libraries are also coupled to at least one other memory control logic adjacent to a memory control logic; the memory system is configured to: complete the following configuration, shield the coupling between at least part of the damaged memory libraries in a memory group and a memory control logic, and select the coupling between the memory libraries in the shared library corresponding to at least one other memory control logic; so that the capacity of the memory system is increased after the configuration is completed.

[0041] For the convenience of describing the present application, the first direction and the second direction in each embodiment of the present application are represented as two orthogonal directions extending from the top surface / bottom surface of the memory system, and the third direction is a direction perpendicular to the top surface / bottom surface of the memory system, which can be understood as the stacking direction of multiple chips of the memory system. The first direction is represented as the X direction in the accompanying drawings; the second direction is represented as the Y direction in the accompanying drawings; and the third direction is represented as the Z direction in the accompanying drawings.

[0042] The term "shared library" includes a plurality of sharable memory libraries, each sharable memory library is coupled to a corresponding memory control logic, and can also be coupled to at least one other memory control logic adjacent to a memory control logic. The term "adjacent" can be understood as physically adjacent to each other, for example, referring to Figure 3 , a memory control logic 100-1 and another memory control logic 100-2 are adjacent to each other in position; or they can be logically connected to each other, for example, refer to Figure 4 , a memory control logic 100-1 is connected to another memory control logic 100-N in a connection relationship. The term "damaged memory bank" can be understood as a bad memory bank in a memory group marked by a memory built-in self-test (MBIST), or a memory bank in a shared library provided to an adjacent memory bank after completing the following configuration (it can also be understood as a shielded memory bank). The term "capacity of a memory group" can be understood as the storage capacity of a good memory bank in a memory group, and the higher the value, the larger the capacity; it can also be understood as the storage capacity of a damaged memory bank in a memory group, and the higher the value, the smaller the capacity. The term "yield of a memory group" can be understood as the number or proportion of good memory banks in a memory group, and the higher the value, the better the yield; it can also be understood as the number or proportion of damaged memory banks in a memory group, and the higher the value, the worse the yield.

[0043] In an embodiment of the present application, at least part of the memory libraries in each memory group serve as shared libraries, and the memory libraries in the shared libraries can be shared between adjacent memory groups, so that the memory system can maximize the capacity of the memory group of each system unit by shielding the coupling between at least part of the damaged memory libraries in a memory group and a memory control logic, and selecting the coupling between the memory libraries in the shared libraries corresponding to at least one other memory control logic, thereby facilitating the use of the memory system and improving the yield of the memory system.

[0044] refer to Figure 3 and Figure 4 In some embodiments, a memory system includes a logic chip and a plurality of memory chips stacked on the logic chip and interconnected with the logic chip; wherein the logic chip includes a plurality of memory control logics; wherein the plurality of memory chips include a plurality of memory groups; each memory chip includes a plurality of memory libraries; each memory group includes one or more memory libraries in each memory chip.

[0045] The memory system 12 includes a plurality of system units, for example, the memory control logic 100-1 and the memory group 200-1 constitute a system unit 12-1, and the memory control logic 100-N and the memory group 200-N constitute another system unit 12-N. The logic chip 100 may be, for example, a central processing unit (CPU), a digital signal processor (DSP), a field programmable gate array (FPGA), a microcontroller unit (MCU), or an application specific integrated circuit (ASIC). The memory chip 200 may be a volatile memory chip, such as a dynamic random access memory chip. In some embodiments, the plurality of memory chips may include 4 stacked layers, and the capacity may support 12 gigabytes (GB) to 16GB, which is not limited to this range, and may also be less than 12GB or greater than 16GB. The plurality of memory chips may also include any number of stacked layers lower or higher than 4 layers. In some embodiments, the logic chip 100 of the memory system 12 is a DRAM control logic (DRAM Memory Controller, DMC), the memory chip 200 of the memory system 12 is a DRAM unit, and the memory system 12 can constitute a high bandwidth memory (High Bandwidth Memory, HBM) DRAM. The DRAM DMC can control the DRAM unit and is configured to store data to the DRAM unit, read data stored in the DRAM unit, or refresh the data stored in the DRAM unit.

[0046] refer to Figure 3 , the logic chip 100 includes a plurality of memory control logics, each memory control logic controls a corresponding memory group, and a memory group includes a plurality of memory banks from a plurality of memory chips 200. For example, a memory control logic 100-1 controls a corresponding memory group 200-1, and a memory group 200-1 includes a partial area 201-1 from a first memory chip 201, a partial area 202-1 from a second memory chip 202, a partial area 203-1 from a third memory chip 203, and a partial area 204-1 from a fourth memory chip 204.

[0047] refer to Figure 4In some embodiments, the production of the memory system may have a yield loss, which is based on memory banks. For example, the memory system includes hundreds to thousands of memory banks. Exemplarily, the memory group 200-1 includes 16 memory banks, namely, four memory banks stack0 macro0, stack0 macro1, stack0 macro2, and stack0 macro3 in the partial area 201-1 of the first memory chip 201, four memory banks stack1 macro0, stack1 macro1, stack1 macro2, and stack1 macro3 in the partial area 202-1d of the second memory chip 202, four memory banks stack2 macro0, stack2 macro1, stack2macro2, and stack2macro3 in the partial area 203-1 of the third memory chip 203, and four memory banks stack3macro0, stack3 macro1, stack3 macro2, and stack3 macro3 in the partial area 204-1 of the fourth memory chip 204. The number of memory banks included in a memory group is not limited to 16, and may also include a number lower or higher than 16, such as 4, 8, 12 or 20. In some embodiments, each memory control logic includes 16 memory bank control circuits Bank0 to Bank15 that independently enable each memory bank in the memory group 200-1, and 4 memory bank control circuits Bank16 to Bank19 that are mapped to each memory bank in the shared library with the adjacent memory control logic 100-2. Exemplarily, the memory system includes 1 logic chip and 4 stacked memory chips, 1 logic chip includes 40 memory control logics, 1 memory chip includes 160 memory banks, 1 logic chip controls the corresponding 1 memory group, and 1 memory group includes 16 memory banks. In some embodiments, the minimum number of good memory banks in the 1 memory group controlled by 1 logic chip can be set, such as not less than 14; or the maximum number of bad memory banks in the 1 memory group controlled by 1 logic chip can be set, such as not more than 2.

[0048] In some embodiments, the memory library can be shared between adjacent memory groups, and the adjacent shared memory groups and the shared memory groups can be located in the same memory chip, for example, in the first memory chip 201; or, respectively located in different memory chips, for example, respectively located in the first memory chip 201 and the second memory chip 202.

[0049] refer to Figure 4In some embodiments, the memory system is configured to: shield the coupling between a memory banks among M damaged memory banks in a memory group and a memory control logic, and select the coupling between a memory banks in a shared library corresponding to at least one other memory control logic; and / or shield the coupling between b memory banks among N memory banks in a shared library of a memory group and a memory control logic; select the coupling between at least one other memory control logic and b memory banks; so that the number of memory banks coupled to a memory control logic and the number of memory banks coupled to at least one other memory control logic are both greater than (4K-M); wherein the maximum number of damaged memory banks in multiple memory groups is M, the number of memory banks in the shared library is N, the number of memory banks in the memory group is 4K, a≤M, b≤N, 0≤M≤4K, and a, M, N, and K are all natural numbers.

[0050] In some embodiments, an offline software algorithm can be used to calculate the optimal allocation algorithm. If the optimal allocation algorithm is successfully calculated, the yield of the memory system meets the requirements, and the memory groups corresponding to each memory control logic in the memory system meet the ratio requirements; if the optimal allocation algorithm cannot be successfully calculated, the memory groups in the memory system that do not meet the yield requirements are marked as not scrapped. The constraints of the optimal allocation algorithm include but are not limited to the following: 1. The yield of the memory system meets the requirements, and the number of damaged memory libraries in each memory group does not exceed the upper limit value; 2. The configurability of the memory group requires that after requesting at least part of the memory libraries in the shared library from the adjacent memory group, the number of damaged memory libraries in the memory group can still meet the requirement that the number of damaged memory libraries in the memory group does not exceed the upper limit value; 3. The shareability of the memory group requires that the value of the upper limit value minus the number of damaged memory libraries in the memory group is greater than zero. Among them, if the number of damaged memory libraries in the memory group does not exceed the upper limit value (for example, 2), the number of sharable memory libraries in the memory group is defined as the upper limit value minus the number of damaged memory libraries in the memory group (for example, 1) and is greater than zero, for example, the sharable space of the memory group is 1 (2-1=1). After requesting all the memory libraries in the shared library from the adjacent memory group, the requirement that the number of damaged memory libraries does not exceed the upper limit value still cannot be met, and the memory library is defined as non-configurable; conversely, after requesting at least part of the memory libraries in the shared library from the adjacent memory group, the requirement that the number of damaged memory libraries does not exceed the upper limit value can be met, and the memory library is defined as configurable.

[0051] In some examples, the memory group 200-1 corresponding to the memory control logic 100-1 fails to meet the ratio requirement. For example, the memory group 200-1 includes 3 damaged memory banks, and the memory groups corresponding to other adjacent memory control logics meet the ratio requirement (for example, the number of damaged memory banks included in the memory group does not exceed 2) and the memory group is configurable. The memory control logic 100-1 can borrow a memory bank from the adjacent shared bank, so that the number of damaged memory banks included in the memory group 200-1 is reduced from 3 to 2, and the number of damaged memory banks included in the adjacent memory group is increased by 1 (no more than 2 at most). For the entire memory system, the number of damaged memory banks is reduced from 3 to 2, so that the yield of the memory system is changed from failing to meet the ratio requirement to meeting the ratio requirement, thereby increasing the minimum available capacity of the memory group and thereby improving the yield of the memory system.

[0052] In other examples, the memory group 200-1 corresponding to the memory control logic 100-1 meets the ratio requirement (for example, the number of damaged memory libraries included in the memory group does not exceed 2) and the memory group is configurable, and the memory groups corresponding to other adjacent memory control logics do not meet the ratio requirement (for example, the number of damaged memory libraries included in the memory group exceeds 2). The memory control logic 100-1 can provide at least one memory library to the adjacent shared library, so that the adjacent memory groups and the memory group 200-1 both meet the ratio requirement (the number of damaged memory libraries included does not exceed 2), and for the entire memory system, the number of damaged memory libraries is reduced to no more than 2, so that the yield of the memory system is changed from failing to meet the ratio requirement to meeting the ratio requirement, thereby increasing the minimum available capacity of the memory group and thereby improving the yield of the memory system.

[0053] refer to Figure 4 or Figure 6 In some embodiments, each memory group includes a first group and a second group; each memory control logic includes a first logic circuit and a second logic circuit; the first group serves as a shared library and is coupled to the second logic circuit and the first logic circuit of at least one other memory control logic through a multiplexer circuit; the second group is coupled to the second logic circuit; the first logic circuit is coupled to the shared library corresponding to at least one other memory control logic through a multiplexer circuit.

[0054] The first group serves as a shared library of the memory group 200-1, the second group includes other memory libraries in the memory group 200-1 excluding the shared library, the second logic circuit includes a corresponding memory library control circuit that independently enables each memory library in the memory group 200-1, and the first logic circuit includes a corresponding memory library control circuit that is mapped to each memory library in the shared library with the adjacent memory control logic 100-2.

[0055] refer to Figure 4 , exemplarily, the first group includes 4 memory banks stack0 macro0, stack1 macro0, stack2macro0 and stack3 macro0, the second group includes the other 12 memory banks in the memory group 200-1 excluding the shared bank, the second logic circuit includes 16 memory bank control circuits Bank0~Bank15 that independently enable each memory bank in the memory group 200-1, and the first logic circuit includes 4 memory bank control circuits Bank16~Bank19 mapped to each memory bank in the shared bank with the adjacent memory control logic 100-2.

[0056] refer to Figure 7 , exemplarily, the first group includes 4 memory banks stack0 macro0, stack1 macro0, stack2macro0 and stack3 macro0, the second group includes the other 12 memory banks in the memory group 200-1 excluding the shared bank, the second logic circuit includes 16 memory bank control circuits Bank0~Bank15 that independently enable each memory bank in the memory group 200-1, and the first logic circuit includes 8 memory bank control circuits Bank16~Bank19, Bank20~Bank23 that are mapped to each memory bank in the shared bank with the adjacent memory control logic 100-2.

[0057] In some embodiments, the number of memory banks in the shared library is positively correlated with yield information; the yield information includes an average of yield values ​​of multiple memory groups; and the yield value includes good or bad information of memory banks in each simulated memory group.

[0058] In some embodiments, the number of memory banks in a shared library ranges from 2 to 2K.

[0059] refer to Figure 4In some embodiments, no more than 1 / 2 of the memory banks in the memory group 200-1 serve as shared banks. Preferably, 1 / 2, 1 / 3, and 1 / 4 of the memory banks in the memory group 200-1 can serve as shared banks. Exemplarily, 4 of the 16 memory banks included in the memory group 200-1 can serve as shared banks, namely, a memory bank stack0 macro0 in the partial area 201-1 of the first memory chip 201, a memory bank stack1 macro0 in the partial area 202-1d of the second memory chip 202, a memory bank stack2 macro0 in the partial area 203-1 of the third memory chip 203, and a memory bank stack3 macro0 in the partial area 204-1 of the fourth memory chip 204; wherein, the memory banks stack0 macro0, stack1 macro0, stack2 macro0, and stack3 macro0 can be coupled to a corresponding memory control logic 100-1, and also coupled to another memory control logic 100-N adjacent to the memory control logic 100-1.

[0060] In some embodiments, the proportion of shared libraries in a memory group may be a default value or an empirical value; the default value or empirical value may be obtained through a large number of simulation experiments. In some embodiments, the proportion of shared libraries in a memory group may be selected according to different yield conditions of the memory system. For example, the higher the yield of the memory system, the lower the proportion of shared libraries in the memory group. A typical value of the proportion of shared libraries in a memory group may be 1 / 4.

[0061] In some embodiments, the memory control logic 100-1 includes a memory bank control circuit mapped to each memory bank in the memory group 200-1, and a memory bank control circuit mapped to each memory bank in a shared bank with an adjacent memory control logic 100-2. Figure 4 , exemplarily, the memory control logic 100-1 can independently enable each memory bank, including 16 memory bank control circuits Bank0 to Bank15 mapped to 16 memory banks in a memory group, and the shared bank ( Figure 4 4 memory bank control circuits Bank16 to Bank19 (not shown). Figure 6 , exemplarily, the memory control logic 100-1 includes 16 memory bank control circuits Bank0 to Bank15 mapped to 16 memory banks in a memory group, and a shared bank ( Figure 64 memory bank control circuits Bank16 to Bank19 of the memory control logic 100-1 (not shown), and 4 memory bank control circuits Bank20 to Bank23 of the shared bank mapped to the memory control logic 100-2.

[0062] refer to Figure 5 In some embodiments, the plurality of memory groups include a first memory group 200-1, a second memory group 200-2, and a third memory group 200-3; the plurality of memory control logics include a first memory control logic 100-1, a second memory control logic 100-2, and a third memory control logic 100-3; the first memory control logic 100-1 is coupled to the corresponding first memory group 200-1, the second memory control logic 100-2 is coupled to the corresponding second memory group 200-2, and the third memory control logic 100-3 is coupled to the corresponding third memory group 200-3; The shared library is coupled to at least one other memory control logic adjacent to a memory control logic, including: the shared library of the second memory group 200-2 is coupled to the first memory control logic 100-1 adjacent to the second memory control logic 100-2; wherein the first group of the second memory group 200-2 is coupled to the second logic circuit of the second memory control logic 100-2 and the first logic circuit of the first memory control logic 100-1 through a multiplexer circuit; the second group of the second memory group 200-2 is coupled to the second logic circuit of the second memory control logic 100-2; the second memory control The first logic circuit of the control logic 100-2 is coupled to the first group of the third memory group 200-3 through the multi-way selection circuit; the memory system is configured to: shield the coupling between a memory banks among the damaged M memory banks in the second memory group 200-2 and the second logic circuit of the second memory control logic 100-2; select the first logic circuit of the second memory control logic 100-2 to be coupled to a memory banks in the first group of the third memory group 200-3 through the multi-way selection circuit; shield the a memory banks in the first group of the third memory group 200-3 and the third memory control logic 100-2; 00-3; and / or, shielding the coupling between b memory banks in the first group of N memory banks of the second memory group 200-2 and the second logic circuit of the second memory control logic 100-2; selecting the first logic circuit of the first memory control logic 100-1 to be coupled to b memory banks in the first group of the second memory group 200-2 through a multi-way selection circuit; so that the number of memory banks coupled to the first memory control logic 100-1, the second memory control logic 100-2 and the third memory control logic 100-3 is greater than (4K-M).

[0063] That is, the second memory group 200-2 of the system unit 12-2 may request the memory bank in the shared pool from the third memory group 200-3 of the system unit 12-3, and / or the second memory group 200-2 may contribute the memory bank in the shared pool to the first memory group 200-1 of the system unit 12-1.

[0064] In some embodiments, the multiplexer circuit includes a 2-1MUX. For example, the first group of the second memory group 200-2 is coupled to the second logic circuit of the second memory control logic 100-2 and the first logic circuit of the first memory control logic 100-1 through the 2-1MUX; the first logic circuit of the second memory control logic 100-2 is coupled to the first group of the third memory group 200-3 through the 2-1MUX.

[0065] In some examples, the yield of the memory system meets the requirements, and the memory group 200-1 corresponding to each memory control logic 100-1 in the memory system needs to meet the ratio requirements, for example, the number of damaged memory libraries included in each memory group does not exceed 2 as an example; wherein, the number of memory libraries not exceeding the number of memory libraries in the shared library (4) is taken as an example, for example, the number of damaged memory libraries included in the first memory group 200-1 is 3, and the number of damaged memory libraries included in the second memory group 200-2 and the third memory group 200-3 are both 0.

[0066] As shown in Table 1 below, after one iteration, one of the four memory libraries in the shared library of the second memory group 200-2 is provided to the first memory group 200-1 for use, the number of damaged memory libraries included in the first memory group 200-1 changes from 3 to 2, the number of damaged memory libraries included in the second memory group 200-2 changes from 0 to 1, and the number of damaged memory libraries included in the third memory group 200-3 remains 0; at the end of the iteration, the yield of the memory system meets the requirements, and the number of damaged memory libraries included in the memory system as a whole is 2.

[0067] Table 1

[0068]

[0069] As shown in Table 2 below, after one iteration, two of the four memory banks in the shared library of the second memory group 200-2 are provided to the first memory group 200-1 for use, the number of damaged memory banks included in the first memory group 200-1 changes from three to one, the number of damaged memory banks included in the second memory group 200-2 changes from zero to two, and the number of damaged memory banks included in the third memory group 200-3 remains zero; at the end of the iteration, the yield of the memory system meets the requirements, and the number of damaged memory banks included in the memory system as a whole is two.

[0070] Table 2

[0071]

[0072] As shown in Table 3 below, through the first iteration, two of the four memory banks in the shared library of the second memory group 200-2 are provided to the first memory group 200-1 for use, the number of damaged memory banks included in the first memory group 200-1 changes from three to one, the number of damaged memory banks included in the second memory group 200-2 changes from zero to two, and the number of damaged memory banks included in the third memory group 200-3 remains zero; through the second iteration, one of the four memory banks in the shared library of the third memory group 200-3 is provided to the first memory group 200-1 for use, the number of damaged memory banks included in the first memory group 200-1 changes from three to two, the number of damaged memory banks included in the second memory group 200-2 changes from zero to two, and the number of damaged memory banks included in the third memory group 200-3 remains zero; through the second iteration, one of the four memory banks in the shared library of the third memory group 200-3 is provided to the first memory group 200-1 for use. The second memory group 200-2 is used, and the number of damaged memory banks included in the second memory group 200-2 changes from 2 to 1, and the number of damaged memory banks included in the third memory group 200-3 changes from 0 to 1, and the number of damaged memory banks included in the first memory group 200-1 is still 1; at the end of the iteration, the yield of the memory system meets the requirement and is optimal, and the number of damaged memory banks included in the memory system as a whole is 1. Compared with the yields of the memory systems shown in Tables 1 and 2, the yield of the memory system shown in Table 3 is improved.

[0073] Table 3

[0074]

[0075] In other examples, taking the number of memory libraries exceeding the shared library (4) as an example, for example, the number of damaged memory libraries included in the first memory group 200-1 is 5, and the number of damaged memory libraries included in the second memory group 200-2 and the third memory group 200-3 are both 0.

[0076] As shown in Table 4 below, after 2 iterations, the number of damaged memory banks included in the first memory group 200-1 changes from 5 to 2, the number of damaged memory banks included in the second memory group 200-2 changes from 0 to 2, and the number of damaged memory banks included in the third memory group 200-3 changes from 0 to 1; at the end of the iteration, the yield of the memory system meets the requirements, and the number of damaged memory banks included in the memory system as a whole is 2.

[0077] Table 4

[0078]

[0079] As shown in Table 5 below, after 2 iterations, the number of damaged memory banks included in the first memory group 200-1 changes from 5 to 2, the number of damaged memory banks included in the second memory group 200-2 changes from 0 to 1, and the number of damaged memory banks included in the third memory group 200-3 changes from 0 to 2; at the end of the iteration, the yield of the memory system meets the requirements, and the number of damaged memory banks included in the memory system as a whole is 2.

[0080] Table 5

[0081]

[0082] As shown in Table 6 below, after 2 iterations, the number of damaged memory banks included in the first memory group 200-1 changes from 5 to 1, the number of damaged memory banks included in the second memory group 200-2 changes from 0 to 2, and the number of damaged memory banks included in the third memory group 200-3 changes from 0 to 2; at the end of the iteration, the yield of the memory system meets the requirements, and the number of damaged memory banks included in the memory system as a whole is 2.

[0083] Table 6

[0084]

[0085] In some further examples, as shown in Table 7 below, after four iterations, the number of damaged memory banks included in the first memory group 200-1 changes from 5 to 1, the number of damaged memory banks included in the second memory group 200-2 changes from 0 to 1, the number of damaged memory banks included in the third memory group 200-3 changes from 0 to 1, and the number of damaged memory banks included in the fourth memory group 200-4 changes from 0 to 1. Figure 5 The number of damaged memory banks contained in the fifth memory group (not shown) changes from 0 to 1, and the fifth memory group ( Figure 5The number of damaged memory banks contained in Table 7 (not shown) changes from 0 to 1; at the end of the iteration, the yield of the memory system meets the requirement and is optimal, and the number of damaged memory banks contained in the memory system as a whole is 1. Compared with the yields of the memory systems shown in Tables 4, 5, and 6, the yield of the memory system shown in Table 7 is improved.

[0086] Table 7

[0087]

[0088] refer to Figure 6In some embodiments, the plurality of memory groups include a first memory group 200-1, a second memory group 200-2, and a third memory group 200-3; the plurality of memory control logics include a first memory control logic 100-1, a second memory control logic 100-2, and a third memory control logic 100-3; the first memory control logic 100-1 is coupled to the corresponding first memory group 200-1, the second memory control logic 100-2 is coupled to the corresponding second memory group 200-2, and the third memory control logic 100-3 is coupled to the corresponding third memory group 200-3; the shared library is coupled to at least one other memory control logic adjacent to a memory control logic, including: The shared library of the second memory group 200-2 is coupled to the first memory control logic 100-1 and / or the third memory control logic 100-3 adjacent to the second memory control logic 100-2; wherein the first group of the second memory group 200-2 is coupled to the second logic circuit of the second memory control logic 100-2, the first logic circuit of the first memory control logic 100-1, and the first logic circuit of the third memory control logic 100-3 through a multiplexer circuit; the second group of the second memory group 200-2 is coupled to the second logic circuit of the second memory control logic 100-2; the first logic circuit of the second memory control logic 100-2 is coupled to the first memory control logic 100-2 through a multiplexer circuit. The memory system is configured to: shield the coupling between a memory banks among the damaged M memory banks in the second memory group 200-2 and the second logic circuit of the second memory control logic 100-2; select the first logic circuit of the second memory control logic 100-2 to be coupled to the first group of the first memory group 200-1 and / or the first group of the third memory group 200-3 through the multiplexer selection circuit; shield the a memory banks among the first group of the first memory group 200-1 and / or the first group of the third memory group 200-3 and the second logic circuit of the first memory control logic 100-1 and / or the first logic circuit of the first memory control logic 100-1 and / or the first logic circuit of the third memory group 200-3 or the coupling between the second logic circuit of the third memory control logic 100-3; and / or, shielding the coupling between b memory banks in the first group of N memory banks of the second memory group 200-2 and the second logic circuit of the second memory control logic 100-2; selecting the first logic circuit of the first memory control logic 100-1 and / or the first logic circuit of the third memory control logic 100-3 to be coupled to b memory banks in the first group of the second memory group 200-2 through a multi-way selection circuit; so that the number of memory banks coupled to the first memory control logic 100-1, the second memory control logic 100-2 and the third memory control logic 100-3 is greater than (4K-M).

[0089] That is, the second memory group 200-2 of the system unit 12-2 can request the memory library in the shared library from the first memory group 200-1 of the system unit 12-1 and / or the third memory group 200-3 of the system unit 12-3, and / or the second memory group 200-2 of the system unit 12-2 can contribute the memory library in the shared library to the first memory group 200-1 of the system unit 12-1 and / or the third memory group 200-3 of the system unit 12-3.

[0090] In some embodiments, the multiplexing circuit includes a three-to-one multiplexer (3-1MUX). For example, the first group of the second memory group 200-2 is coupled to the second logic circuit of the second memory control logic 100-2, the first logic circuit of the first memory control logic 100-1, and the first logic circuit of the third memory control logic 100-3 through the three-to-one multiplexer; the first logic circuit of the second memory control logic 100-2 is coupled to the first group of the first memory group 200-1 and the first group of the third memory group 200-3 through the three-to-one multiplexer.

[0091] In some examples, the yield of the memory system meets the requirements, and the memory groups corresponding to each memory control logic in the memory system need to meet the ratio requirements, for example, the number of damaged memory libraries included in each memory group does not exceed 2 as an example; wherein, the number of memory libraries not exceeding 4 in the shared library is taken as an example, for example, the number of damaged memory libraries included in the second memory group 200-2 is 3, and the number of damaged memory libraries included in the first memory group 200-1 and the third memory group 200-3 are both 0.

[0092] As shown in Table 8 below, after 1 iteration, the number of damaged memory libraries included in the first memory group 200-1 changes from 0 to 1, the number of damaged memory libraries included in the second memory group 200-2 changes from 3 to 2, and the number of damaged memory libraries included in the third memory group 200-3 is still 0; at the end of the iteration, the yield of the memory system meets the requirements, and the number of damaged memory libraries included in the memory system as a whole is 2.

[0093] Table 8

[0094]

[0095] As shown in Table 9 below, after 1 iteration, the number of damaged memory libraries included in the first memory group 200-1 is still 0, the number of damaged memory libraries included in the second memory group 200-2 changes from 3 to 2, and the number of damaged memory libraries included in the third memory group 200-3 changes from 0 to 1; at the end of the iteration, the yield of the memory system meets the requirements, and the number of damaged memory libraries included in the memory system as a whole is 2.

[0096] Table 9

[0097]

[0098] As shown in Table 10 below, after one iteration, the number of damaged memory banks included in the first memory group 200-1 changes from 0 to 1, the number of damaged memory banks included in the second memory group 200-2 changes from 3 to 1, and the number of damaged memory banks included in the third memory group 200-3 changes from 0 to 1; at the end of the iteration, the yield of the memory system meets the requirement and is optimal, and the number of damaged memory banks included in the memory system as a whole is 1. Compared with the yields of the memory systems shown in Tables 8 and 9, the yield of the memory system shown in Table 7 is improved.

[0099] Table 10

[0100]

[0101] In other examples, taking the number of memory libraries exceeding the shared library (4) as an example, for example, the number of damaged memory libraries included in the second memory group 200-2 is 5, and the number of damaged memory libraries included in the first memory group 200-1 and the third memory group 200-3 are both 0.

[0102] As shown in Table 11 below, after one iteration, the number of damaged memory banks included in the first memory group 200-1 changes from 5 to 1, the number of damaged memory banks included in the second memory group 200-2 changes from 0 to 2, and the number of damaged memory banks included in the third memory group 200-3 changes from 0 to 2; at the end of the iteration, the yield of the memory system meets the requirements, and the number of damaged memory banks included in the memory system as a whole is 2.

[0103] Table 11

[0104]

[0105] In some other examples, for example, the number of damaged memory banks included in the second memory group 200-1 is 5, and the Nth memory group ( Figure 6), the first memory group 200-1, the third memory group 200-3, and the fourth memory group (not shown), Figure 6 As shown in Table 12 below, after two iterations, the number of damaged memory banks included in the first memory group 200-1 changes from 5 to 1, and the number of damaged memory banks included in the Nth memory group ( Figure 6 ), the first memory group 200-1, the third memory group 200-3, and the fourth memory group (not shown), Figure 6 At the end of the iteration, the yield of the memory system reaches the requirement and is optimal. The number of damaged memory libraries contained in the memory system as a whole is 1. Compared with the yield of the memory system shown in Table 11, the yield of the memory system shown in Table 7 is improved.

[0106] Table 12

[0107]

[0108] In some other embodiments, the number of memory control logics coupled to the shared library of the memory group may exceed 3, and the multiplexer circuit further includes an X-1 multiplexer (X-1MUX), where X is a natural number greater than 3. The more ways available for selection in the multiplexer circuit means the more memory control logics coupled to the shared library of a memory group, and the more resources of the memory control logic are consumed. The selection of the number of ways of the multiplexer circuit needs to weigh various factors such as the resource consumption of the memory control logic and the yield of the memory system.

[0109] In some embodiments, the memory system also includes a non-volatile memory; the non-volatile memory is configured to store configuration information; the configuration information includes first configuration information and second configuration information; wherein the first configuration information is used to complete a first configuration; the first configuration includes enabling / enabling non-each memory control logic to be coupled to each memory library in a corresponding memory group; wherein the second configuration information is used to complete a second configuration; the second configuration includes selecting a shared library to be coupled to a memory control logic, or selecting a shared library to be coupled to a memory control logic in at least one other memory control logic adjacent to the memory control logic.

[0110] In some embodiments, the non-volatile memory includes a One-Time Programmable (OTP) or an electronic fuse (efuse).

[0111] In some embodiments, the memory system also includes a remapping register and a multiplexer register; the memory system is also configured to: in response to startup of the memory system, read first configuration information and second configuration information from the non-volatile memory; write the first configuration information and the second configuration information into the remapping register and the multiplexer register, respectively; complete the first configuration according to the first configuration information stored in the remapping register, and complete the second configuration according to the second configuration information stored in the multiplexer register.

[0112] Figure 7 A schematic diagram of detailed operation steps of a method for manufacturing a memory system provided in an embodiment of the present application. It should be understood that Figure 7 The steps shown in the figure between step S101 and step S111 are not exclusive, and other steps may be performed before, after or between any steps in the shown operation; Figure 7 The steps shown in the figure can be adjusted in sequence according to actual needs.

[0113] In a second aspect, the present application provides a method for manufacturing a memory system, referring to Figure 7 , the manufacturing method comprises the following steps:

[0114] S102, providing a multi-layer stacked chip; the multi-layer stacked chip includes a logic chip and a plurality of memory chips stacked on the logic chip and interconnected with the logic chip; wherein the logic chip includes a plurality of memory control logics; wherein the plurality of memory chips include a plurality of memory groups; each memory chip includes a plurality of memory libraries; each memory group includes one or more memory libraries in each memory chip; a plurality of memory groups, each memory group includes a plurality of memory libraries; a plurality of memory control logics, each memory control logic is coupled to each memory library in a corresponding memory group; at least part of the memory libraries in each memory group are used as shared libraries, and the shared libraries are also coupled to at least one other memory control logic adjacent to a memory control logic;

[0115] S103, testing the multi-layer stacked chip to generate yield information of the multi-layer stacked chip; the yield information includes quality information of the memory banks in each memory group;

[0116] S104-S107, generating and exporting configuration information according to the yield information satisfying the preset conditions; the configuration information includes first configuration information and second configuration information; wherein the first configuration information is used to complete the first configuration; the first configuration includes enabling / enabling non-each memory control logic to be coupled to each memory library in a corresponding memory group; wherein the second configuration information is used to complete the second configuration; the second configuration includes selecting a shared library to be coupled to a memory control logic, or selecting a shared library to be coupled to a memory control logic in at least one other memory control logic adjacent to a memory control logic;

[0117] S108. Write the configuration information into the non-volatile memory of the multi-layer stacked chip; the first configuration information of the non-volatile memory is used to complete the first configuration, and the second configuration information stored in the non-volatile memory is used to complete the second configuration, so that the yield of the multi-layer stacked chip after completing the first configuration and the second configuration is greater than the yield of the multi-layer stacked chip before completing the first configuration and the second configuration.

[0118] It should be noted that the preset condition can be understood as the number of damaged memory banks in the memory group exceeds the upper limit value (for example, 2); or, the preset condition can also be understood as the number of damaged memory banks in the memory group does not exceed the upper limit value (for example, 2) and is not optimal.

[0119] It should be noted that the configuration information is written into the non-volatile memory of the multi-layer stacked chip to obtain the memory system as described in the above-mentioned embodiments of the first aspect.

[0120] refer to Figure 7 In some embodiments, the multi-layer stacked chip is tested to generate yield information of the multi-layer stacked chip, referring to step S103, including: performing a memory built-in self-test (MBIST) on the multi-layer stacked chip to generate fail bit data of each memory bank; based on the fail bit data of each memory bank, using offline software to calculate and generate good or bad information of each memory bank; based on the good or bad information of each memory bank, generating good or bad information of each memory group; based on the good or bad information of each memory group, generating yield information of the multi-layer stacked chip.

[0121] It should be noted that the quality information of the memory library includes information whether the memory library is a bad memory library or a good memory library. If the failure bit of the memory library exceeds the preset value, the memory library is marked as a bad memory library. If the failure bit of the memory library does not exceed the preset value, the memory library is marked as a good memory library. The quality information of the memory group includes information whether the memory group is a bad memory group or a good memory group. If the bad memory banks of the memory group exceed the preset value, the memory group is marked as a bad memory group. If the bad memory banks of the memory group do not exceed the preset value, the memory group is marked as a good memory group. The yield information of the multi-layer stacked chip includes good multi-layer stacked chips or waste chips. If each memory group is a good memory group, the multi-layer stacked chip is marked as a good multi-layer stacked chip. If there is at least one bad memory group after the configuration is completed, the multi-layer stacked chip is marked as a waste chip.

[0122] refer to Figure 7 In some embodiments, configuration information is generated and exported based on whether the yield information satisfies the preset conditions, including: referring to step S105, calculating the optimal allocation algorithm using an offline software algorithm based on whether the yield information satisfies the preset conditions; referring to step S106, generating configuration information based on successful calculation of the optimal allocation algorithm; referring to step S107, generating and exporting configuration information.

[0123] refer to Figure 7 In some embodiments, referring to step S109, according to which the yield information does not meet the preset conditions, the configuration information adopts the default configuration; or, referring to step S110, according to the failure of calculation of the optimal allocation algorithm, the multi-layer stacked chip is marked as a waste chip.

[0124] It should be noted that the default configuration can be understood as each memory control logic is coupled to each memory bank in a corresponding memory group, and the shared bank in each memory group is not coupled to at least one other memory control logic adjacent to a memory control logic.

[0125] The memory system obtained by the manufacturing method of the memory system provided in the embodiment of the present application is the same as or similar to the memory system in the embodiments of the first aspect above. For the technical features not fully disclosed in the embodiment of the present application, please refer to the memory system in the embodiments of the first aspect above for understanding, and no further details will be given here.

[0126] Figure 8 A flowchart of an operating method of a memory system provided in an embodiment of the present application.

[0127] In a third aspect, the present application provides an operating method of a memory system, referring to Figure 8 , the operation method comprises the following steps:

[0128] S201, start a memory system; wherein the memory system includes a plurality of memory groups and a plurality of memory control logics; each memory group includes a plurality of memory banks; each memory control logic is coupled to each memory bank in a corresponding memory group; at least part of the memory banks in each memory group are used as shared banks, and the shared banks are also coupled to at least one other memory control logic adjacent to a memory control logic;

[0129] S202, in response to the startup of the memory system, read configuration information from the non-volatile memory of the memory system; the configuration information includes first configuration information and second configuration information; wherein the first configuration information is used to complete a first configuration; the first configuration includes enabling / enabling non-each memory control logic to be coupled to each memory bank in a corresponding memory group; wherein the second configuration information is used to complete a second configuration; the second configuration includes selecting a shared bank to be coupled to a memory control logic, or selecting a shared bank to be coupled to a memory control logic in at least one other memory control logic adjacent to the memory control logic;

[0130] S203, writing the first configuration information and the second configuration information into a remapping register and a multiplexer register of the memory system respectively;

[0131] S204, completing the first configuration according to the first configuration information stored in the remapping register, and completing the second configuration according to the second configuration information stored in the multi-way selection register, so that the yield of the memory system after completing the first configuration and the second configuration is greater than the yield of the memory system before completing the first configuration and the second configuration.

[0132] It should be noted that the yield of the memory system before completing the first configuration and the second configuration can be understood as the yield of the memory system under the default configuration. The default configuration can be understood as each memory control logic is coupled to each memory library in a corresponding memory group, and the shared library in each memory group is not coupled to at least one other memory control logic adjacent to a memory control logic.

[0133] The memory system used in the operating method of the memory system provided in the embodiments of the present application is the same as or similar to the memory system in the embodiments of the first aspect above. For the technical features not fully disclosed in the embodiments of the present application, please refer to the memory system in the embodiments of the first aspect above for understanding, and no further details will be given here.

[0134] It should be understood that "one embodiment" or "an embodiment" mentioned throughout the specification means that specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present application. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in various embodiments of the present application, the size of the sequence number of the above-mentioned processes does not mean the order of execution, and the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application. The above-mentioned sequence numbers of the embodiments of the present application are only for description and do not represent the advantages and disadvantages of the embodiments.

[0135] The above description is only a preferred implementation mode of the present application, and does not limit the protection scope of the present application. All equivalent structural changes made by using the contents of the present application specification and drawings under the application concept of the present application, or direct / indirect application in other related technical fields are included in the protection scope of the present application.

Claims

1. A memory system, characterized in that: include: a plurality of memory groups, each of the memory groups comprising a plurality of memory banks; a plurality of memory control logics, each of the memory control logics being coupled to each of the memory banks in a corresponding one of the memory groups; At least part of the memory banks in each of the memory groups serve as shared banks, and the shared banks are further coupled to at least one other memory control logic adjacent to one of the memory control logics; The memory system is configured as follows: The following configuration is completed: shielding the coupling between the at least partially damaged memory bank in the memory group and the memory control logic, and selecting the coupling between the memory banks in the shared library corresponding to the other at least one memory control logic; So that the capacity of the memory system is increased after the configuration is completed.

2. The memory system according to claim 1, wherein: The memory system is configured as follows: shielding coupling between a of the damaged M memory banks in a memory group and a memory control logic, and selecting coupling between a of the shared banks corresponding to at least one other memory control logic; and / or, shielding the coupling between b memory banks among N memory banks in the shared bank of the memory group and a memory control logic; selecting the coupling between the other at least one memory control logic and b memory banks; So that the number of the memory libraries coupled to one of the memory control logics and the number of the memory libraries coupled to at least one of the other memory control logics are both greater than (4K-M); wherein the number of the memory libraries with the greatest damage in the plurality of memory groups is M, the number of the memory libraries in the shared library is N, the number of the memory libraries in the memory group is 4K, a≤M, b≤N, 0≤M≤4K, and a, M, N, and K are all natural numbers.

3. The memory system according to claim 2, wherein: Each of the memory groups includes a first group and a second group; each of the memory control logics includes a first logic circuit and a second logic circuit; the first group serves as the shared library and is coupled to the second logic circuit and the first logic circuit of at least one other memory control logic through a multiplexer circuit; the second group is coupled to the second logic circuit; The first logic circuit is coupled to the shared library corresponding to at least one other memory control logic through the multiplexer circuit.

4. The memory system according to claim 3, characterized in that: The plurality of memory groups include a first memory group, a second memory group, and a third memory group; the plurality of memory control logics include a first memory control logic, a second memory control logic, and a third memory control logic; the first memory control logic is coupled to the corresponding first memory group, the second memory control logic is coupled to the corresponding second memory group, and the third memory control logic is coupled to the corresponding third memory group; The shared library is coupled to at least one of the other memory control logics adjacent to one of the memory control logics, including: the shared library of the second memory group is coupled to the first memory control logic adjacent to the second memory control logic; wherein the first group of the second memory group is coupled to the second logic circuit of the second memory control logic and the first logic circuit of the first memory control logic through the multiplexer circuit; the second group of the second memory group is coupled to the second logic circuit of the second memory control logic; the first logic circuit of the second memory control logic is coupled to the first group of the third memory group through the multiplexer circuit; The memory system is configured as follows: Shielding the coupling between a of the damaged M memory banks in the second memory group and the second logic circuit of the second memory control logic; selecting the first logic circuit of the second memory control logic to be coupled to a of the memory banks in the first group of the third memory group through the multiplexer circuit; shielding the coupling between a of the memory banks in the first group of the third memory group and the second logic circuit of the third memory control logic; and / or, shielding the coupling between b memory banks of the N memory banks of the first group of the second memory group and the second logic circuit of the second memory control logic; selecting the first logic circuit of the first memory control logic to be coupled to b memory banks of the first group of the second memory group through the multiplexer circuit; So that the number of the memory banks coupled to the first memory control logic, the second memory control logic and the third memory control logic is greater than (4K-M).

5. The memory system according to claim 3, characterized in that: The plurality of memory groups include a first memory group, a second memory group, and a third memory group; the plurality of memory control logics include a first memory control logic, a second memory control logic, and a third memory control logic; the first memory control logic is coupled to the corresponding first memory group, the second memory control logic is coupled to the corresponding second memory group, and the third memory control logic is coupled to the corresponding third memory group; The shared library is coupled to at least one of the other memory control logics adjacent to one of the memory control logics, including: the shared library of the second memory group is coupled to the first memory control logic and / or the third memory control logic adjacent to the second memory control logic; wherein the first group of the second memory group is coupled to the second logic circuit of the second memory control logic, the first logic circuit of the first memory control logic, and the first logic circuit of the third memory control logic through the multiplexer circuit; the second group of the second memory group is coupled to the second logic circuit of the second memory control logic; the first logic circuit of the second memory control logic is coupled to the first group of the first memory group and the first group of the third memory group through the multiplexer circuit; The memory system is configured as follows: Shielding the coupling between a of the damaged M memory banks in the second memory group and the second logic circuit of the second memory control logic; selecting the first logic circuit of the second memory control logic to be coupled to a of the memory banks in the first group of the first memory group and / or the first group of the third memory group through the multiplexer circuit; shielding the coupling between a of the memory banks in the first group of the first memory group and / or the first group of the third memory group and the second logic circuit of the first memory control logic and / or the second logic circuit of the third memory control logic; and / or, shielding the coupling between b memory banks of the N memory banks of the first group of the second memory group and the second logic circuit of the second memory control logic; selecting the first logic circuit of the first memory control logic and / or the first logic circuit of the third memory control logic to be coupled to b memory banks of the first group of the second memory group through the multiplexer circuit; So that the number of the memory banks coupled to the first memory control logic, the second memory control logic and the third memory control logic is greater than (4K-M).

6. The memory system according to claim 1, wherein: The number of the memory banks in the shared library is positively correlated with yield information; the yield information includes an average of yield values ​​of the plurality of memory groups; and the yield value includes good or bad information of the memory banks in each of the simulated memory groups.

7. The memory system according to claim 6, characterized in that: The number of the memory banks in the shared library ranges from 2 to 2K.

8. The memory system according to claim 1, wherein: The memory system also includes a non-volatile memory; The non-volatile memory is configured to store configuration information; the configuration information includes first configuration information and second configuration information; Wherein, the first configuration information is used to complete the first configuration; the first configuration includes enabling / enabling each of the memory control logics to be coupled to each of the memory banks in a corresponding one of the memory groups; The second configuration information is used to complete the second configuration; the second configuration includes selecting the shared library to be coupled to one of the memory control logics, or selecting the shared library to be coupled to one of the memory control logics in at least one other memory control logic adjacent to one of the memory control logics.

9. The memory system according to claim 8, characterized in that: The memory system also includes a remapping register and a multiplexer register; The memory system is also configured to: In response to startup of the memory system, reading the first configuration information and the second configuration information from the non-volatile memory; Writing the first configuration information and the second configuration information into the remapping register and the multiplexing register respectively; The first configuration is completed according to the first configuration information stored in the remapping register, and the second configuration is completed according to the second configuration information stored in the multiplexing register.

10. The memory system according to claim 1, wherein: The memory system includes a logic chip and a plurality of memory chips stacked on the logic chip and interconnected with the logic chip; Wherein, the logic chip includes the plurality of memory control logics; The plurality of memory chips include the plurality of memory groups; each of the memory chips includes a plurality of the memory banks; and each of the memory groups includes one or more of the memory banks in each of the memory chips.

11. A method for manufacturing a memory system, characterized in that: include: A multi-layer stacked chip is provided; the multi-layer stacked chip comprises a logic chip and a plurality of memory chips stacked on the logic chip and interconnected with the logic chip; wherein the logic chip comprises the plurality of memory control logics; wherein the plurality of memory chips comprises the plurality of memory groups; each of the memory chips comprises a plurality of memory libraries; each of the memory groups comprises one or more of the memory libraries in each of the memory chips; a plurality of memory groups, each of the memory groups comprises a plurality of memory libraries; a plurality of memory control logics, each of the memory control logics being coupled to each of the memory libraries in a corresponding one of the memory groups; at least part of the memory libraries in each of the memory groups being shared libraries, the shared libraries being further coupled to at least one other memory control logic adjacent to one of the memory control logics; Testing the multi-layer stacked chip to generate yield information of the multi-layer stacked chip; the yield information includes quality information of the memory bank in each of the memory groups; According to the yield information satisfying the preset condition, configuration information is generated and derived; the configuration information includes first configuration information and second configuration information; wherein the first configuration information is used to complete the first configuration; the first configuration includes enabling / enabling non-each of the memory control logics to be coupled to each of the memory libraries in the corresponding one of the memory groups; wherein the second configuration information is used to complete the second configuration; the second configuration includes selecting the shared library to be coupled to one of the memory control logics, or selecting the shared library to be coupled to one of the memory control logics of at least one of the other memory control logics adjacent to one of the memory control logics; The configuration information is written into the non-volatile memory of the multi-layer stacked chip; the first configuration information of the non-volatile memory is used to complete the first configuration, and the second configuration information stored in the non-volatile memory is used to complete the second configuration, so that the yield of the multi-layer stacked chip after completing the first configuration and the second configuration is greater than the yield of the multi-layer stacked chip before completing the first configuration and the second configuration.

12. The manufacturing method according to claim 11, characterized in that: Testing the multi-layer stacked chip to generate yield information of the multi-layer stacked chip includes: Performing a memory built-in self-test on the multi-layer stacked chip to generate failed bit data of each memory bank; Based on the failed bit data of each memory bank, using offline software to calculate and generate the quality information of each memory bank; Based on the quality information of each of the memory banks, generating quality information of each of the memory groups; Based on the quality information of each of the memory groups, yield information of the multi-layer stacked chip is generated.

13. The manufacturing method according to claim 12, characterized in that: According to the yield information satisfying a preset condition, generating and exporting the configuration information includes: According to the yield information satisfying the preset conditions, an optimal allocation algorithm is calculated using an offline software algorithm; The configuration information is generated successfully according to the calculation of the optimal allocation algorithm; The configuration information is exported.

14. The manufacturing method according to claim 13, characterized in that: According to the yield information not satisfying the preset condition, the configuration information adopts a default configuration; or, according to the calculation failure of the optimal allocation algorithm, the multi-layer stacked chip is marked as a waste chip.

15. A method for operating a memory system, characterized in that: include: Starting the memory system; wherein the memory system comprises a plurality of memory groups and a plurality of memory control logics; each of the memory groups comprises a plurality of memory libraries; each of the memory control logics is coupled to each of the memory libraries in a corresponding one of the memory groups; at least part of the memory libraries in each of the memory groups are used as shared libraries, and the shared libraries are also coupled to at least one other memory control logic adjacent to one of the memory control logics; In response to the startup of the memory system, configuration information is read from the non-volatile memory of the memory system; the configuration information includes first configuration information and second configuration information; wherein the first configuration information is used to complete a first configuration; the first configuration includes enabling / enabling non-each of the memory control logics to be coupled to each of the memory banks in a corresponding one of the memory groups; wherein the second configuration information is used to complete a second configuration; the second configuration includes selecting the shared bank to be coupled to a memory control logic, or selecting the shared bank to be coupled to one of the memory control logics in at least one other of the memory control logics adjacent to the one of the memory control logics; Writing the first configuration information and the second configuration information into a remapping register and a multiplexer register of the memory system respectively; The first configuration is completed according to the first configuration information stored in the remapping register, and the second configuration is completed according to the second configuration information stored in the multiplexer register, so that the yield of the memory system after completing the first configuration and the second configuration is greater than the yield of the memory system before completing the first configuration and the second configuration.

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