Control method of multi-core system-on-chip and multi-core system-on-chip

Abstract

The invention discloses a control method of a multi-core system-on-chip and the multi-core system-on-chip. Relates to the technical field of chip design. The method comprises the following steps: acquiring an operation index of a multi-core system on chip; based on the operation indexes, current working modes corresponding to a plurality of CPU cores in the multi-core system on chip are determined, and the current working modes are used for indicating whether the corresponding CPU cores execute tasks according to an independent mode or a dynamic heterogeneous redundancy mode; and controlling the plurality of CPU cores to execute tasks according to the corresponding current working modes. The technical problems that the multi-core system-on-chip is poor in working flexibility and low in task execution efficiency due to the fact that the multi-core system-on-chip only supports all the CPU cores to execute the same task or all the CPU cores execute different tasks respectively in the prior art are solved.

Description

Technical Field

[0001] The present invention relates to the technical field of chip design, and in particular to a control method for a multi-core system on chip and a multi-core system on chip. Background Art

[0002] At present, multi-core system on chip (SoC) is a very common architecture in the field of chip design, and the corresponding chips are widely used in daily production and life. Currently, common multi-core SoC systems are mainly divided into two categories. One is that each CPU core works independently and handles different tasks to improve efficiency; the other is that each CPU core handles the same task and works in a dynamic heterogeneous redundant manner to provide the security of the SoC system. Both methods have their own advantages and disadvantages, but the actual application scenarios are different. Some scenarios focus on task execution efficiency, while others focus on task execution security. If different multi-core SoC systems need to be configured for different scenarios according to the current architecture, there are problems such as high application cost, poor flexibility, and low task execution efficiency.

[0003] To address the above-mentioned problems, no effective solution has been proposed yet. Summary of the invention

[0004] The embodiments of the present invention provide a control method for a multi-core system on chip and a multi-core system on chip, so as to at least solve the technical problems in the related art that the multi-core system on chip only supports all CPU cores to execute the same task, or all CPU cores execute different tasks respectively, and the multi-core system on chip has poor working flexibility and low task execution efficiency.

[0005] According to one aspect of an embodiment of the present invention, a control method for a multi-core system-on-chip is provided, comprising: obtaining operating indicators of the multi-core system-on-chip; determining current operating modes corresponding to multiple CPU cores in the multi-core system-on-chip based on the operating indicators, wherein the current operating mode is used to indicate whether the corresponding CPU core executes a task in an independent mode, executes a task in a dynamic heterogeneous redundancy mode, or suspends execution of a task, and the independent mode is used to indicate that the corresponding CPU core processes a task alone; the dynamic heterogeneous redundancy mode is used to indicate that the corresponding CPU core cooperates with other CPU cores to process the same task, and dynamically adjusts the working status and task allocation of different CPU cores during the process of cooperating to process the same task; and controlling the multiple CPU cores to execute tasks in accordance with the corresponding current operating modes.

[0006] Optionally, obtaining the operating indicators of the multi-core system-on-chip includes: obtaining application scenarios of the multi-core system-on-chip, wherein the application scenarios include fixed working mode scenarios or automatic working mode switching scenarios; when the application scenario is an automatic working mode switching scenario, obtaining the operating indicators of the multi-core system-on-chip.

[0007] Optionally, the method further includes: when the application scenario is a fixed working mode scenario, obtaining fixed working modes pre-set for the multiple CPU cores respectively; and controlling the multiple CPU cores to perform tasks according to the corresponding fixed working modes.

[0008] Optionally, determining the current operating modes corresponding to the multiple CPU cores in the multi-core system-on-chip based on the operating indicators includes: determining a target CPU allocation strategy based on the operating indicators, wherein the target CPU allocation strategy is at least used to indicate the number of first CPU cores that execute tasks in the independent mode and the number of second CPU cores that execute tasks in the dynamic heterogeneous redundancy mode; determining the current operating modes corresponding to the multiple CPU cores based on the target CPU allocation strategy.

[0009] Optionally, determining the target CPU allocation strategy based on the operating indicator includes: determining the target indicator range to which the operating indicator belongs from multiple indicator ranges; and determining the CPU allocation strategy corresponding to the target indicator range among the CPU allocation strategies corresponding to the multiple indicator ranges as the target CPU allocation strategy.

[0010] Optionally, in the case where there are multiple operating indicators, determining the target CPU allocation strategy based on the operating indicators includes: determining weight values ​​corresponding to the multiple operating indicators respectively; performing weighted calculation based on the multiple operating indicators and the weight values ​​corresponding to the multiple operating indicators respectively to obtain an indicator score value; and determining the target CPU allocation strategy based on the indicator score value.

[0011] Optionally, determining the target CPU allocation strategy includes: determining a target indicator scoring range to which the indicator scoring value belongs from multiple indicator scoring ranges; and determining, among the CPU allocation strategies corresponding to the multiple indicator scoring ranges, a CPU allocation strategy corresponding to the target indicator scoring range as the target CPU allocation strategy.

[0012] Optionally, the operating indicator includes a task level of the task to be executed, and / or at least one of the following: temperature of the multi-core system on chip, task congestion, task safety level, and service quality level.

[0013] According to another aspect of an embodiment of the present invention, a multi-core system on chip is provided, comprising: a plurality of CPU cores and a target CPU core, wherein the target CPU core is used to execute any one of the control methods for the multi-core system on chip.

[0014] According to another aspect of an embodiment of the present invention, a computer program product is provided, including a computer program, wherein when the computer program is executed by a processor, the steps of any one of the control methods for a multi-core system on chip are implemented.

[0015] In an embodiment of the present invention, by obtaining the operating index of a multi-core system-on-chip; based on the operating index, determining the current working modes corresponding to the multiple CPU cores in the multi-core system-on-chip, wherein the current working mode is used to indicate whether the corresponding CPU core executes the task in an independent mode, executes the task in a dynamic heterogeneous redundant mode, or suspends the execution of the task, and the independent mode is used to indicate that the corresponding CPU core is processing a task alone; the dynamic heterogeneous redundant mode is used to indicate that the corresponding CPU core cooperates with other CPU cores to process the same task, and dynamically adjusts the working status and task allocation of different CPU cores in the process of cooperating to process the same task; and controlling the multiple CPU cores to execute tasks in accordance with the corresponding current working modes, respectively, so as to achieve the purpose of flexibly configuring the respective working modes of the multiple CPU cores according to the task level and the operating index of the multi-core system-on-chip, thereby achieving the technical effect of improving the working flexibility of the multi-core system-on-chip and the task execution efficiency, thereby solving the technical problem that the multi-core system-on-chip in the related art only supports all CPU cores to execute the same task, or all CPU cores to execute different tasks respectively, and the multi-core system-on-chip has poor working flexibility and low task execution efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of this application. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0017] Figure 1 is a flow chart of a control method of a multi-core system on chip according to an embodiment of the present invention;

[0018] Figure 2 is a schematic diagram of an optional mimetic microcontroller system structure according to an embodiment of the present invention;

[0019] Figure 3 is an internal implementation architecture diagram of an optional system-on-chip scheduling subsystem according to an embodiment of the present invention;

[0020] Figure 4This is an internal implementation architecture diagram of an optional working mode management module according to an embodiment of the present invention;

[0021] Figure 5 is a flow chart of an optional control method of a multi-core system on chip according to an embodiment of the present invention;

[0022] Figure 6 is an optional mimetic decision flow chart according to an embodiment of the present invention;

[0023] Figure 7 is a schematic diagram of a control device for a multi-core system on chip according to an embodiment of the present invention. DETAILED DESCRIPTION

[0024] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0025] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0026] First, to facilitate understanding of the embodiments of the present invention, some terms or nouns involved in the present invention are explained below:

[0027] Advanced High-performance Bus (AHB-BUS), a bus standard for connecting processors, memories, and peripherals, is often used in high-performance System on Chip (SoC) designs. AHB-BUS provides high-bandwidth, low-latency data transmission capabilities, supports parallel access to multiple master and slave devices, and helps improve the overall performance and efficiency of the system.

[0028] According to an embodiment of the present invention, an embodiment of a method for controlling a multi-core system on chip is provided. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer executable instructions, and although a logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0029] Figure 1 is a flow chart of a control method of a multi-core system on chip according to an embodiment of the present invention. Figure 1 As shown, the method comprises the following steps:

[0030] Step S102, obtaining the operating index of the multi-core system on chip;

[0031] Optionally, the multi-core system on chip integrates multiple CPU cores and a target CPU core, wherein the target CPU core is a CPU core other than the multiple CPU cores and can serve as the execution subject of steps S102 to S106.

[0032] In an optional embodiment, operating indicators of the multi-core system-on-chip can be obtained during the process of executing tasks based on the multi-core system-on-chip, wherein the operating indicators include the task level of the task to be executed, and / or at least one of the following: the temperature of the multi-core system-on-chip, task congestion, task safety level, and service quality level.

[0033] Optionally, the task level can be understood as the task priority of the task to be executed, which is used to indicate the importance of the task. The task level can be predetermined based on factors such as the task type, task complexity, and computing power requirement. Before executing step S102, a corresponding quality of service (QoS) number and a corresponding service level can be assigned to each task to be executed based on one or more of the factors such as the task type, task complexity, and computing power requirement.

[0034] Optionally, the task congestion is used to indicate the task congestion level of the multi-core system-on-chip during the task execution process, and the task congestion level can be used to measure the safety of the multi-core system-on-chip during the task execution process. The greater the task congestion, the higher the corresponding safety, and vice versa. The task safety level can be pre-set for each task to be executed before executing step S102, or it can be determined during the task execution process based on other indicators of the multi-core system-on-chip (such as task congestion, task type) and other factors.

[0035] Optionally, the service quality level is the QoS level, which can be used to describe the performance, response speed, stability and other aspects of the chip. The service quality level can be measured by, but is not limited to, one or more of the data transmission speed, response time, bandwidth, and delay indicators of the multi-core system on chip. By obtaining the operating indicators of the multi-core system on chip, the task execution of the multi-core system on chip can be measured and monitored in real time. The operating indicators are used as the basis for setting the working mode of each CPU core in the multi-core system on chip.

[0036] In an optional embodiment, obtaining the operating indicators of the multi-core system on chip includes: obtaining the application scenario of the multi-core system on chip, wherein the application scenario includes a fixed working mode scenario or an automatic working mode switching scenario; when the application scenario is an automatic working mode switching scenario, obtaining the operating indicators of the multi-core system on chip.

[0037] Optionally, before executing the above step S102, the application scenario of the multi-core system-on-chip can be determined to confirm whether the multi-core system-on-chip is currently in a fixed working mode scenario or an automatic working mode switching scenario, wherein the fixed working mode scenario means that the user can pre-set the working mode of each CPU core in the multi-core system-on-chip, and the automatic working mode switching scenario means that the working mode of each CPU core is automatically switched during the multi-core system-on-chip execution of tasks. By defining different working modes, different application requirements can be met. In the automatic working mode switching scenario, the multi-core system-on-chip will monitor the operating indicators of the multi-core system-on-chip for flexible setting of the subsequent working modes of each CPU core. The above method can not only enrich the application scenarios of the multi-core system-on-chip, but also better meet the application scenario requirements of different users. At the same time, the working mode of each CPU core can be adjusted and optimized by real-time monitoring of the operating indicators of the multi-core system-on-chip to improve the task execution flexibility and task execution efficiency of the multi-core system-on-chip.

[0038] In an optional embodiment, the method further includes: when the application scenario is a fixed working mode scenario, obtaining fixed working modes pre-set for the multiple CPU cores respectively; and controlling the multiple CPU cores to perform tasks according to the corresponding fixed working modes.

[0039] It can be understood that in a fixed working mode scenario, the multi-core system-on-chip will always maintain a specific working mode (i.e., a fixed working mode). The fixed working mode is pre-set according to actual needs, that is, before executing a task based on the multi-core system-on-chip, it is pre-set which CPU cores in the multi-core system-on-chip execute tasks in an independent mode, which CPU cores execute tasks in a dynamic heterogeneous redundant mode, and which CPU cores do not need to work, etc., thereby enriching the application scenarios of the multi-core system-on-chip, and through a multi-core system-on-chip, the user's task execution needs can be better met, and the investment cost of the multi-core system-on-chip during task execution can be reduced.

[0040] Step S104, based on the operation index, determining the current working modes respectively corresponding to the multiple CPU cores in the multi-core system-on-chip, wherein the current working mode is used to indicate whether the corresponding CPU core executes the task in an independent mode, executes the task in a dynamic heterogeneous redundancy mode, or suspends the execution of the task, and the independent mode is used to indicate that the corresponding CPU core processes a task alone; the dynamic heterogeneous redundancy mode is used to indicate that the corresponding CPU core cooperates with other CPU cores to process the same task, and dynamically adjusts the working status and task allocation of different CPU cores in the process of cooperating to process the same task;

[0041] It can be understood that the operation index is used to indicate the current operation status of the multi-core system on chip. The current working mode of each CPU core is determined based on the operation index. Through the operation index, it can be determined whether each CPU core executes tasks in an independent mode, in a dynamic heterogeneous redundant mode, or stops running and temporarily does not execute tasks. That is, it is determined which CPU cores among multiple CPU cores execute different tasks in an independent mode; and which CPU cores cooperate with each other to execute the same task in a dynamic heterogeneous redundant mode. In this way, the purpose of flexibly determining and adjusting the working mode of each CPU core according to the current operation status of the multi-core system on chip is achieved.

[0042] It should be noted that the dynamic heterogeneous redundancy mode is a mode that dynamically adjusts the working status and task allocation of different CPU cores in the multi-core system-on-chip to provide higher reliability and security of multi-core system-on-chip task execution. In the dynamic heterogeneous redundancy mode, the operating status of each CPU core in the multi-core system-on-chip can be monitored in real time, and the working mode and task allocation of each CPU core can be dynamically adjusted according to factors such as the operating load, power consumption, temperature of the multi-core system-on-chip, and the task level of the task to be executed, thereby maximizing the stability and reliability of the multi-core system-on-chip when executing tasks.

[0043] In an optional embodiment, determining the current operating modes corresponding to the multiple CPU cores in the multi-core system on chip based on the operating indicators includes: determining a target CPU allocation strategy based on the operating indicators, wherein the target CPU allocation strategy is at least used to indicate the number of first CPU cores that execute tasks in the independent mode and the number of second CPU cores that execute tasks in the dynamic heterogeneous redundancy mode; determining the current operating modes corresponding to the multiple CPU cores based on the target CPU allocation strategy.

[0044] Optionally, the target CPU allocation strategy determined by the operation index can indicate the CPU core quantity allocation situation, that is, how many CPU cores need to be allocated to perform tasks in the independent mode to obtain the first CPU core quantity; and how many CPU cores need to be allocated to perform tasks in the dynamic heterogeneous redundancy mode to obtain the second CPU core quantity; further, according to the CPU core quantity allocation situation, the CPU cores of the first CPU core quantity can be selected from multiple CPU cores, and the corresponding current working mode can be set to the independent mode; the CPU cores of the second CPU core quantity can be selected, and the corresponding current working mode can be set to the dynamic heterogeneous redundancy mode, thereby obtaining the current working modes corresponding to the multiple CPU cores. Among them, the first CPU core quantity and the second CPU core quantity are both integers greater than or equal to 0; and the sum of the first CPU core quantity and the second CPU core quantity is less than or equal to the total number of multiple CPU cores.

[0045] Through the above methods, it is possible to realize flexible switching of working modes based on a multi-core system-on-chip, and it is possible to realize that a multi-core system-on-chip performs tasks in both independent mode and dynamic heterogeneous redundancy mode at the same time. For example, each CPU core among multiple CPU cores can be set to perform its own tasks in independent mode; multiple CPU cores can also be set to perform the same task in dynamic heterogeneous redundancy mode; and some CPU cores among multiple CPU cores can be set to perform their own tasks in independent mode, while the other parts can perform the same task in dynamic heterogeneous redundancy mode. This can significantly improve the efficiency and flexibility of task execution.

[0046] In an optional embodiment, determining the target CPU allocation strategy based on the operating indicator includes: determining the target indicator range to which the operating indicator belongs from multiple indicator ranges; and determining the CPU allocation strategy corresponding to the target indicator range among the CPU allocation strategies corresponding to the multiple indicator ranges as the target CPU allocation strategy.

[0047] Optionally, multiple metric ranges can be preset, and a CPU allocation policy is corresponding to each metric range. When the running metric is determined, the target metric range to which the running metric belongs is determined, and further, the CPU allocation policy corresponding to the target metric range is determined from multiple CPU allocation policies as the target CPU allocation policy required currently. By matching the target metric range with the corresponding CPU allocation policy, the corresponding CPU allocation policy can be formulated according to the running conditions and performance requirements of the multi-core on-chip system, thereby realizing flexible configuration of the working modes of each CPU core.

[0048] Optionally, the running metric of the multi-core on-chip system is used as the task level of the to-be-executed task, and the corresponding multiple metric ranges are multiple task level ranges. The task level is determined according to the computing power requirement of the to-be-executed task. The higher the computing power requirement is, the higher the corresponding task level is, and vice versa. The QoS number and task level can be allocated to each task in advance according to the computing power requirement of each task. When allocating the number of CPU cores based on the task level, the task level is directly proportional to the number of CPU cores allocated to the task. For example, if a task corresponding to a certain QoS number requires more computing power, then the higher the corresponding task level is, the more CPU cores are allocated to the task. For example, when there are 5 CPU cores, when the computing power requirement is between 0 - x1, the task level is determined to be the first level; when the computing power requirement is between x1 - x2, the task level is determined to be the second level; when the computing power requirement is greater than x2, the task level is determined to be the third level, where 0 < x1 < x2. The CPU allocation policy corresponding to the first level is set to execute the task in the independent working mode; the CPU allocation policy corresponding to the second level is set to allocate 3 CPU cores to execute the same task in the dynamic heterogeneous redundancy mode; the CPU allocation policy corresponding to the third level is set to allocate 5 CPU cores to execute the same task in the dynamic heterogeneous redundancy mode. When the computing power requirement of a certain task is determined, the task level of the task is determined, and the corresponding CPU allocation policy is also determined accordingly.

[0049] Optionally, the QoS number and task level are allocated to each different task. For example, if a task corresponding to a certain QoS number requires more computing power, then the higher the corresponding task level is, the multi-core on-chip system automatically switches to the dynamic heterogeneous redundancy mode when receiving this task, and multiple CPU cores cooperate to process the task to improve the task processing service level; if the task level corresponding to a certain QoS number is relatively low, then the multi-core on-chip system automatically allocates less execution body computing power when receiving this task, and other execution bodies can process other tasks.

[0050] Optionally, when the range of multiple indicators is two, there are two corresponding CPU allocation strategies, that is, multiple CPU cores all use independent working mode to execute tasks, and multiple CPU cores use dynamic heterogeneous redundancy mode to execute the same task. Taking the task congestion degree of the multi-core system-on-chip as an example, a congestion threshold X (where X is greater than 0) is set. When the congestion degree is less than X, a safer dynamic heterogeneous redundancy mode can be used, that is, multiple CPU cores use dynamic heterogeneous redundancy mode to execute the same task; when the congestion degree is greater than X, it automatically switches to a more efficient mode in which each CPU core works independently (i.e., independent mode).

[0051] In an optional embodiment, when there are multiple operating indicators, determining the target CPU allocation strategy based on the operating indicators includes: determining weight values ​​corresponding to the multiple operating indicators respectively; performing weighted calculation based on the multiple operating indicators and the weight values ​​corresponding to the multiple operating indicators respectively to obtain an indicator score value; and determining the target CPU allocation strategy based on the indicator score value.

[0052] Optionally, when there are multiple operating indicators, an indicator score value can be obtained by weighted calculation of the multiple operating indicators, and the score value is used to indicate the comprehensive score of the multi-core system on chip under the influence of the multiple operating indicators. On this basis, the target CPU allocation strategy determined based on the indicator score value is the result obtained by comprehensively considering multiple different indicator dimensions, which is more in line with the actual operation needs of the multi-core system on chip.

[0053] In an optional embodiment, determining the target CPU allocation strategy based on the indicator score value includes: determining a target indicator score range to which the indicator score value belongs from multiple indicator score ranges; and determining the CPU allocation strategy corresponding to the target indicator score range among the CPU allocation strategies corresponding to the multiple indicator score ranges as the target CPU allocation strategy.

[0054] Optionally, the indicator score value can be used to measure the comprehensive operation score of the multi-core system-on-chip under the influence of multiple operation indicators. Different indicator score ranges can correspond to different operation characteristics of the multi-core system-on-chip. By setting different CPU allocation strategies for multiple indicator score ranges, the CPU allocation strategy can be selected in a targeted manner according to the indicator score range to which the indicator score value belongs when the indicator score value is known. In this way, the corresponding CPU allocation strategy can be formulated according to the operation status and performance requirements of the multi-core system-on-chip, thereby realizing flexible configuration of the working mode of each CPU core.

[0055] Optionally, taking multiple operating indicators such as chip junction temperature T (i.e., the temperature of the multi-core system on chip), chip congestion X, chip QoS level Q, and chip security level S as examples, a weighted formula including indicators such as T, X, Q, and S is set to calculate the overall indicator score value Y, and an interval range is set for Y. If the value of Y falls within range A, m CPU cores out of multiple CPU cores are enabled (i.e., in running state), and a of the m CPU cores are configured to work in independent mode, and (ma) CPU cores are configured to work in dynamic heterogeneous redundant mode; similarly, if the value of Y falls within range B, n CPU cores out of n CPU cores are enabled, and b of the n heterogeneous executors are configured to work in independent mode, and (nb) heterogeneous executors are configured to work in dynamic heterogeneous redundant mode, and so on.

[0056] It can be understood that in the above method, multiple heterogeneous executors in a multi-core system-on-chip can flexibly configure the working mode. A certain CPU core can be configured to work in an independent mode or to cooperate with other CPU cores to work in a dynamic heterogeneous redundant working mode. That is to say, independent working mode and heterogeneous redundant mode can exist at the same time in the same multi-core system-on-chip. For example, if there are 5 CPU cores in the multi-core system-on-chip, three of the CPU cores can be configured to work in heterogeneous redundant mode, and the other two heterogeneous executors can work in independent working mode.

[0057] Step S106, controlling the multiple CPU cores to execute tasks according to the corresponding current working modes respectively.

[0058] It can be understood that when the current working modes corresponding to the multiple CPU cores are determined, each CPU core is controlled to execute tasks according to the corresponding current working mode, thereby achieving flexible configuration of the working mode and task execution of each CPU core.

[0059] Through the above steps S102 to S106, the purpose of flexibly configuring the working modes of multiple CPU cores according to the task level and the operating indicators of the multi-core system-on-chip can be achieved, thereby realizing the technical effect of improving the working flexibility of the multi-core system-on-chip and the task execution efficiency, and further solving the technical problems in the related technology that the multi-core system-on-chip only supports all CPU cores to execute the same task, or all CPU cores execute different tasks respectively, and the multi-core system-on-chip has poor working flexibility and low task execution efficiency.

[0060] Based on the above embodiments and optional embodiments, the present invention proposes an optional implementation of a multi-core system-on-chip control method, which can be applied to a Mimic MCU system architecture scenario. Figure 2 is a schematic diagram of an optional mimetic microcontroller system structure according to an embodiment of the present invention, such as Figure 2As shown in FIG. 1 , the mimetic microcontroller system is composed of a heterogeneous CPU subsystem, a system-level chip scheduling subsystem (SoC Schedule Subsystem) and a SoC subsystem, wherein the heterogeneous CPU subsystem has multiple CPU cores (such as CPU0, CPU1, CPU2, etc.) built in, and each CPU core is connected to the system-level chip scheduling subsystem through a corresponding high-performance bus standard (Advanced High-performance Bus, AHB-BUS). The method can be Figure 2 The SoC subsystem is executed by the system-level chip scheduling subsystem in the multi-core system-on-chip, and its role is to dynamically configure the working modes of multiple CPU cores in the multi-core system-on-chip. The SoC subsystem integrates multiple functional modules or components, which can include but are not limited to AHB bus subsystem, peripheral model interface, phase-locked loop, power-on reset, clock and reset management and other functional modules, which are used to provide corresponding connections and functional services for the system-level chip scheduling subsystem.

[0061] Specifically, Figure 3 1 is an internal implementation architecture diagram of an optional system-level chip scheduling subsystem according to an embodiment of the present invention (taking triple-redundant, lightweight advanced high-performance bus AHB-lite transmission as an example), such as Figure 3 As shown, the SCSchedule Subsystem system includes multiple modules such as the CPU Transfer Queue module, the Work Mode Management module, the Platform-Level Interrupt Controller (PLIC) module, the Mimic Judgment module, and the Mimic Distribution module, among which:

[0062] For the CPU Transfer Queue module, each CPU processing channel corresponds to a CPU Transfer Queue module. The CPU Transfer Queue module is instantiated as many times as there are Channel channels (characterized by redundancy) to cache the commands sent from the corresponding CPU channels and take out command requests from the cache according to the commands of the queue management module.

[0063] The Work Mode Management module is used to flexibly manage the working modes and mimic scheduling strategies of multiple CPU cores included in the multi-core system-on-chip, for example, to determine whether each CPU core uses an independent working mode to execute tasks or a dynamic heterogeneous redundant mode to execute tasks. This module is generally implemented by a single CPU core (such as the target CPU core) and can dynamically manage mimic strategies.

[0064] The PLIC module is used to receive interrupt request signals sent by various peripherals, process interrupt sources according to interrupt management settings (including interrupt enable, interrupt priority setting, interrupt mask, etc.), and summarize and send them to each CPU core.

[0065] The Mimic Judgment module is used to compare the bus transmission commands dispatched by each channel according to the mimic judgment strategy and send them to the peripheral module (system bus) when the working mode is dynamic heterogeneous redundancy mode. In addition, in case of comparison failure and abnormal data of one or more heterogeneous execution bodies, the system has designed a state jump mechanism such as system on-site retention, cleaning, and recovery to ensure that the comparison process can proceed normally.

[0066] The Mimic Distribution module is used to receive the peripheral processing results returned on the bus, copy and distribute the peripheral return results according to the mimic heterogeneous executor enable settings, and finally send them to the CPU channels corresponding to each CPU core.

[0067] It should be noted that the CPU type (homogeneous or heterogeneous), quantity, CPU transmission bus protocol (Advanced High Performance Bus - Lightweight Edition AMBA AHB-Lite, Advanced Scalable Interconnect AMBA AXI, Wishbone Bus, etc.) described in this embodiment is not particularly limited. For convenience, the examples are described using heterogeneous CPU, three-core CPU, and AHB-Lite as examples.

[0068] Among them, the key Work Mode Management module and Mimic Judgement module are described in detail as follows:

[0069] in, Figure 4 This is an internal implementation architecture diagram of an optional work mode management module according to an embodiment of the present invention. The Work Mode Management module is used to manage the work mode, including the setting of the number of CPU cores used when executing tasks, wherein each CPU core in the multi-core system-on-chip can be regarded as a heterogeneous executor; the corresponding work mode selection of each CPU core (multi-task independent work mode (i.e., independent mode) or dynamic heterogeneous redundant mode); monitoring of SoC performance and temperature (as a basis for automatic switching of work modes); selection of mimic scheduling strategies; comparison of cleaning and recovery principles, abnormal situation handling, abnormal on-site recovery, etc. under abnormal conditions, which are used as a scheduling basis for the Mimic Judgement module to perform scheduling and on-site recovery of CPU core commands. In order to ensure the flexibility and security of mimic strategy management, a CPU core is set inside the multi-core system-on-chip, and strategies can be dynamically managed according to needs. This CPU core is not open to users.

[0070] Based on the above embodiments and optional embodiments, the present invention proposes an optional implementation mode: Figure 5 is a flowchart of an optional multi-core system on chip control method according to an embodiment of the present invention, which can be applied to Figures 2 to 3 In the system architecture, such as Figure 5 As shown, the method includes:

[0071] S1, the user selects an application scenario. If the working mode is fixed, step S2 is executed; if the working mode is automatically switched, step S3 is executed.

[0072] S2, when the application scenario is a fixed working mode scenario, the user configures the number of multi-core systems-on-chip that need to work when executing the task, and the working mode of each CPU core that needs to work. If the selected working mode is the independent mode, step S4 is executed; if the selected working mode is the dynamic heterogeneous redundancy mode, step S5 is executed;

[0073] S3, when the application scenario is an automatic working mode switching scenario, obtaining operating indicators of the multi-core system on chip;

[0074] S4, when the working mode is independent mode, each CPU core processes tasks independently, and there is no correlation between tasks;

[0075] S5, when the working mode is the dynamic heterogeneous redundancy mode, each CPU core processes the same task and starts the mimic judgment process to execute the task.

[0076] In independent mode, each CPU core works independently, so there is no need for mimic judgment action, so this module can be configured to sleep mode; if the system is configured to work in dynamic heterogeneous redundancy mode, then the mimic judgment process is required. Figure 2 and Figure 3 The three-redundancy (corresponding to three CPU cores) and AHB-lite transmission shown are used as examples to illustrate the workflow of the mimic judgment. Figure 6 is an optional mimetic decision flow chart according to an embodiment of the present invention, such as Figure 6 As shown in the figure, the process specifically includes:

[0077] S51, monitoring the scheduling result of the previous Queue Management module;

[0078] S52, receiving an AHB-lite transmission command input from a previous queue management module;

[0079] S53, performing transaction-level comparison on the AHB-lite transmission of the three CPU cores accessing the peripherals (i.e., peripheral devices); if the comparison is successful, executing step S54, otherwise executing step S56;

[0080] S54, executing corresponding read and write operations on the peripheral device;

[0081] S55, save the checkpoint context information context to the corresponding static random access memory (SRAM) space according to the mimicry strategy, and the judgment ends;

[0082] S56, generating an interrupt to the policy CPU;

[0083] S57, the policy CPU takes over the comparison process and performs cleaning and recovery actions.

[0084] This embodiment adopts a demand-based multi-core SoC variable configuration method, which can flexibly configure the multi-core SoC architecture according to the actual application scenario's requirements for efficiency and safety, etc., and can select multiple cores to independently process tasks to improve the system's task processing efficiency, or select multiple cores to process tasks in a dynamic heterogeneous redundant manner to improve system safety. Users can flexibly configure the working mode of the multi-core SoC system according to the application scenario requirements, which greatly improves the system's flexibility and reduces the cost of chip application for the entire system. Users can flexibly configure the working mode of the multi-core SoC system according to the application scenario requirements, and can also flexibly allocate the CPU core working mode according to the real-time status of system task execution (including task execution efficiency, system power consumption, etc.), which greatly improves the system's flexibility and reduces the cost of chip application for the entire system. In addition, the software and hardware designed in this embodiment have a wide range of applications in the field of multi-core CPUs, and are flexible, efficient, safe, and low-cost.

[0085] In this embodiment, a control device for a multi-core system on chip is also provided, and the device is used to implement the above-mentioned embodiments and preferred implementation modes, and the descriptions that have been made will not be repeated. As used below, the terms "module" and "device" can implement a combination of software and / or hardware for a predetermined function. Although the devices described in the following embodiments are preferably implemented in software, the implementation of hardware, or a combination of software and hardware, is also possible and conceivable.

[0086] According to an embodiment of the present invention, there is also provided an embodiment of a device for implementing the control method of the multi-core system on chip. Figure 7 is a schematic diagram of the structure of a control device of a multi-core system on chip according to an embodiment of the present invention. Figure 7 As shown, the control device of the multi-core system on chip includes: an indicator acquisition module 700, a working mode determination module 702, and a control module 704, wherein:

[0087] The indicator acquisition module 700 is used to obtain the operating indicators of the multi-core system on chip;

[0088] The working mode determination module 702 is connected to the indicator acquisition module 700, and is used to determine the current working modes corresponding to the multiple CPU cores in the multi-core system-on-chip based on the operating indicators, wherein the current working mode is used to indicate whether the corresponding CPU core executes the task in an independent mode, executes the task in a dynamic heterogeneous redundancy mode, or suspends the execution of the task, and the independent mode is used to indicate that the corresponding CPU core processes a task alone; the dynamic heterogeneous redundancy mode is used to indicate that the corresponding CPU core cooperates with other CPU cores to process the same task, and dynamically adjusts the working status and task allocation of different CPU cores in the process of cooperating to process the same task;

[0089] The control module 704 is connected to the working mode determination module 702, and is used to control the multiple CPU cores to execute tasks according to the corresponding current working modes.

[0090] In an embodiment of the present invention, an indicator acquisition module 700 is provided to acquire the operating indicator of the multi-core system on chip; a working mode determination module 702 is connected to the indicator acquisition module 700 and is used to determine the current working modes corresponding to the multiple CPU cores in the multi-core system on chip based on the operating indicator, wherein the current working mode is used to indicate whether the corresponding CPU core executes a task in an independent mode, executes a task in a dynamic heterogeneous redundancy mode, or suspends the execution of a task, the independent mode is used to indicate that the corresponding CPU core processes a task alone; the dynamic heterogeneous redundancy mode is used to indicate that the corresponding CPU core cooperates with other CPU cores to process the same task, and in the cooperation to process the same task In the process of executing tasks, the working status and task allocation of different CPU cores are dynamically adjusted; the control module 704 is connected to the working mode determination module 702, and is used to control the multiple CPU cores to execute tasks according to the corresponding current working modes, thereby achieving the purpose of flexibly configuring the respective working modes of the multiple CPU cores according to the task level and the operating indicators of the multi-core system on chip, thereby achieving the technical effect of improving the working flexibility of the multi-core system on chip and the task execution efficiency, and further solving the technical problems in the related technology that the multi-core system on chip only supports all CPU cores to execute the same task, or all CPU cores to execute different tasks respectively, and the multi-core system on chip has poor working flexibility and low task execution efficiency.

[0091] It should be noted that the above modules can be implemented by software or hardware. For example, for the latter, it can be implemented in the following ways: the above modules can be located in the same processor; or the above modules can be located in different processors in any combination.

[0092] It should be noted that the indicator acquisition module 700, the working mode determination module 702, and the control module 704 correspond to steps S102 to S106 in the embodiment, and the examples and application scenarios implemented by the modules and the corresponding steps are the same, but are not limited to the contents disclosed in the above embodiments. It should be noted that the modules as part of the device can be run in a computer terminal.

[0093] It should be noted that the optional or preferred implementation of this embodiment can refer to the relevant description in the embodiment, which will not be repeated here.

[0094] The control device of the above-mentioned multi-core system on chip can also include a processor and a memory. The above-mentioned indicator acquisition module 700, working mode determination module 702, control module 704, etc. are all stored in the memory as program modules, and the processor executes the above-mentioned program modules stored in the memory to realize the corresponding functions.

[0095] The processor includes a kernel, which retrieves the corresponding program module from the memory. The kernel may be one or more. The memory may include non-permanent memory in a computer-readable medium, random access memory (RAM) and / or non-volatile memory, such as read-only memory (ROM) or flash RAM. The memory includes at least one memory chip.

[0096] According to an embodiment of the present application, an embodiment of a non-volatile storage medium is also provided. Optionally, in this embodiment, the non-volatile storage medium includes a stored program, wherein when the program is running, the device where the non-volatile storage medium is located is controlled to execute any of the control methods for the multi-core system on chip.

[0097] Optionally, in this embodiment, the non-volatile storage medium may be located in any computer terminal in a computer terminal group in a computer network, or in any mobile terminal in a mobile terminal group, and the non-volatile storage medium includes a stored program.

[0098] Optionally, when the program is running, the device where the non-volatile storage medium is located is controlled to perform the following functions: obtaining operating indicators of the multi-core system-on-chip; based on the operating indicators, determining the current operating modes corresponding to the multiple CPU cores in the multi-core system-on-chip, wherein the current operating mode is used to indicate whether the corresponding CPU core executes tasks in an independent mode, in a dynamic heterogeneous redundancy mode, or suspends execution of tasks, and the independent mode is used to indicate that the corresponding CPU core processes a task alone; the dynamic heterogeneous redundancy mode is used to indicate that the corresponding CPU core cooperates with other CPU cores to process the same task, and in the process of cooperating to process the same task, dynamically adjusts the working status and task allocation of different CPU cores; and controls the multiple CPU cores to execute tasks in accordance with the corresponding current operating modes.

[0099] According to an embodiment of the present application, an embodiment of a processor is also provided. Optionally, in this embodiment, the processor is used to run a program, wherein when the program is run, any of the control methods of the multi-core system on chip is executed.

[0100] According to an embodiment of the present application, an embodiment of a multi-core system on chip is also provided. The multi-core system on chip comprises: a plurality of CPU cores and a target CPU core, wherein the target CPU core is used to execute any one of the control methods of the multi-core system on chip.

[0101] According to an embodiment of the present application, an embodiment of a computer program product is also provided. When executed on a data processing device, the program is suitable for executing the control method steps of initializing any of the multi-core system on chip described above.

[0102] Optionally, the above-mentioned computer program product, when executed on a data processing device, is suitable for executing an initialization program having the following method steps: obtaining operating indicators of a multi-core system-on-chip; based on the operating indicators, determining the current operating modes corresponding to the multiple CPU cores in the multi-core system-on-chip, wherein the current operating mode is used to indicate whether the corresponding CPU core executes a task in an independent mode, executes a task in a dynamic heterogeneous redundancy mode, or suspends the execution of a task, and the independent mode is used to indicate that the corresponding CPU core processes a task alone; the dynamic heterogeneous redundancy mode is used to indicate that the corresponding CPU core cooperates with other CPU cores to process the same task, and dynamically adjusts the working status and task allocation of different CPU cores in the process of cooperating to process the same task; and controlling the multiple CPU cores to execute tasks in accordance with the corresponding current operating modes.

[0103] An embodiment of the present invention provides an electronic device, which includes a processor, a memory, and a program stored in the memory and executable on the processor. When the processor executes the program, the following steps are implemented: obtaining operating indicators of a multi-core system-on-chip; based on the operating indicators, determining current operating modes corresponding to multiple CPU cores in the multi-core system-on-chip, wherein the current operating mode is used to indicate whether the corresponding CPU core executes a task in an independent mode, executes a task in a dynamic heterogeneous redundant mode, or suspends execution of a task, and the independent mode is used to indicate that the corresponding CPU core processes a task alone; the dynamic heterogeneous redundant mode is used to indicate that the corresponding CPU core cooperates with other CPU cores to process the same task, and dynamically adjusts the working status and task allocation of different CPU cores during the process of cooperating to process the same task; and controlling the multiple CPU cores to execute tasks in accordance with the corresponding current operating modes.

[0104] The above sequence of the embodiments of the present invention is for description only and does not represent the superiority or inferiority of the embodiments.

[0105] In the above embodiments of the present invention, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0106] In the several embodiments provided in this application, it should be understood that the disclosed technical content can be implemented in other ways. Among them, the device embodiments described above are only schematic. For example, the division of the above modules can be a logical function division. There may be other division methods in actual implementation, such as multiple modules or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, modules or indirect coupling or communication connection of modules, which can be electrical or other forms.

[0107] The modules described above as separate components may or may not be physically separated, and the components shown as modules may or may not be physical modules, that is, they may be located in one place or distributed on multiple modules. Some or all of the modules may be selected according to actual needs to achieve the purpose of the present embodiment.

[0108] In addition, each functional module in each embodiment of the present invention may be integrated into one processing module, or each module may exist physically separately, or two or more modules may be integrated into one module. The above-mentioned integrated module may be implemented in the form of hardware or in the form of software functional modules.

[0109] If the above-mentioned integrated module is implemented in the form of a software function module and sold or used as an independent product, it can be stored in a computer-readable non-volatile storage medium. Based on this understanding, the technical solution of the present invention is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product. The computer software product is stored in a non-volatile storage medium, including a number of instructions to enable a computer device (which can be a personal computer, server or network device, etc.) to perform all or part of the steps of the various embodiments of the present invention. The aforementioned non-volatile storage medium includes: U disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), mobile hard disk, magnetic disk or optical disk and other media that can store program codes.

[0110] The above are only preferred embodiments of the present invention. It should be pointed out that, for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A control method for a multi-core system on chip, characterized in that: include: Get the operating metrics of multi-core system-on-chip; Based on the operation index, determining the current working modes respectively corresponding to the multiple CPU cores in the multi-core system-on-chip, wherein the current working mode is used to indicate whether the corresponding CPU core executes the task in an independent mode, executes the task in a dynamic heterogeneous redundancy mode, or suspends the execution of the task, and the independent mode is used to indicate that the corresponding CPU core processes a task alone; the dynamic heterogeneous redundancy mode is used to indicate that the corresponding CPU core cooperates with other CPU cores to process the same task, and dynamically adjusts the working status and task allocation of different CPU cores in the process of cooperating to process the same task; The multiple CPU cores are controlled to execute tasks according to the corresponding current working modes respectively.

2. The method according to claim 1, characterized in that The obtaining of the operating index of the multi-core system on chip includes: Acquire an application scenario of the multi-core system on chip, wherein the application scenario includes a fixed working mode scenario or an automatic working mode switching scenario; When the application scenario is an automatic working mode switching scenario, the operating indicator of the multi-core system on chip is obtained.

3. The method according to claim 2, characterized in that The method further comprises: When the application scenario is a fixed working mode scenario, obtaining fixed working modes pre-set for the multiple CPU cores respectively; The multiple CPU cores are controlled to execute tasks according to corresponding fixed working modes.

4. The method according to claim 1, characterized in that: The determining, based on the operation index, current operating modes respectively corresponding to the plurality of CPU cores in the multi-core system on chip comprises: Based on the operation index, determining a target CPU allocation strategy, wherein the target CPU allocation strategy is at least used to indicate the number of first CPU cores that execute tasks in the independent mode and the number of second CPU cores that execute tasks in the dynamic heterogeneous redundancy mode; Based on the target CPU allocation strategy, current working modes corresponding to the multiple CPU cores are determined.

5. The method according to claim 4, characterized in that The step of determining a target CPU allocation strategy based on the operating indicator includes: Determining a target indicator range to which the operating indicator belongs from a plurality of indicator ranges; The CPU allocation policy corresponding to the target indicator range among the CPU allocation policies corresponding to the multiple indicator ranges is determined as the target CPU allocation policy.

6. The method according to claim 4, characterized in that In the case where there are multiple operating indicators, determining the target CPU allocation strategy based on the operating indicators includes: Determine the weight values ​​corresponding to multiple operating indicators; Performing weighted calculation based on the multiple operating indicators and the weight values ​​respectively corresponding to the multiple operating indicators to obtain an indicator score value; Based on the indicator score value, the target CPU allocation strategy is determined.

7. The method according to claim 6, characterized in that The step of determining the target CPU allocation strategy based on the indicator score value includes: Determine a target indicator scoring range to which the indicator scoring value belongs from a plurality of indicator scoring ranges; The CPU allocation strategy corresponding to the target indicator score range among the CPU allocation strategies corresponding to the multiple indicator score ranges is determined as the target CPU allocation strategy.

8. The method according to any one of claims 1 to 7, characterized in that The operation index includes the task level of the task to be executed, and / or at least one of the following: the temperature of the multi-core system on chip, the task congestion, the task safety level, and the service quality level.

9. A multi-core system on chip, characterized in that: include: A plurality of CPU cores and a target CPU core, wherein the target CPU core is used to execute the control method of the multi-core system on chip as claimed in any one of claims 1 to 8.

10. A computer program product, comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the control method of the multi-core system on chip described in any one of claims 1 to 8 are implemented.

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