Sparse matrix vector multiplication parallel optimization method and system based on CSR storage format

Abstract

The invention provides a sparse matrix vector multiplication parallel optimization method and system based on a CSR storage format, and relates to the technical field of high-performance parallel computing, and the method comprises the steps: obtaining sparse matrix data stored in the CSR format; splitting and integrating the sparse matrix by adopting a row grouping method, dividing rows with similar non-zero element numbers into the same group, and configuring computing resources for each group; the method comprises the following steps: firstly, pre-loading sparse matrix data in each group, defining a texture memory, and pre-loading the sparse matrix data into the texture memory; an independent kernel is set for each group to execute SpMV calculation of all rows in each group, and non-zero elements of sparse matrix data and corresponding vector data are preloaded into a shared memory in the calculation execution process of the kernel; and the kernel executes SpMV calculation by adopting a hybrid static-dynamic thread scheduling method until all rows are calculated, and a final result is obtained.

Description

Technical Field

[0001] The present disclosure relates to the field of high-performance parallel computing technology, and in particular to a sparse matrix-vector multiplication parallel optimization method and system based on a CSR storage format. Background Art

[0002] The statements in this section merely provide background information related to the present disclosure and do not necessarily constitute prior art.

[0003] In modern computing applications, sparse matrix-vector multiplication (SpMV) is essential for processing large sparse matrices. It plays a core role in many fields such as scientific computing, engineering simulation, image processing, and machine learning. The SpMV operation involves multiplying a sparse matrix A with a dense vector x to produce a new vector y. From a mathematical point of view, this process can be expressed as y = A × x, where y represents the result of the resulting vector.

[0004] Graphics processing units (GPUs) are highly favored in the field of scientific computing due to their high throughput and powerful parallel processing capabilities. However, despite the excellent performance of GPUs in many computing tasks, GPU-based SpMV algorithms still face some performance bottlenecks, the most important of which are unbalanced computing load and discontinuous memory access.

[0005] Unbalanced computational load is usually caused by the uneven distribution of non-zero elements in sparse matrices, which may cause some threads to perform a large amount of computation while other threads may be idle. Unbalanced load reduces the computational efficiency of the GPU and increases the computation time. Discontinuous memory access is usually caused by the limitations of the storage format itself. Taking the CSR format as an example, since the index values ​​in col_idx are sorted in a non-continuous order, the operation of accessing vector x is also non-continuous. A separate memory transaction may be required for each non-continuous access, which will increase the access overhead and reduce the cache hit rate, thus seriously affecting the execution efficiency of SpMV. Summary of the invention

[0006] In order to solve the above problems, the present invention proposes a sparse matrix-vector multiplication parallel optimization method and system based on the CSR storage format, comprehensively considers the load balancing and memory access efficiency on large-scale parallel processors, designs a new SpMV algorithm based on the CSR format, combines hybrid static-dynamic thread scheduling, and dynamically adjusts thread allocation according to the actual computing load to adapt to the computing requirements of different rows, thereby maintaining the predictability of static scheduling and the flexibility of dynamic scheduling, thereby maximizing the efficiency of parallel computing.

[0007] According to some embodiments, the present disclosure adopts the following technical solutions:

[0008] The parallel optimization method of sparse matrix-vector multiplication based on CSR storage format includes:

[0009] Get sparse matrix data stored in CSR format;

[0010] The sparse matrix is ​​split and integrated using the row grouping method, rows with similar numbers of non-zero elements are divided into the same group, and computing resources are allocated for each group;

[0011] First, the sparse matrix data in each group is preloaded, a texture memory is defined, and the sparse matrix data is preloaded into the texture memory;

[0012] A separate kernel is set for each group to perform SpMV calculations on all rows in each group. During the kernel calculation, the non-zero elements of the sparse matrix data and the corresponding vector data are preloaded into the shared memory.

[0013] The kernel uses a hybrid static-dynamic thread scheduling method to perform SpMV calculations until all rows are calculated and the final results are obtained.

[0014] According to some embodiments, the present disclosure adopts the following technical solutions:

[0015] A sparse matrix-vector multiplication parallel optimization system based on CSR storage format, including:

[0016] A data acquisition module, used to acquire sparse matrix data stored in CSR format;

[0017] The preprocessing module is used to split and integrate the sparse matrix using the row grouping method, divide the rows with similar numbers of non-zero elements into the same group, and configure computing resources for each group;

[0018] A preloading module is used to preload the sparse matrix data in each group, define a texture memory, and preload the sparse matrix data into the texture memory;

[0019] The parallel computing module is used to set up a separate kernel for each group to perform SpMV calculations on all rows in each group. During the kernel calculation process, the non-zero elements of the sparse matrix data and the corresponding vector data are preloaded into the shared memory; the kernel uses a hybrid static-dynamic thread scheduling method to perform SpMV calculations until all row calculations are completed to obtain the final result.

[0020] According to some embodiments, the present disclosure adopts the following technical solutions:

[0021] A computer program product includes a computer program, which, when executed by a processor, implements the sparse matrix-vector multiplication parallel optimization method based on the CSR storage format.

[0022] According to some embodiments, the present disclosure adopts the following technical solutions:

[0023] A non-transitory computer-readable storage medium is used to store computer instructions. When the computer instructions are executed by a processor, the sparse matrix-vector multiplication parallel optimization method based on the CSR storage format is implemented.

[0024] According to some embodiments, the present disclosure adopts the following technical solutions:

[0025] An electronic device comprises: a processor, a memory and a computer program; wherein the processor is connected to the memory, the computer program is stored in the memory, and when the electronic device is running, the processor executes the computer program stored in the memory so that the electronic device executes the sparse matrix-vector multiplication parallel optimization method based on the CSR storage format.

[0026] Compared with the prior art, the present invention has the following beneficial effects:

[0027] The disclosed sparse matrix vector multiplication parallel optimization method based on CSR storage format comprehensively considers two key factors: optimizing load balancing on large-scale parallel processors and improving memory access efficiency, and designs a new SpMV algorithm based on CSR format. Through the following three carefully designed steps, significant performance improvement is achieved: first, row grouping, which first reads the number of non-zero elements in each row of the matrix, and divides rows with similar numbers into the same group, so that each processing unit undertakes relatively uniform computing tasks, thereby effectively solving the load balancing problem; second, matrix and vector preloading, before performing product and sum calculations, the non-zero elements of the matrix and the corresponding vector data are preloaded into the cache in the form of a two-dimensional array; third, hybrid static-dynamic thread scheduling, combining the advantages of static and dynamic thread scheduling, dynamically adjusting thread allocation according to the actual computing load to adapt to the computing needs of different rows. This hybrid scheduling strategy not only maintains the predictability of static scheduling, but also has the flexibility of dynamic scheduling, thereby maximizing the efficiency of parallel computing.

[0028] The disclosed sparse matrix-vector multiplication parallel optimization method based on CSR storage format and the proposed new SpMV algorithm based on CSR format achieve efficient processing of large-scale sparse matrix-vector multiplication through the collaborative work of three steps: row grouping, matrix and vector preloading, and hybrid static-dynamic thread scheduling. This comprehensive design method not only improves the overall performance of the algorithm, but also provides a new research direction and optimization strategy for the field of sparse matrix computing. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The accompanying drawings constituting a part of the present disclosure are used to provide a further understanding of the present disclosure. The illustrative embodiments of the present disclosure and their descriptions are used to explain the present disclosure and do not constitute an improper limitation on the present disclosure.

[0030] Figure 1 A flow chart of a parallel optimization method for sparse matrix-vector multiplication based on CSR storage format according to an embodiment of the present disclosure;

[0031] Figure 2 The matrix information stored in the CSR format according to the embodiment of the present disclosure;

[0032] Figure 3 To implement the SpMV process based on row grouping according to the embodiment of the present disclosure;

[0033] Figure 4 The implementation idea of ​​preloading the sparse matrix A and vector x of the embodiment of the present disclosure is as follows;

[0034] Figure 5 This is an implementation idea of ​​the hybrid static-dynamic thread scheduling method of the embodiment of the present disclosure. DETAILED DESCRIPTION

[0035] The present disclosure is further described below in conjunction with the accompanying drawings and embodiments.

[0036] It should be noted that the following detailed descriptions are all illustrative and are intended to provide further explanation of the present disclosure. Unless otherwise specified, all technical and scientific terms used herein have the same meanings as those commonly understood by those skilled in the art to which the present disclosure belongs.

[0037] It should be noted that the terms used herein are only for describing specific embodiments and are not intended to limit the exemplary embodiments according to the present disclosure. As used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. In addition, it should be understood that when the terms "comprising" and / or "including" are used in this specification, it indicates the presence of features, steps, operations, devices, components and / or combinations thereof.

[0038] Example 1

[0039] In one embodiment of the present disclosure, a sparse matrix-vector multiplication parallel optimization method based on the CSR storage format is provided, including:

[0040] Step 1: Get sparse matrix data stored in CSR format;

[0041] Step 2: Split and integrate the sparse matrix using the row grouping method, group rows with similar numbers of non-zero elements into the same group, and allocate computing resources for each group;

[0042] Step 3: preload the sparse matrix data in each group, define a texture memory, and preload the sparse matrix data into the texture memory;

[0043] Step 4: Set up a separate kernel for each group to perform SpMV calculations on all rows in each group. During the kernel calculation process, preload the non-zero elements of the sparse matrix data and the corresponding vector data into the shared memory.

[0044] Step 5: The kernel uses a hybrid static-dynamic thread scheduling method to perform SpMV calculations until all rows are calculated and the final result is obtained.

[0045] As an embodiment, the present invention discloses a sparse matrix-vector multiplication parallel optimization method based on the CSR storage format, proposes a novel SpMV algorithm based on the CSR format, and realizes efficient processing of large-scale sparse matrix-vector multiplication through the coordinated work of three steps: row grouping, matrix and vector preloading, and hybrid static-dynamic thread scheduling. The specific implementation process is as follows:

[0046] Step 1: Get sparse matrix data stored in CSR format;

[0047] The CSR (Compressed Sparse Row) format is a data structure used to store and process sparse matrices, and is particularly suitable for row access operations on sparse matrices. The CSR format is mainly composed of three arrays: the values ​​array, the col_idx array, and the row_offsets array. Among them, the values ​​array stores the specific values ​​of all non-zero elements row by row; the col_idx array stores the column indexes of all non-zero elements row by row; and the row_offsets array stores the position of the first non-zero element in each row of the matrix in the values ​​array and the col_idx array. Specifically, input the matrix data stored in the CSR format to obtain the values ​​array, col_idx array, and row_offsets array. Figure 2 Given a matrix information stored in CSR format.

[0048] Step 2: Split and integrate the sparse matrix using the row grouping method, group rows with similar numbers of non-zero elements into the same group, and allocate computing resources for each group;

[0049] Specifically, step 2.1: split and integrate the sparse matrix using the row grouping method, and divide the rows with similar numbers of non-zero elements into the same group, including:

[0050] Regarding how to divide, the present disclosure designs a division rule G i, which is a set partitioning problem in mathematics, and its mathematical expression is G i =[a i , a i+1 -1](i>0). i Represents that in all rows, the number of non-zero elements in each row is in a i to a i+1 -1 range (including a i and a i+1 -1). i It is a sequence in mathematics, and its general formula is:

[0051]

[0052] According to the general formula a i , G i It can be specifically divided into sets such as G1=[1, 2], G2=[3, 4], G3=[5, 8], G4=[9, 12], etc. Figure 3 The process from (a) to (b) embodies the idea of ​​row grouping.

[0053] Furthermore, in order to store each group G i The corresponding data defines a structure named group. Its member variables include the lower limit of the number of elements al, the upper limit of the number of elements au, the vector dynamic array rows, the total number of non-zero elements nnz, the size of the thread group groupsize, the size of the thread block blocksize, the number of thread blocks blocks, and the sub-matrix data of the CPU end in each group (stored in a two-dimensional array matrix with a length of a i+1 -1, the width is the size of the rows array, which is set by calling the size() function) and the sub-matrix data on the GPU side in each group (stored in a two-dimensional pointer variable GPU_matrix, allocated using the cudaMallocPitch function, with the same length and width as the matrix array).

[0054] Among them, al and au store a respectively. i and a i+1 -1; the rows array is used to store the row index of the rows that meet the conditions; nnz is used to store the current group G i The total number of non-zero elements in G; groupsize, blocksize and blocks are used to store the group G respectively. i The resource configuration when executing the calculation, the configuration method will be described in step 2.2); the sub-matrix data of the CPU and GPU in each group is the current group G i Detailed calculation information for all rows contained within.

[0055] After getting the structure group, a structure array groups will be created to store the data in multiple groups. Before that, a one-dimensional array Array_num of size n needs to be created to store the number of non-zero elements in each row of the sparse matrix. For the row with row index i, the value of Array_num[i] is set to (row_offsets[i+1]-row_offsets[i]).

[0056] Then, we traverse the array Array_num from the beginning, load all rows into the corresponding structure variables, and then get the complete structure array groups. The structure variables with empty non-zero elements are not considered. The data al, au, rows, and nnz can be updated after traversing all rows.

[0057] Step 2.2: Configure computing resources for each group, including:

[0058] After the grouping is completed, each group G i Start a separate kernel K i Perform SpMV calculations for all rows in it. Figure 3 (c) shows the SpMV execution mode. i When performing calculations, the size of groupsize is set to 2 to the power of μ(μ∈N), and the specific value is to satisfy groupsize≤min(128, (a i+1 -1) / 2) is to ensure that each thread has sufficient computing load. For example, kernel K3 uses a thread group with groupsize=4 to perform calculations. Since the parallel SpMV algorithm will eventually calculate the final result through the reduction operation, if the groupsize is too large, it will cause too much thread synchronization overhead. Therefore, the upper limit of groupsize is set to 128.

[0059] In addition, each K i The number of opened thread blocks is configured by (nnz+k*blocksize-1) / k*blocksize, where nnz is G i The total number of non-zero elements in the block, blocksize is the size of the block, and the default value is 1024 in most cases. i+1 -1) / groupsize, which indicates the number of iterations that the thread group performs SpMV calculation on a row of data. In most cases, k = 2 or 3.

[0060] Step 3: Preload the sparse matrix data in each group, define a texture memory, and preload the sparse matrix data into the texture memory;

[0061] Step 3.1: According to the rows array in each group obtained in step 2, the corresponding information of the large sparse matrix is ​​read from the values, column_indices and row_offsets arrays to fill the two-dimensional array matrix in each group. Among them, the matrix is ​​stored in order from top to bottom and from left to right, and the number of non-zero elements is less than a i+1 For the row with -1, the subsequent positions are all set to 0. In this way, multiple sub-matrices can be obtained and saved in the structure array groups.

[0062] Step 3.2: Based on the obtained two-dimensional array matrix, use cudaMemcpy2D to copy the data in the matrix to the pointer variable GPU_matrix in the device memory. In subsequent calculations, this two-dimensional array can be accessed by calculating the two-dimensional index.

[0063] Step 3.3: Declare a texture reference texRef, specify the data type as float, set the dimension to 2, and set the read mode to cudaReadModeNormalizedFloat. Finally, use cudaBindTextur e The 2D function binds the previously allocated device memory GPU_matrix to the texture reference texRef.

[0064] Step 4: Set up a separate kernel for each group to perform SpMV calculations on all rows in each group. During the kernel's calculation process, preload the non-zero elements of the sparse matrix data and the corresponding vector data into the shared memory. The kernel uses a hybrid static-dynamic thread scheduling method to perform SpMV calculations until all rows are calculated and the final result is obtained.

[0065] Specifically, for each group G i Open a separate kernel K respectively i To perform SpMV calculation for all rows, perform SpMV calculation based on the resources configured in step 2.

[0066] Step 4.1: In most applications, the vector x corresponding to the non-zero elements will be updated frequently, so the vector x corresponding to the non-zero elements is not preloaded into the texture memory before starting the kernel. Specially, here we choose to preload the vector x corresponding to the non-zero elements based on shared memory during kernel execution. The idea is: before performing product and sum operations, the data of some rows will be preloaded into the two-dimensional shared memory array shared_x to cache the data in the vector x corresponding to the non-zero elements until all rows are calculated. The preloading process needs to be implemented in combination with the rows array and the col_idx array. The rows array is used to determine which rows need to be loaded, and the col_idx array is used to determine the location of the specific data that needs to be loaded in the vector x corresponding to the non-zero elements. Similarly, if the number of non-zero elements is less than a i+1 For rows with -1, the subsequent positions are also set to 0.

[0067] For different groups G i Open kernel K i , the size and structure of the array shared_x will be dynamically set to (blocksize / groupsize)*(a i+1 -1). where blocksize / groupsize and a i+1 -1 represents the number of rows and columns of the two-dimensional array respectively. Figure 4 The specific ideas for preloading the sparse matrix A and vector x are given.

[0068] It is worth noting that the capacity of shared memory is usually limited by the hardware. Therefore, due to the different thread organization forms, blocksiz e The size may also need to be changed.

[0069] Step 4.2: The idea of ​​the hybrid static-dynamic thread scheduling method is to first divide the computing task into n steps of iteration. The first n-1 steps of iteration are divided into tasks through static thread scheduling, while the nth step of iteration is divided into tasks through dynamic thread scheduling. This algorithm can further achieve load balancing and reduce synchronization overhead. Figure 5 The implementation idea of ​​the hybrid static-dynamic thread scheduling method is given.

[0070] Specifically, the specific process of the hybrid static-dynamic thread scheduling method is as follows: First, the computing task is divided into Step. The calculation of the first step is carried out in sequence according to the thread number. For idle threads, the remaining computing tasks will be dynamically executed until the row of computing is completed. This method can further achieve load balancing and reduce synchronization overhead. Figure 5 The implementation idea of ​​the hybrid static-dynamic thread scheduling method is given.

[0071] Subsequent calculations only need to multiply and sum the preloaded data GPU_matrix and shared_x according to the corresponding positions to get the final result.

[0072] Example 2

[0073] In one embodiment of the present disclosure, a sparse matrix-vector multiplication parallel optimization system based on the CSR storage format is provided, comprising:

[0074] A data acquisition module, used to acquire sparse matrix data stored in CSR format;

[0075] The preprocessing module is used to split and integrate the sparse matrix using the row grouping method, divide the rows with similar numbers of non-zero elements into the same group, and configure computing resources for each group;

[0076] A preloading module is used to preload the sparse matrix data in each group, define a texture memory, and preload the sparse matrix data into the texture memory;

[0077] The parallel computing module is used to set up a separate kernel for each group to perform SpMV calculations on all rows in each group. During the kernel calculation process, the non-zero elements of the sparse matrix data and the corresponding vector data are preloaded into the shared memory; the kernel uses a hybrid static-dynamic thread scheduling method to perform SpMV calculations until all row calculations are completed to obtain the final result.

[0078] Example 3

[0079] In one embodiment of the present disclosure, a computer program product is provided, including a computer program, which, when executed by a processor, implements the sparse matrix-vector multiplication parallel optimization method based on the CSR storage format.

[0080] Example 4

[0081] In one embodiment of the present disclosure, a non-transitory computer-readable storage medium is provided, wherein the non-transitory computer-readable storage medium is used to store computer instructions. When the computer instructions are executed by a processor, the sparse matrix-vector multiplication parallel optimization method based on the CSR storage format is implemented.

[0082] Example 5

[0083] In one embodiment of the present disclosure, an electronic device is provided, including: a processor, a memory, and a computer program; wherein the processor is connected to the memory, the computer program is stored in the memory, and when the electronic device is running, the processor executes the computer program stored in the memory, so that the electronic device executes the sparse matrix-vector multiplication parallel optimization method based on the CSR storage format.

[0084] The present disclosure is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present disclosure. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0085] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.

[0086] Although the above describes the specific implementation methods of the present disclosure in conjunction with the accompanying drawings, it is not intended to limit the scope of protection of the present disclosure. Technical personnel in the relevant field should understand that on the basis of the technical solution of the present disclosure, various modifications or variations that can be made by those skilled in the art without creative work are still within the scope of protection of the present disclosure.

Claims

1. A sparse matrix-vector multiplication parallel optimization method based on CSR storage format, characterized in that: include: Get sparse matrix data stored in CSR format; The sparse matrix is ​​split and integrated using the row grouping method, rows with similar numbers of non-zero elements are divided into the same group, and computing resources are allocated for each group; First, the sparse matrix data in each group is preloaded, a texture memory is defined, and the sparse matrix data is preloaded into the texture memory; A separate kernel is set for each group to perform SpMV calculations on all rows in each group. During the kernel calculation, the non-zero elements of the sparse matrix data and the corresponding vector data are preloaded into the shared memory. The kernel uses a hybrid static-dynamic thread scheduling method to perform SpMV calculations until all rows are calculated and the final result is obtained.

2. The sparse matrix-vector multiplication parallel optimization method based on CSR storage format as claimed in claim 1, characterized in that: Get the sparse matrix data stored in CSR format and get three arrays: values ​​array, col_idx array, and row_offsets array. If it is not stored in CSR format, format conversion is required.

3. The sparse matrix-vector multiplication parallel optimization method based on CSR storage format as claimed in claim 1, characterized in that: The sparse matrix is ​​split and integrated by using the row grouping method, and the rows with similar number of non-zero elements are divided into the same group, including: the row grouping method is based on the division rule G i =[a i ,a i+1 -1](i>0), where a i Satisfies the following formula: Among them, G i Represents the number of non-zero elements in [a i , a i+1 -1], define a group structure to store each group G i The corresponding sparse matrix data of the structure includes the lower limit of the number of elements, the upper limit of the number of elements, the dynamic array, the total number of non-zero elements, the size of the thread group, the size of the thread block, the number of thread blocks, the sub-sparse matrix data of the CPU side in each group, and the sub-sparse matrix data of the GPU side in each group.

4. The sparse matrix-vector multiplication parallel optimization method based on CSR storage format as claimed in claim 1, characterized in that: Configuring computing resources for each group includes: after obtaining the structure group, creating a structure array groups to store the data in multiple groups, allocating resources for subsequent computing, and setting the size of groupsize to the power of 2 μ(μ∈N), with the specific value satisfying groupsize≤min(128, (a i+1 -1) / 2), the number of blocks of threads enabled for each kernel calculation is configured by (nnz+k*blocksize-1) / k*blocksize.

5. The sparse matrix-vector multiplication parallel optimization method based on CSR storage format as claimed in claim 1, characterized in that: First, the sparse matrix data in each group is preloaded, a texture memory is defined, and the sparse matrix data is preloaded into the texture memory, including: according to the rows array in each group, the corresponding information of the large sparse matrix is ​​read from the values ​​array, the column_indices array and the row_offsets array to fill the two-dimensional array matrix in each group; according to the obtained two-dimensional array matrix, cudaMemcpy2D is used to copy the data in the matrix to the pointer variable GPU_matrix in the device memory, a texture memory is defined, the data type is specified as float, and the cudaBindTexture2D function is used to bind the GPU matrix to the texture memory.

6. The sparse matrix-vector multiplication parallel optimization method based on CSR storage format as claimed in claim 1, characterized in that: Set up a separate kernel for each group to perform SpMV calculations on all rows in each group. During the kernel calculation process, preload the non-zero elements of the sparse matrix data and the corresponding vector data into the shared memory, including: before performing product and sum operations, preload the sparse matrix data of some rows into the two-dimensional shared memory array shared_x to cache the data in the vector x corresponding to the non-zero elements until all rows are calculated. The preloading process needs to be implemented in conjunction with the rows array and the col_idx array. The rows array is used to determine which rows need to be loaded, and the col_idx array is used to determine the location of the specific data that needs to be loaded in the vector x. The number of non-zero elements is less than a i+1 For rows with -1, the subsequent positions are also set to 0.

7. A sparse matrix-vector multiplication parallel optimization system based on CSR storage format, characterized in that: include: A data acquisition module, used to acquire sparse matrix data stored in CSR format; The preprocessing module is used to split and integrate the sparse matrix using the row grouping method, divide the rows with similar numbers of non-zero elements into the same group, and configure computing resources for each group; A preloading module is used to preload the sparse matrix data in each group, define a texture memory, and preload the sparse matrix data into the texture memory; The parallel computing module is used to set up a separate kernel for each group to perform SpMV calculations on all rows in each group. During the kernel calculation process, the non-zero elements of the sparse matrix data and the corresponding vector data are preloaded into the shared memory; the kernel uses a hybrid static-dynamic thread scheduling method to perform SpMV calculations until all row calculations are completed to obtain the final result.

8. A computer program product, comprising a computer program, characterized in that When the computer program is executed by a processor, the parallel optimization method for sparse matrix-vector multiplication based on the CSR storage format described in any one of claims 1 to 6 is implemented.

9. A non-transitory computer-readable storage medium, characterized in that: The non-transitory computer-readable storage medium is used to store computer instructions. When the computer instructions are executed by the processor, the sparse matrix-vector multiplication parallel optimization method based on the CSR storage format as described in any one of claims 1 to 6 is implemented.

10. An electronic device, characterized in that: include: A processor, a memory and a computer program; wherein the processor is connected to the memory, the computer program is stored in the memory, and when the electronic device is running, the processor executes the computer program stored in the memory to enable the electronic device to implement the sparse matrix-vector multiplication parallel optimization method based on the CSR storage format as described in any one of claims 1 to 6.

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