Mainboard performance optimization method and optimization system

Abstract

The invention provides a mainboard performance optimization method and optimization system, and relates to the technical field of mainboards, the mainboard comprises a plurality of functional units, the method comprises the following steps: determining the connection relationship among the functional units, and collecting the historical data of each functional unit; constructing an agent model for the mainboard based on the connection relationship, the historical operation data and the historical performance data; forming a first optimization target set through random combination, and performing initial prediction of mainboard performance by utilizing the proxy model and combining a Bayesian optimization method to obtain an initial prediction result; performing iterative optimization in a Bayesian optimization framework based on the initial prediction result, and identifying a non-dominated solution by using a multi-objective optimization algorithm in the iterative optimization process to form a Pareto leading edge; and performing target matching on the input second optimization target set based on all the first optimization target sets of all the random combinations, and applying the optimal configuration corresponding to the matched first optimization target set to each functional unit so as to realize performance optimization of the mainboard.

Description

Technical Field

[0001] The present invention relates to the technical field of motherboards, and in particular to a motherboard performance optimization method and optimization system. Background Art

[0002] With the rapid development of computer technology, the performance optimization of the motherboard, as the core component of the computer system, has attracted increasing attention from the industry. The motherboard integrates many functional units, such as processors, memory, input and output interfaces, etc. These functional units transmit and interact with each other through complex connections, which together determine the overall performance of the motherboard. However, due to the high complexity of motherboard design and the mutual influence between functional units, traditional performance optimization methods often fail to achieve ideal results.

[0003] Traditional motherboard performance optimization usually relies on engineers' experience and experimental testing. This method is not only time-consuming and laborious, but also difficult to fully consider the interaction effects between all functional units on the motherboard. In addition, with the continuous update of motherboard design and the emergence of new technologies, traditional methods are often difficult to adapt to new performance optimization needs.

[0004] Therefore, it is necessary to provide a motherboard performance optimization method and optimization system to solve the above technical problems. Summary of the invention

[0005] In order to solve the above technical problems, the present invention provides a motherboard performance optimization method and optimization system, which comprehensively considers the connection relationship, interaction effect and multi-objective optimization requirements of various functional units on the motherboard, and realizes comprehensive optimization of the motherboard performance by constructing an accurate proxy model and combining the Bayesian optimization method and multi-objective optimization algorithm.

[0006] The present invention provides a method for optimizing the performance of a mainboard, wherein the mainboard includes a plurality of functional units, and the optimization method includes the following steps:

[0007] Determine the connection relationship between each functional unit, and collect historical data of each functional unit, wherein the historical data includes historical operation data and historical performance data;

[0008] Building an agent model for the motherboard based on the connection relationship, historical operation data, and historical performance data, wherein the agent model is used to simulate the performance of the motherboard under different configurations;

[0009] A first optimization target set is formed by random combination, and the proxy model is used in combination with a Bayesian optimization method to perform an initial prediction of the motherboard performance to obtain an initial prediction result;

[0010] Based on the initial prediction results, performing iterative optimization within a Bayesian optimization framework, and identifying non-dominated solutions using a multi-objective optimization algorithm during the iterative optimization process to form a Pareto front;

[0011] Based on all the first optimization target sets of all the random combinations, the input second optimization target set is targeted and matched, and the optimal configuration corresponding to the matched first optimization target set is applied to each functional unit to achieve performance optimization of the mainboard.

[0012] Preferably, determining the connection relationship between the functional units and collecting historical data of each functional unit includes:

[0013] Identify the types of all functional units on the mainboard and their physical connection interfaces, and construct a logical connection diagram between the functional units based on the types and physical connection interfaces;

[0014] Collect and record the communication protocols and data exchange frequencies between the functional units, and use them as the connection relationship between the functional units;

[0015] Collect historical operation data and corresponding historical performance data of each functional unit during operation to form complete historical data.

[0016] Preferably, building an agent model for the mainboard based on the connection relationship, historical operation data and historical performance data includes:

[0017] Preprocessing the collected historical data;

[0018] According to the connection relationship between each functional unit, the input feature of the proxy model is defined, wherein the input feature is designed to quantify and reflect the interaction effect generated by the connection relationship between each functional unit;

[0019] An initial proxy model is built based on a machine learning algorithm, and the proxy model is trained and optimized based on historical operation data and historical performance data to obtain a proxy model that simulates the performance of the motherboard under different configurations.

[0020] Preferably, the first optimization target set is formed by random combination, and the proxy model is used in combination with the Bayesian optimization method to perform initial prediction of the motherboard performance to obtain the initial prediction result, including:

[0021] Randomly selecting multiple optimization targets from a pre-built optimization target library and combining them to form a first optimization target set, wherein the optimization target library includes multiple optimization directions related to motherboard performance;

[0022] Using the constructed proxy model, according to the current first optimization target set, the input parameters of the proxy model are set, wherein the input parameters are defined as indicators reflecting the performance requirements of each optimization target in the first optimization target set on the motherboard;

[0023] Combined with Bayesian optimization method, the proxy model is used to make a preliminary prediction of the motherboard's performance;

[0024] When the optimization termination condition is met, the iteration is stopped and the current optimal initial prediction result is output, wherein the initial prediction result corresponds to the predicted optimal value of the motherboard performance under the first optimization target set and its corresponding configuration.

[0025] Preferably, the method combines the Bayesian optimization method and uses the proxy model to make a preliminary prediction of the performance of the motherboard, including:

[0026] The Gaussian process regression model in the Bayesian optimization method is used to estimate the performance distribution of the motherboard under different configurations;

[0027] The next most promising configuration is selected by obtaining the function, and the proxy model is used to predict the performance of the motherboard under this configuration;

[0028] The Gaussian process regression model is iteratively updated until the optimization termination condition is met, and the current optimal initial prediction result is output.

[0029] Preferably, the iterative optimization is performed within a Bayesian optimization framework based on the initial prediction results, and a multi-objective optimization algorithm is used to identify non-dominated solutions during the iterative optimization process to form a Pareto front, including:

[0030] Iteratively selecting and evaluating new configurations based on the initial prediction results within a Bayesian optimization framework;

[0031] The multi-objective optimization algorithm NSGA-II is used to identify the non-dominated solutions in each iteration;

[0032] The proxy model is iteratively updated until the termination condition is met, and the current optimal Pareto front and its corresponding non-dominated solution are output, wherein each non-dominated solution in the Pareto front represents the optimal configuration of each functional unit under the current first optimization objective set.

[0033] Preferably, the step of performing target matching on the input second optimization target set based on all first optimization target sets of all random combinations, and applying the optimal configuration corresponding to the matched first optimization target set to each functional unit includes:

[0034] Based on all the randomly combined first optimization target sets, matching the target quantity of the standardized second optimization target set;

[0035] Calculating the Euclidean distance between the second optimization target set and the first optimization target set after each target quantity is matched;

[0036] Filter out the first optimization target set with the smallest Euclidean distance to the standardized second optimization target set;

[0037] The optimal configuration corresponding to the screened first optimization target set is applied to each functional unit.

[0038] Preferably, the calculation formula of the Euclidean distance is:

[0039]

[0040] Among them, D(G 2 , G 1 ) is the second optimization target set G 2 and the first optimization target set G 1 The Euclidean distance between 2 =(g 21 , g 22 , …, g 2n ), G 2 =(g 11 , g 12 , …, g 1n ), g 2n and g 1n are the optimization targets in the second optimization target set and the first optimization target set respectively, and n is the number of targets.

[0041] The present invention also provides a motherboard performance optimization system for executing a motherboard performance optimization method, wherein the motherboard includes a plurality of functional units, and the optimization system includes:

[0042] A data collection module, used to determine the connection relationship between the functional units and collect historical data of each functional unit, wherein the historical data includes historical operation data and historical performance data;

[0043] A model building module, used to build an agent model for the mainboard based on the connection relationship, historical operation data and historical performance data, wherein the agent model is used to simulate the performance of the mainboard under different configurations;

[0044] An initial prediction module, used to form a first optimization target set by random combination, use the proxy model, and combine the Bayesian optimization method to make an initial prediction of the motherboard performance to obtain an initial prediction result;

[0045] An iterative optimization module, used for performing iterative optimization within a Bayesian optimization framework based on the initial prediction results, and identifying non-dominated solutions using a multi-objective optimization algorithm during the iterative optimization process to form a Pareto frontier;

[0046] The configuration application module is used to match the input second optimization target set based on all the first optimization target sets of all random combinations, and apply the optimal configuration corresponding to the matched first optimization target set to each functional unit to achieve performance optimization of the mainboard.

[0047] Compared with the related art, the motherboard performance optimization method and optimization system provided by the present invention have the following beneficial effects:

[0048] The present invention constructs an accurate proxy model by determining the connection relationship between functional units and collecting historical data. It can simulate the performance of the motherboard under different configurations. It combines the Bayesian optimization method and the multi-objective optimization algorithm to achieve efficient iterative optimization, form a Pareto frontier, and provide diversified optimal configuration options. At the same time, according to the second optimization target set input by the user, the most similar first optimization target set is found through target matching, and the corresponding optimal configuration is applied to the motherboard, thereby achieving comprehensive optimization of the motherboard performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] Figure 1 A flow chart of a method for optimizing motherboard performance provided by the present invention;

[0050] Figure 2 A module structure diagram of a mainboard performance optimization system provided by the present invention. DETAILED DESCRIPTION

[0051] The present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It is to be understood that the specific embodiments described herein are only used to explain the present invention, rather than to limit the present invention. It should also be noted that, for ease of description, only the parts related to the present invention, rather than all structures, are shown in the accompanying drawings. In addition, the embodiments of the present invention and the features in the embodiments may be combined with each other without conflict.

[0052] It should also be noted that, for ease of description, only the part relevant to the present invention but not all the content is shown in the accompanying drawings. It should be mentioned before discussing the exemplary embodiments in more detail that some exemplary embodiments are described as the processing or method described as a flow chart. Although the flow chart describes each operation (or step) as being processed sequentially, many operations therein can be implemented in parallel, concurrently or simultaneously. In addition, the order of each operation can be rearranged. When its operation is completed, the processing can be terminated, but it can also have additional steps not included in the accompanying drawings. The processing can correspond to a method, a function, a procedure, a subroutine, a subprogram, etc.

[0053] Embodiment 1

[0054] The present invention provides a method for optimizing the performance of a motherboard. The motherboard includes a plurality of functional units. The functional units refer to independent parts on the motherboard that are responsible for specific tasks, including but not limited to:

[0055] CPU: Central Processing Unit, responsible for executing instructions.

[0056] Memory: RAM that stores temporary data.

[0057] Storage devices: such as SSD or HDD, used to store persistent data.

[0058] I / O controller: manages the interfaces of input / output devices, such as USB, PCI-E, etc.

[0059] Power management unit: responsible for motherboard power supply management and energy-saving control.

[0060] These functional units work together to form the basic architecture of the motherboard. By optimizing the connection relationship and configuration between these functional units, the overall performance of the motherboard can be significantly improved.

[0061] refer to Figure 1 As shown, the optimization method includes the following steps:

[0062] S1: Determine the connection relationship between each functional unit and collect historical data of each functional unit, wherein the historical data includes historical operation data and historical performance data.

[0063] Specifically, step S1 includes the following steps:

[0064] S11: Identify the types of all functional units on the mainboard and their physical connection interfaces, and construct a logical connection diagram between the functional units based on the types and physical connection interfaces.

[0065] In the process of motherboard performance optimization, it is crucial to understand the connection relationship between each functional unit. The physical connection between functional units determines the data transmission path and efficiency between them, which in turn affects the overall performance of the motherboard. Therefore, identifying the types of all functional units on the motherboard and their physical connection interfaces, and constructing a logical connection diagram between functional units, is the basic work of performance optimization.

[0066] During implementation, motherboard diagnostic software is used to identify all functional units on the motherboard (such as CPU, memory, storage devices, I / O controllers, etc.), and PCI-E detectors are used to identify the physical connection interfaces of each functional unit (such as PCI-E slots, SATA ports, etc.).

[0067] Draw a logical connection diagram between functional units based on the identified information, and identify the data flow path and interface type between each unit.

[0068] S12: Collect and record the communication protocols and data exchange frequencies between the functional units, and use them as the connection relationships between the functional units.

[0069] In this embodiment, in addition to the physical connection, the communication protocol and data exchange frequency between the functional units are also important factors affecting the performance of the motherboard. Understanding this information can help optimize data transmission efficiency and reduce bottlenecks.

[0070] During implementation, the communication protocols used between the functional units (such as PCI-E, USB, SATA, etc.) are identified, and the data exchange frequency between the functional units under normal working conditions is monitored and recorded, and the identified communication protocols and data exchange frequency information are recorded as part of the connection relationship between the functional units.

[0071] S13: Collecting historical operation data and corresponding historical performance data of each functional unit during operation to form complete historical data.

[0072] In this embodiment, historical operation data and historical performance data are the basis for building the proxy model, and these data reflect the actual operation and performance of the motherboard under different configurations. Collecting these data can help more accurately simulate the performance of the motherboard under different configurations.

[0073] During implementation, the historical operating data of each functional unit during operation is collected through built-in sensors, including but not limited to temperature, power consumption, frequency, etc., and the historical performance data of the motherboard under different configurations is recorded, including but not limited to latency, throughput, system stability, etc. The collected data are integrated into a complete historical data set for use in subsequent agent model construction.

[0074] S2: Building an agent model for the motherboard based on the connection relationship, historical operation data, and historical performance data, wherein the agent model is used to simulate the performance of the motherboard under different configurations.

[0075] Specifically, step S2 includes the following steps:

[0076] S21: Preprocess the collected historical data.

[0077] Before building the proxy model, the collected historical data needs to be preprocessed. This is because the original data may contain noise, outliers, missing values ​​and other problems. If these problems are not resolved, they will directly affect the construction quality and prediction accuracy of the subsequent model.

[0078] During implementation, data cleaning is used to remove or correct erroneous data points. For example, if there is an abnormally high temperature reading, it is necessary to check whether it is caused by sensor failure or environmental interference, and make corresponding corrections.

[0079] Missing data points may be filled using methods including but not limited to interpolation (such as linear interpolation) and mean filling.

[0080] Since historical data may contain data of different dimensions, normalization or standardization is required to make all data at the same scale for subsequent analysis.

[0081] S22: Based on the connection relationship between each functional unit, define the input features of the proxy model, wherein the input features are designed to quantify and reflect the interaction effects generated by the connection relationship between each functional unit.

[0082] In this embodiment, in order to enable the proxy model to accurately simulate the performance of the motherboard under different configurations, it is necessary to design input features that can reflect the interaction effects between functional units. These input features not only include the state of a single functional unit, but also should take into account the interaction between functional units.

[0083] During implementation, features related to the functional unit are extracted from historical data, including but not limited to CPU load, memory occupancy, and I / O operation frequency.

[0084] According to the connection relationship between the functional units identified in step S1, a state feature reflecting the interaction effect between the functional units is designed. For example, when the CPU and the memory frequently exchange data, the usage rate of the memory bandwidth may increase.

[0085] By combining the state characteristics of a single functional unit and the connection relationship characteristics between functional units, a feature vector that can fully reflect the state of the motherboard is constructed.

[0086] S23: construct an initial proxy model based on a machine learning algorithm, train the proxy model and optimize the model according to historical operation data and historical performance data, and obtain a proxy model that simulates the performance of the motherboard under different configurations.

[0087] In this embodiment, the purpose of constructing the proxy model is to be able to predict the performance of the motherboard under different configurations through simulation. The proxy model relies on a machine learning algorithm to learn the mapping relationship between the motherboard performance and the configuration.

[0088] During implementation, a neural network is selected as the machine learning algorithm. The neural network has powerful nonlinear fitting capabilities, can handle complex input-output relationships, and has good generalization capabilities on large data sets.

[0089] According to the input features defined in step S22, key features that have a significant impact on the motherboard performance are selected, such as CPU load, memory usage, I / O operation frequency, etc.

[0090] Divide the historical data into training set, validation set and test set. Usually 70% of the data can be used as training set, 15% of the data as validation set, and 15% of the data as test set.

[0091] Design the structure of the neural network, including the input layer, hidden layer and output layer, where the input layer inputs the number of features, such as CPU load, memory usage, I / O operation frequency, etc.

[0092] Design one or more hidden layers, and the number of nodes in each layer can be adjusted according to actual conditions.

[0093] The output layer outputs motherboard performance metrics, such as latency, throughput, etc.

[0094] Activation function: Select the ReLU activation function.

[0095] Loss Function: Select the mean squared error loss function.

[0096] During training, the input features are normalized, the network weights and bias terms are randomly initialized, the training data is input, the output is calculated through forward propagation, the gradient of the loss function is calculated, and the network parameters are updated using the gradient descent optimization algorithm. The training is iterated multiple times until the model converges or reaches the predetermined training round.

[0097] When validating the model, the validation set data is used to evaluate the generalization ability of the model. The specific steps are as follows:

[0098] Input validation set data and output prediction performance.

[0099] Calculate the prediction error, such as mean squared error (MSE) or mean absolute error (MAE).

[0100] Adjust hyperparameters such as learning rate, number of hidden layers, number of hidden layer nodes, etc.

[0101] When optimizing the model, the hyperparameters are adjusted through grid search to optimize the model performance. The specific steps are as follows:

[0102] Define the hyperparameter space, search within the hyperparameter space, find the optimal hyperparameter combination, and retrain the model using the optimal hyperparameters.

[0103] When evaluating the model, use the test set data for the final evaluation to ensure that the model has good generalization ability. The specific steps are as follows:

[0104] Use the test set data to make predictions.

[0105] Calculate the final prediction error and evaluate the accuracy of the model.

[0106] S3: The first optimization target set is formed by random combination, and the proxy model is used in combination with the Bayesian optimization method to make an initial prediction of the motherboard performance to obtain an initial prediction result.

[0107] Specifically, step S3 includes the following steps:

[0108] S31: randomly selecting multiple optimization targets from a pre-built optimization target library and combining them to form a first optimization target set, wherein the optimization target library contains multiple optimization directions related to motherboard performance.

[0109] In the process of motherboard performance optimization, it is necessary to define optimization goals, which include but are not limited to improving throughput, reducing latency, reducing power consumption, improving system stability, maximizing available memory, minimizing CPU usage, and maximizing storage throughput. By building an optimization target library containing multiple optimization directions and randomly selecting multiple optimization target combinations to form the first optimization target set, different optimization strategies can be explored.

[0110] During the optimization process, a diversified optimization target set library is built based on the specific needs of the motherboard performance improvement. This library covers multiple key optimization directions and aims to comprehensively improve system performance, including but not limited to enhancing throughput to speed up data processing, reducing latency to improve response efficiency, and reducing power consumption to achieve energy conservation. More importantly, this optimization target set library has the characteristics of dynamic adjustment, which means that with the evolution of subsequent needs and the development of technology, new optimization targets can be flexibly added to it to ensure that the optimization strategy always remains forward-looking and practical.

[0111] A plurality of optimization targets are randomly selected from the optimization target library and combined to form a first optimization target set. The number of this optimization target set can vary according to the specific situation, and three, five or more targets can be selected, depending on the actual needs. At the same time, it is necessary to ensure that the selected optimization targets are logically complementary and meaningful to avoid conflicts between targets.

[0112] S32: Using the constructed proxy model, according to the current first optimization target set, the input parameters of the proxy model are set, wherein the input parameters are defined as indicators reflecting the performance requirements of the motherboard for each optimization target in the first optimization target set.

[0113] In order to enable the proxy model to make predictions based on the current first optimization target set, the first optimization target set needs to be converted into input parameters that the model can understand. These input parameters reflect the performance requirements of the motherboard under different configurations.

[0114] During implementation, the input parameters of the proxy model are defined according to the optimization objectives in the first optimization objective set, and the various optimization objectives in the first optimization objective set are converted into specific performance requirement indicators. For example, if the goal is to improve throughput, the input parameters of the model are adjusted accordingly. Finally, an input vector that can reflect the optimization objectives is constructed for use by the proxy model.

[0115] S33: Combined with the Bayesian optimization method, the proxy model is used to make a preliminary prediction of the motherboard's performance.

[0116] Specifically, step S33 includes the following steps:

[0117] S33a: Estimate the performance distribution of motherboards under different configurations using Gaussian process regression model in Bayesian optimization method.

[0118] In this embodiment, first, the Gaussian process regression model is initialized, specifically by selecting a kernel function to define the similarity between input data. In this application, a radial basis function is selected, and its form is:

[0119]

[0120] Among them, k(x i , x j ) represents the input data x i and input data x j The correlation between them, D represents the dimension of the input data, x id and x jd Represents the input data x i and input data x j The d-th eigenvalue of , exp(·) represents the exponential function, l d Denotes the length scale of the d-th eigenvalue.

[0121] Set initial hyperparameter values, such as the length scale l d and signal variance σ n

[0122] Then, the Gaussian process regression model is trained. Specifically, the historical operation data and historical performance data collected in step S2 are used to construct a training data set, and the Gaussian process regression model is fitted using the training data set to obtain model parameters.

[0123] Calculate the covariance matrix K of the training data set, where K = k(x i , x j ), and solve the model parameters by maximizing the log-likelihood function.

[0124] Finally, the performance distribution is estimated by taking the configuration data to be predicted as input and using the Gaussian process regression model to calculate the performance mean and variance of the configuration to be predicted.

[0125] S33b: Select the next most promising configuration by acquiring the function and use the proxy model to predict the performance of the motherboard under this configuration.

[0126] In this embodiment, the expected improvement is selected as the acquisition function, the acquisition function value is calculated for each configuration in the candidate configuration set, and the configuration with the largest acquisition function value is selected as the next most potential configuration.

[0127] The selected configuration data is input into the agent model, and the Gaussian process regression model is used to predict the motherboard performance under the configuration.

[0128] S33c: Iteratively update the Gaussian process regression model until the optimization termination condition is met, and output the current optimal initial prediction result.

[0129] In this embodiment, the newly selected configuration and its predicted performance are added to the training data set, and the Gaussian process regression model is refitted using the updated training data set.

[0130] Set optimization termination conditions, including but not limited to the maximum number of iterations and the predicted performance improvement threshold, and check whether the current number of iterations has reached the maximum number of iterations or whether the predicted performance improvement is lower than the threshold.

[0131] The current optimal configuration and its corresponding prediction performance are recorded. If the termination condition is met, the current optimal initial prediction result is output.

[0132] S34: When the optimization termination condition is met, the iteration is stopped and the current optimal initial prediction result is output, wherein the initial prediction result corresponds to the predicted optimal value of the motherboard performance under the first optimization target set and its corresponding configuration.

[0133] In this embodiment, when the Bayesian optimization process meets the termination condition, it is necessary to stop the iteration and output the current optimal initial prediction result. This is to ensure that the optimization process does not iterate excessively and retain the current optimal configuration.

[0134] During implementation, check again whether the optimization termination condition is met. If the termination condition is met, stop the iteration and output the current optimal initial prediction result, including the predicted optimal value and its corresponding configuration.

[0135] S4: Based on the initial prediction results, iterative optimization is performed within the Bayesian optimization framework, and a multi-objective optimization algorithm is used to identify non-dominated solutions during the iterative optimization process to form the Pareto front.

[0136] Specifically, step S4 includes the following steps:

[0137] S41: In a Bayesian optimization framework, new configurations are iteratively selected and evaluated based on initial prediction results.

[0138] In the Bayesian optimization framework, based on the initial prediction results obtained in step S3, the configuration needs to be further optimized to find a configuration closer to the optimal solution. By iteratively selecting and evaluating new configurations, the global optimal solution can be gradually approached.

[0139] During implementation, the optimal configuration obtained in step S3 is used as the initial configuration. Based on the current proxy model and the acquisition function, the next most promising configuration is selected. The acquisition function value is calculated for each configuration in the candidate configuration set. The configuration with the largest acquisition function value is selected as the next most promising configuration. The proxy model is used to predict the motherboard performance under the new configuration. The newly selected configuration and its predicted performance are added to the training data set, and the Gaussian process regression model is refitted. The above steps are repeated until the termination condition is met.

[0140] S42: Use the multi-objective optimization algorithm NSGA-II to identify non-dominated solutions in each iteration.

[0141] In multi-objective optimization problems, there is usually no single optimal solution, but rather a set of non-dominated solutions that form the Pareto front. NSGA-II (Non-dominated Sorting Genetic Algorithm II) is a commonly used multi-objective optimization algorithm for identifying non-dominated solutions.

[0142] During implementation, the new configurations evaluated in each iteration are non-dominated sorted. In the current configuration set, if there is no other configuration that makes all objectives better than the current configuration, then the current configuration is non-dominated. The congestion degree of the non-dominated solutions is calculated to distinguish the non-dominated solutions at the same level. The non-dominated solutions are selected according to the non-dominated level and congestion degree to form the Pareto front of the current iteration. The non-dominated solutions obtained in each iteration are added to the total Pareto front.

[0143] Through the NSGA-II algorithm, it is possible to find a balance between multiple optimization objectives and identify a set of non-dominated solutions; the formed Pareto front contains the optimal configuration between multiple optimization objectives, providing decision makers with more options.

[0144] S43: Iteratively update the proxy model until the termination condition is met, and output the current optimal Pareto front and its corresponding non-dominated solution, wherein each non-dominated solution in the Pareto front represents the optimal configuration of each functional unit under the current first optimization objective set.

[0145] In this embodiment, through continuous iterative optimization, it is necessary to determine when to stop the optimization process and output the current optimal Pareto front and its corresponding non-dominated solution. The termination condition is set to prevent over-optimization and ensure the generalization ability of the model.

[0146] During implementation, the agent model is iteratively updated until the termination condition is met. Similarly, the optimization termination conditions are set, such as the maximum number of iterations, the prediction performance improvement threshold, etc., and it is checked whether the current number of iterations has reached the maximum number of iterations, or whether the prediction performance improvement is lower than the threshold. When the termination condition is met, the current optimal Pareto front and its corresponding non-dominated solution are output, the non-dominated solution obtained in each iteration is recorded, and the current optimal Pareto front is output.

[0147] S5: Based on all the first optimization target sets of all the random combinations, target matching is performed on the input second optimization target set, and the optimal configuration corresponding to the matched first optimization target set is applied to each functional unit to achieve performance optimization of the mainboard.

[0148] Specifically, step S5 includes the following steps:

[0149] S51: Based on all randomly combined first optimization target sets, target quantity matching is performed on the standardized second optimization target set.

[0150] During the motherboard performance optimization process, users may propose new optimization target sets (second optimization target sets), which may differ from the first optimization target sets formed by random combination in terms of quantity and specific targets. In order to find the first optimization target set closest to the second optimization target set proposed by the user, the two need to be matched. During the matching process, the second optimization target set needs to be standardized first for comparison.

[0151] During implementation, each target in the second optimization target set is standardized to ensure that all targets are within the same dimensional range, which can be processed by the Z-score standardization method.

[0152] For each randomly combined first optimization goal set, find a second optimization goal set with the same number of goals. For each matching first optimization goal set, match its goals with the standardized second optimization goal set. For example, if the first optimization goal set includes "increase throughput" and "reduce latency", and the second optimization goal set includes "increase throughput" and "reduce power consumption", then the two goal sets can be considered to match in quantity.

[0153] S52: Calculate the Euclidean distance between the second optimization target set and the first optimization target set after each target quantity is matched.

[0154] After finding the first optimization target set that matches the number of targets of the second optimization target set, it is necessary to further calculate the similarity between the two. Euclidean distance is a commonly used metric that can measure the distance between two vectors, thereby reflecting the difference between the two sets of optimization targets.

[0155] During implementation, the objectives in each optimization objective set are converted into a vector form. For example, if the optimization objective set includes "increasing throughput" and "reducing latency", each objective can be regarded as a dimension and assigned a certain value (such as a standardized value).

[0156] Use the Euclidean distance formula to calculate the Euclidean distance between the first optimization target set and the second optimization target set after each target quantity is matched.

[0157] The calculation formula of Euclidean distance is:

[0158]

[0159] Among them, D(G 2 , G 1 ) is the second optimization target set G 2 and the first optimization target set G 1 The Euclidean distance between 2 =(g 21 , g 22 , …, g 2n ), G 2 =(g 11 , g 12 , …, g 1n ), g 2n and g 1n are the optimization targets in the second optimization target set and the first optimization target set respectively, and n is the number of targets

[0160] By calculating the Euclidean distance, the difference between two sets of optimization objectives can be quantified, which facilitates further screening of the best matching target set.

[0161] S53: Filter out the first optimization target set having the smallest Euclidean distance with the standardized second optimization target set.

[0162] After calculating the Euclidean distance between the second optimization target set and the first optimization target set after each target quantity is matched, it is necessary to select the first optimization target set with the smallest distance as the best matching target set.

[0163] During implementation, all calculated Euclidean distances are compared to find the smallest distance, and the first optimization target set having the smallest Euclidean distance to the second optimization target set is selected.

[0164] By screening out the target set with the smallest distance, it is possible to ensure that the first optimization target set that best matches the user's needs is found, thereby reducing unnecessary calculations and improving the efficiency of the optimization process.

[0165] S54: Apply the selected optimal configuration corresponding to the first optimization target set to each functional unit.

[0166] After completing the matching of the first optimization target set and the second optimization target set, and selecting the first optimization target set that best matches the second optimization target set, the next step is to apply the optimal configuration corresponding to the first optimization target set to the functional units of the motherboard. The purpose of this is to adjust the configuration of the motherboard according to the specific needs of the user to achieve the best performance.

[0167] During implementation, the optimal configurations are extracted from the non-dominated solutions (i.e., Pareto fronts) corresponding to the first set of optimization objectives. These configurations are identified by multi-objective optimization algorithms (such as NSGA-II) within the Bayesian optimization framework and represent the optimal configurations of each functional unit under the current set of optimization objectives.

[0168] Apply the optimal configuration to the functional units of the motherboard. The specific steps are as follows:

[0169] CPU configuration: Adjust the CPU's operating mode (such as frequency, number of cores, etc.) to achieve optimal performance.

[0170] Memory configuration: Adjust the memory operating mode (such as frequency, number of channels, etc.) to improve memory bandwidth utilization.

[0171] Storage device configuration: Optimize the read and write strategies of storage devices, such as adjusting cache strategies and optimizing file system parameters.

[0172] I / O controller configuration: Adjust the priority and scheduling policy of I / O devices to improve the efficiency of I / O operations.

[0173] Power management unit configuration: adjust the power management strategy, such as dynamically adjusting voltage and frequency, to achieve energy saving.

[0174] Embodiment 2

[0175] The present invention also provides a motherboard performance optimization system for executing a motherboard performance optimization method, wherein the motherboard includes a plurality of functional units, referring to Figure 2 As shown, the optimization system includes:

[0176] The data collection module 100 is used to determine the connection relationship between the functional units and collect the historical data of each functional unit, wherein the historical data includes historical operation data and historical performance data;

[0177] A model building module 200, for building an agent model for the motherboard based on the connection relationship, historical operation data and historical performance data, wherein the agent model is used to simulate the performance of the motherboard under different configurations;

[0178] The initial prediction module 300 is used to form a first optimization target set by random combination, use the proxy model, and combine the Bayesian optimization method to perform initial prediction of the motherboard performance to obtain an initial prediction result;

[0179] An iterative optimization module 400 is used to perform iterative optimization within a Bayesian optimization framework based on the initial prediction results, and to identify non-dominated solutions using a multi-objective optimization algorithm during the iterative optimization process to form a Pareto frontier;

[0180] The configuration application module 500 is used to target match the input second optimization target set based on all first optimization target sets of all random combinations, and apply the optimal configuration corresponding to the matched first optimization target set to each functional unit to achieve performance optimization of the mainboard.

[0181] The present application is described with reference to flowcharts and / or block diagrams of methods, devices (systems) and computer program products according to embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0182] Those skilled in the art can understand that all or part of the steps in the various methods of the above embodiments can be completed by instructing related hardware through a program, and the program can be stored in a computer-readable storage medium, and the storage medium includes a read-only memory (ROM), a random access memory (RAM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), a one-time programmable read-only memory (OTPROM), an electronically erasable rewritable read-only memory (EEPROM), a compact disc (CD-ROM) or other optical disc storage, magnetic disk storage, magnetic tape storage, or any other computer-readable medium that can be used to carry or store data.

[0183] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.

Claims

1. A method for optimizing motherboard performance, wherein the motherboard comprises a plurality of functional units, characterized in that: The optimization method comprises the following steps: Determine the connection relationship between each functional unit, and collect historical data of each functional unit, wherein the historical data includes historical operation data and historical performance data; Building an agent model for the motherboard based on the connection relationship, historical operation data, and historical performance data, wherein the agent model is used to simulate the performance of the motherboard under different configurations; A first optimization target set is formed by random combination, and the proxy model is used in combination with a Bayesian optimization method to perform an initial prediction of the motherboard performance to obtain an initial prediction result; Based on the initial prediction results, performing iterative optimization within a Bayesian optimization framework, and identifying non-dominated solutions using a multi-objective optimization algorithm during the iterative optimization process to form a Pareto front; Based on all the first optimization target sets of all the random combinations, the input second optimization target set is targeted and matched, and the optimal configuration corresponding to the matched first optimization target set is applied to each functional unit to achieve performance optimization of the mainboard.

2. A method for optimizing motherboard performance according to claim 1, characterized in that: Determining the connection relationship between the functional units and collecting historical data of each functional unit includes: Identify the types of all functional units on the mainboard and their physical connection interfaces, and construct a logical connection diagram between the functional units based on the types and physical connection interfaces; Collect and record the communication protocols and data exchange frequencies between the functional units, and use them as the connection relationship between the functional units; Collect historical operation data and corresponding historical performance data of each functional unit during operation to form complete historical data.

3. A method for optimizing motherboard performance according to claim 2, characterized in that: The constructing of an agent model for the mainboard based on the connection relationship, historical operation data and historical performance data includes: Preprocessing the collected historical data; According to the connection relationship between each functional unit, the input feature of the proxy model is defined, wherein the input feature is designed to quantify and reflect the interaction effect generated by the connection relationship between each functional unit; An initial proxy model is built based on a machine learning algorithm, and the proxy model is trained and optimized based on historical operation data and historical performance data to obtain a proxy model that simulates the performance of the motherboard under different configurations.

4. A method for optimizing motherboard performance according to claim 3, characterized in that: The first optimization target set is formed by random combination, and the proxy model is used in combination with the Bayesian optimization method to perform an initial prediction of the motherboard performance to obtain an initial prediction result, including: Randomly selecting multiple optimization targets from a pre-built optimization target library and combining them to form a first optimization target set, wherein the optimization target library includes multiple optimization directions related to motherboard performance; Using the constructed proxy model, according to the current first optimization target set, the input parameters of the proxy model are set, wherein the input parameters are defined as indicators reflecting the performance requirements of each optimization target in the first optimization target set on the motherboard; Combined with Bayesian optimization method, the proxy model is used to make a preliminary prediction of the motherboard's performance; When the optimization termination condition is met, the iteration is stopped and the current optimal initial prediction result is output, wherein the initial prediction result corresponds to the predicted optimal value of the motherboard performance under the first optimization target set and its corresponding configuration.

5. A method for optimizing motherboard performance according to claim 4, characterized in that: The Bayesian optimization method is combined with the agent model to make a preliminary prediction of the performance of the motherboard, including: The Gaussian process regression model in the Bayesian optimization method is used to estimate the performance distribution of the motherboard under different configurations; The next most promising configuration is selected by obtaining the function, and the proxy model is used to predict the performance of the motherboard under this configuration; The Gaussian process regression model is iteratively updated until the optimization termination condition is met, and the current optimal initial prediction result is output.

6. A method for optimizing motherboard performance according to claim 5, characterized in that: Based on the initial prediction results, performing iterative optimization within a Bayesian optimization framework, and using a multi-objective optimization algorithm to identify non-dominated solutions during the iterative optimization process to form a Pareto frontier, including: Iteratively selecting and evaluating new configurations based on the initial prediction results within a Bayesian optimization framework; The multi-objective optimization algorithm NSGA-II is used to identify the non-dominated solutions in each iteration; The proxy model is iteratively updated until the termination condition is met, and the current optimal Pareto front and its corresponding non-dominated solution are output, wherein each non-dominated solution in the Pareto front represents the optimal configuration of each functional unit under the current first optimization objective set.

7. A method for optimizing motherboard performance according to claim 6, characterized in that: The step of performing target matching on the input second optimization target set based on all first optimization target sets of all random combinations, and applying the optimal configuration corresponding to the matched first optimization target set to each functional unit, includes: Based on all the randomly combined first optimization target sets, matching the target quantity of the standardized second optimization target set; Calculating the Euclidean distance between the second optimization target set and the first optimization target set after each target quantity is matched; Filter out the first optimization target set with the smallest Euclidean distance to the standardized second optimization target set; The optimal configuration corresponding to the screened first optimization target set is applied to each functional unit.

8. A method for optimizing motherboard performance according to claim 7, characterized in that: The calculation formula of the Euclidean distance is: Where D(G2, G1) is the Euclidean distance between the second optimization target set G2 and the first optimization target set G1, G2 = (g 21 , g 22 , …, g 2n ), G2=(g 11 , g 12 , …, g 1n ), g 2n and g 1n are the optimization targets in the second optimization target set and the first optimization target set respectively, and n is the number of targets.

9. A motherboard performance optimization system, used to execute a motherboard performance optimization method as claimed in any one of claims 1 to 8, wherein the motherboard comprises a plurality of functional units, characterized in that: The optimization system comprises: A data collection module, used to determine the connection relationship between the functional units and collect historical data of each functional unit, wherein the historical data includes historical operation data and historical performance data; A model building module, used to build an agent model for the mainboard based on the connection relationship, historical operation data and historical performance data, wherein the agent model is used to simulate the performance of the mainboard under different configurations; An initial prediction module, used to form a first optimization target set by random combination, use the proxy model, and combine the Bayesian optimization method to make an initial prediction of the motherboard performance to obtain an initial prediction result; An iterative optimization module, used for performing iterative optimization within a Bayesian optimization framework based on the initial prediction results, and identifying non-dominated solutions using a multi-objective optimization algorithm during the iterative optimization process to form a Pareto frontier; The configuration application module is used to match the input second optimization target set based on all the first optimization target sets of all random combinations, and apply the optimal configuration corresponding to the matched first optimization target set to each functional unit to achieve performance optimization of the mainboard.

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