Analog domain low-order multi-bit fusion quantization method

Abstract

The invention discloses an analog domain low-order multi-bit fusion quantization method, which is used for supporting in-memory computing macro-cell and accelerator design of an analog domain and a digital / analog mixed domain, and belongs to the technical field of special integrated circuit design. According to the method, an analog domain low-bit multi-bit fusion quantization method is provided, so that the problem of power consumption waste caused by quantization of a low-bit weight calculation result is solved. Compared with a traditional bit-by-bit quantization method, according to the characteristic that different bit weight calculation results have different contributions to the performance of the neural network, the quantization method adopts conventional bit-by-bit quantization on a high-bit weight calculation result, and adopts a method of performing simulation domain fusion and one-time quantization on a plurality of low-bit weight calculation results on a low-bit weight calculation result. On the premise of ensuring the performance of the neural network, the quantization frequency is reduced, the power consumption of the quantization part is reduced, and the energy efficiency of the calculation unit is further improved.

Description

Technical Field

[0001] The present invention relates to the technical field of application-specific integrated circuit design, and in particular to an analog domain low-order multi-bit fusion quantization method. Background Art

[0002] In highly parallel neural network applications, computing in memory (CIM) has been proven to have significant energy efficiency advantages and acceleration effects. CIM performs multiplication and accumulation (MAC) operations directly in the storage array, effectively reducing the large amount of energy consumption caused by frequent data transmission between the processor and the storage, thereby overcoming the "storage wall" problem under the von Neumann architecture. In neural networks, a large amount of input data and weights exist in the form of high-precision floating-point numbers. In order to effectively deploy neural networks on CIM circuits, these floating-point data need to be quantized. At present, the commonly used quantization method is to convert floating-point numbers into integer data (such as INT8, INT4, etc.). This type of integer / fixed-point quantization method can basically meet the requirements of neural network reasoning, and the error caused by quantization is usually negligible. However, integer quantization methods show different characteristics at the software level and hardware level. At the software level, the calculation results of different bit weights have different effects on the neural network, and the results of low bit weights contribute less to the performance; at the hardware level, the readout of the results of different bit weights consumes the same circuit energy. Therefore, merging the low bit weight results into the high bit weight results for quantized readout can save energy without affecting the performance of the neural network. In addition, the sparsity of the neural network allows truncating the full-scale readout results to further reduce circuit area and energy consumption, while having limited impact on the performance of the neural network. Summary of the invention

[0003] The present invention provides an analog domain low-bit multi-bit fusion quantization method to alleviate the problem of power consumption waste caused by quantization of low-bit weight calculation results.

[0004] An embodiment of the present invention provides an analog domain low-order multi-bit fusion quantization method, which is used to perform a quantization readout after fusing multiple low-order weight calculation results in the analog domain. The method comprises the following steps:

[0005] Cluster the data involved in the calculation;

[0006] The low bits are fused using a specific combination of quantized readouts;

[0007] According to the budget of quantization readout, a certain number of bits of high-order weights are discarded from the selected fusion quantization combination.

[0008] Optionally, in one embodiment of the present invention, when clustering the data involved in the calculation, s data are selected from the data that need to participate in the calculation, where s is an integer power of 2.

[0009] Optionally, in one embodiment of the present invention, when using a specific quantization readout combination to fuse low bits, the principles for selecting the low-bit fusion quantization combination include: from the perspective of the hardware readout circuit, the difference in the full-scale logarithm of different bit weight fusion combinations is less than or equal to 1; from the perspective of software performance, the number of bits of the low-bit weight fusion combination is greater than or equal to the number of bits of the high-bit weight fusion combination.

[0010] Optionally, in one embodiment of the present invention, the implementation of analog domain low-bit fusion includes charge domain weighted sharing and current domain / time domain weighted superposition.

[0011] Optionally, in one embodiment of the present invention, the full-scale result is rounded off starting from the high bit according to specific network requirements and the area of ​​the readout circuit.

[0012] The analog domain low-order multi-bit fusion quantization method of the embodiment of the present invention is used to alleviate the problem of power consumption waste caused by the quantization of low-order weight calculation results. Compared with the traditional bit-by-bit quantization method, the quantization method adopts conventional bit-by-bit quantization for the calculation results of high-order weights, and adopts the method of fusing the calculation results of multiple low-order weights in the analog domain for one quantization for the calculation results of low-order weights. Under the premise of ensuring the performance of the neural network, the number of quantization times is reduced, the power consumption of the quantization part is reduced, and the energy efficiency of the computing unit is improved.

[0013] Additional aspects and advantages of the present invention will be given in part in the following description and in part will be obvious from the following description, or will be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The above and / or additional aspects and advantages of the present invention will become apparent and easily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which:

[0015] Figure 1 A schematic diagram of an analog domain low-order multi-bit fusion quantization method provided according to an embodiment of the present invention. DETAILED DESCRIPTION

[0016] Embodiments of the present invention are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present invention, and should not be construed as limiting the present invention.

[0017] like Figure 1 As shown, the analog domain low-order multi-bit fusion quantization method is used to support the design of in-memory computing macro units and accelerators in the analog domain and digital / analog hybrid domain; a method is proposed to quantize and read out multiple low-order weight calculation results after fusing them in the analog domain.

[0018] like Figure 1 As shown, multiplication will produce results of different bits of O0, O1, O2, ... The analog domain low-order multi-bit fusion quantization method includes the following steps:

[0019] Cluster the data involved in the calculation;

[0020] The low bits are fused using a specific combination of quantized readouts;

[0021] According to the budget of quantization readout, a certain number of bits of high-order weights are discarded from the selected fusion quantization combination.

[0022] In this embodiment, when clustering the data involved in the calculation, s data are selected from the data that need to participate in the calculation, where s is an integer power of 2, and s can be an integer power of 2 such as 32, 64, etc.

[0023] In this embodiment, the principles for selecting low-order fusion quantization combinations include: from the perspective of the hardware readout circuit, the difference in the full-scale logarithm of different bit-weight fusion combinations should be less than or equal to 1; from the perspective of software performance, the number of bits of the low-order weight fusion combination should be greater than or equal to the number of bits of the high-order weight fusion combination; different selection methods correspond to different software and hardware overheads.

[0024] In this embodiment, the implementation method of low-bit fusion in the analog domain includes weighted sharing in the charge domain and weighted superposition in the current domain / time domain.

[0025] In this embodiment, the selection of the full-scale result starting from the high bit should depend on the specific network requirements and the area of ​​the readout circuit, and the discarding of 0, 1, 2, and 3 bits may be appropriately considered.

[0026] The analog domain low-order multi-bit fusion quantization method proposed in an embodiment of the present invention is used to support the design of in-memory computing macro units and accelerators in the analog domain and the digital / analog hybrid domain, and the method takes into account both software and hardware overhead.

[0027] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or N embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, without contradiction.

[0028] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In the description of the present invention, the meaning of "N" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

Claims

1. An analog domain low-bit multi-bit fusion quantization method, characterized in that: The method is used to perform a quantization readout after fusing multiple low-order weight calculation results in the analog domain, and the method comprises the following steps: Cluster the data involved in the calculation; The low bits are fused using a specific combination of quantized readouts; According to the budget of quantization readout, a certain number of bits of high-order weights are discarded from the selected fusion quantization combination.

2. The analog domain low-order multi-bit fusion quantization method according to claim 1, characterized in that: When clustering the data involved in the calculation, s data are selected from the data that need to participate in the calculation, where s is an integer power of 2.

3. The analog domain low-order multi-bit fusion quantization method according to claim 1, characterized in that: In using a specific quantization readout combination to fuse the low bits, the principles for selecting the low-bit fusion quantization combination include: from the perspective of the hardware readout circuit, the difference in the full-scale logarithm of different bit weight fusion combinations is less than or equal to 1; from the perspective of software performance, the number of bits of the low-bit weight fusion combination is greater than or equal to the number of bits of the high-bit weight fusion combination.

4. The analog domain low-order multi-bit fusion quantization method according to claim 3, characterized in that: The implementation methods of low-bit fusion in the analog domain include charge domain weighted sharing and current domain / time domain weighted superposition.

5. The analog domain low-order multi-bit fusion quantization method according to claim 1, characterized in that: The full-scale result is rounded off starting from the high bit according to the specific network requirements and the area of ​​the readout circuit.

Images