Chip packaging method and chip packaging structure

Abstract

The invention provides a chip packaging method and a chip packaging structure, and relates to the technical field of semiconductors. According to the method, after the first plastic package layer is manufactured, the first plastic package structure is cut, so that the thermal stress of the first plastic package layer caused by inconsistent thermal expansion coefficients is reduced, and the risk of cracking of the carrier plate in the subsequent process is reduced. Next, the cut plastic package units are transferred to a second carrier plate, secondary plastic package processing is carried out on the cut plastic package units, a second plastic package layer is formed, and due to the fact that the first plastic package layer and the second plastic package layer are the same in material, the thermal stress difference between the first plastic package layer and the second plastic package layer is small; the risk of fracture of the support plate caused by thermal stress difference is further reduced, the production efficiency of the subsequent process is improved, the support plate can be recycled, and the production cost is reduced.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a chip packaging method and a chip packaging structure. Background Art

[0002] In semiconductor technology, packaging is an important part of the production and processing of semiconductor integrated circuit chips. It can not only place, fix, seal and protect the chip, but also enhance the electrical and thermal performance, and also realize the transmission of data and signals between the internal and external circuits of the chip. However, the existing chip packaging process still has the problem of low production efficiency. Summary of the invention

[0003] In order to at least overcome the above-mentioned deficiencies in the prior art, the purpose of the present application is to provide a chip packaging method and a chip packaging structure.

[0004] In a first aspect, an embodiment of the present application provides a chip packaging method, the chip packaging method comprising:

[0005] A first carrier board is provided, and a stacked wiring layer, a chip layer and a first plastic packaging layer are sequentially manufactured on one side of the first carrier board to obtain a first plastic packaging structure, wherein the chip layer includes a plurality of chips;

[0006] Removing the first carrier board and cutting the first plastic packaging structure to obtain a plastic packaging unit including at least one chip;

[0007] Providing a second carrier, transferring the plurality of the plastic encapsulation units onto the second carrier, and manufacturing a second plastic encapsulation layer covering the plastic encapsulation units to obtain a second plastic encapsulation structure, wherein the material of the first plastic encapsulation layer is the same as the material of the second plastic encapsulation layer;

[0008] The second plastic packaging structure is ground to reduce the thickness of the second plastic packaging structure.

[0009] In a possible implementation, the step of providing a first carrier board, and sequentially manufacturing a stacked routing layer, a chip layer, and a first plastic packaging layer on one side of the first carrier board to obtain a first plastic packaging structure includes:

[0010] Providing a first carrier board, and forming a first adhesive layer on one side of the first carrier board;

[0011] Making a wiring layer on a side of the first adhesive layer away from the first carrier board;

[0012] Manufacturing a chip layer including a plurality of chips on a side of the wiring layer away from the first carrier board;

[0013] A first plastic packaging material is used to make a first plastic packaging layer on the peripheral sides of the wiring layer and the chip layer, and on a side of the chip layer away from the first carrier board, to obtain a first plastic packaging structure.

[0014] In a possible implementation, the step of providing a second carrier, transferring the plurality of plastic encapsulation units onto the second carrier, and manufacturing a second plastic encapsulation layer covering the plastic encapsulation units to obtain a second plastic encapsulation structure includes:

[0015] Providing a second carrier board, and forming a second adhesive layer on one side of the second carrier board;

[0016] Transferring the plurality of plastic encapsulation units to a side of the second adhesive layer away from the second carrier board;

[0017] A second plastic encapsulation material is used to make a second plastic encapsulation layer covering the plastic encapsulation unit to obtain a second plastic encapsulation structure, wherein the first plastic encapsulation material is the same as the second plastic encapsulation material.

[0018] In a possible implementation, the step of using a first plastic encapsulation material to form a first plastic encapsulation layer on the peripheral sides of the routing layer and the chip layer, and on a side of the chip layer away from the first carrier board to obtain a first plastic encapsulation structure includes:

[0019] The first carrier board with the chip layer manufactured thereon is placed in a plastic encapsulation mold, the first plastic encapsulation material is pressed into the plastic encapsulation mold, a first plastic encapsulation layer is formed on the peripheral sides of the routing layer and the chip layer, and on the side of the chip layer away from the first carrier board, to obtain a first plastic encapsulation structure.

[0020] In a possible implementation, the step of using a second plastic encapsulation material to make a second plastic encapsulation layer covering the plastic encapsulation unit to obtain a second plastic encapsulation structure includes:

[0021] The second carrier plate after transferring the molding unit is placed in the molding mold, the second molding material is pressed into the molding mold, and a second molding layer is formed on the peripheral side of the molding unit and the side away from the second carrier plate to obtain a second molding structure.

[0022] In a possible implementation manner, the step of manufacturing a chip layer including a plurality of chips on a side of the wiring layer away from the first carrier board includes:

[0023] A plurality of chips are placed on a side of the wiring layer away from the first carrier board, wherein electrode pins of the plurality of chips face the wiring layer and are electrically connected to the wiring layer;

[0024] A bottom filling glue layer is formed between the chip and the wiring layer to fill the two, so as to obtain the chip layer.

[0025] In a possible implementation manner, after the step of grinding the second plastic package structure to reduce the thickness of the second plastic package structure, the method further includes:

[0026] removing the second carrier board, and bonding the ground second plastic package structure to a third carrier board, wherein the ground side of the second plastic package structure is in contact with the third carrier board;

[0027] Fabricating an interconnection structure on a side of the routing layer away from the chip layer to obtain conductive balls or conductive pillars electrically connected to the routing layer;

[0028] The third carrier board is removed, and the second plastic packaging structure with the conductive balls manufactured thereon is cut to obtain a chip packaging structure including at least a single chip.

[0029] In a possible implementation, the step of manufacturing an interconnection structure on a side of the wiring layer away from the chip layer to obtain a conductive ball electrically connected to the wiring layer includes:

[0030] Cleaning the wiring layer to remove dirt and / or oxides on the surface of the wiring layer;

[0031] Performing metal deposition on the wiring layer to form a plurality of conductive bumps or conductive pits on the wiring layer;

[0032] Transferring the prefabricated conductive balls to the conductive bumps and / or conductive pits to electrically connect the conductive balls to the wiring layer; or,

[0033] The conductive bumps are tinned to form conductive pillars electrically connected to the wiring layer.

[0034] In a second aspect, an embodiment of the present application further provides a chip packaging structure, wherein the chip packaging structure includes a plastic packaging unit, and the plastic packaging unit includes:

[0035] Routing layer;

[0036] A chip layer, the chip layer is located on the wiring layer, the chip layer includes at least one chip, and the chip is electrically connected to the wiring layer;

[0037] A first plastic sealing layer surrounding the chip layer;

[0038] The chip packaging structure further includes a second packaging layer, which surrounds the first plastic packaging layer, wherein the first plastic packaging layer and the second packaging layer are made of the same material.

[0039] In a possible implementation, the chip packaging structure further includes a conductive ball, the conductive ball is located on a side of the routing layer away from the chip layer, and the conductive ball is connected to a routing in the routing layer.

[0040] Based on any of the above aspects, the chip packaging method and chip packaging structure provided in the embodiment of the present application, after making the first plastic sealing layer, cut the first plastic sealing structure to reduce the thermal stress generated by the inconsistent thermal expansion coefficient of the first plastic sealing layer, and reduce the risk of carrier board rupture in the subsequent process. Then, the cut plastic sealing unit is transferred to the second carrier, and a second plastic sealing treatment is performed on it to form the second plastic sealing layer. Since the material of the first plastic sealing layer and the material of the second plastic sealing layer are the same, the thermal stress difference between the first plastic sealing layer and the second plastic sealing layer is small, which further reduces the risk of carrier board rupture caused by the thermal stress difference, improves the production efficiency of the subsequent process, and can also recycle the carrier board to reduce production costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without creative work.

[0042] Figure 1 A schematic diagram of a process flow of a chip packaging method provided in an embodiment of the present application;

[0043] Figure 2 for Figure 1 The corresponding process diagram;

[0044] Figure 3 for Figure 1 Schematic diagram of the sub-step flow of step S110;

[0045] Figure 4 Another schematic diagram of a chip packaging method provided in an embodiment of the present application;

[0046] Figure 5 for Figure 4 The corresponding process diagram;

[0047] Figure 6 A schematic diagram of the chip packaging structure provided in the embodiment of the present application Figure 1 ;

[0048] Figure 7 A schematic diagram of the chip packaging structure provided in the embodiment of the present application Figure 2 . DETAILED DESCRIPTION

[0049] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various different configurations.

[0050] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for which protection is sought, but merely represents selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.

[0051] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.

[0052] In the description of this application, it should be noted that the terms "upper", "lower", etc. indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship in which the product of the application is usually placed when in use, which is only for the convenience of describing this application and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on this application. In addition, the terms "first", "second", etc. are only used to distinguish the description, and cannot be understood as indicating or implying relative importance.

[0053] In the description of this application, it should also be noted that, unless otherwise clearly specified and limited, the terms "disposed", "connected", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal connection of two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0054] It should be noted that, in the absence of conflict, different features in the embodiments of the present application may be combined with each other.

[0055] The inventors discovered that in the relevant chip packaging process, the thermal expansion coefficients (CTE) between the packaging layer material and the chip 121, the wiring layer 110 and the carrier are inconsistent, resulting in a large thermal stress difference. This thermal stress difference may cause the carrier to crack during the grinding of the plastic packaging layer, thereby affecting subsequent processes and reducing production efficiency.

[0056] In order to solve the problems in the prior art, the present application provides a chip packaging method. Figure 1 and Figure 2 , Figure 1 FIG. 1 is a flow chart of a chip packaging method. Figure 2 for Figure 1 The corresponding process diagram. Figure 1 and Figure 2 Each step of the chip packaging method is described in detail.

[0057] Step S110: providing a first carrier board, and sequentially manufacturing a stacked wiring layer, a chip layer and a first plastic packaging layer on one side of the first carrier board to obtain a first plastic packaging structure.

[0058] In this step, the first carrier 210 may be, but not limited to, a glass carrier, a resin carrier, etc. The chip layer 120 may include a plurality of chips 121 electrically connected to the wiring layer 110. For example, the chip 121 may include a system-on-chip 121 (SoC chip 121) and a high-bandwidth memory chip 121 (HBM) and other chips 121.

[0059] Step S120: removing the first carrier board and cutting the first plastic package structure to obtain a plastic package unit including at least one chip.

[0060] In this step, the first plastic encapsulation structure 101 is cut to release some of the thermal stress caused by the inconsistency of the thermal expansion coefficients of the first plastic encapsulation layer 130, the chip 121, the wiring layer 110, and the first carrier 210, thereby reducing the risk of carrier cracking in subsequent processes. Specifically, the first plastic encapsulation structure 101 can be cut by laser cutting or precision cutting to obtain a plastic encapsulation unit 1011 with smooth edges.

[0061] Step S130: providing a second carrier, transferring a plurality of plastic encapsulation units onto the second carrier, and manufacturing a second plastic encapsulation layer covering the plastic encapsulation units to obtain a second plastic encapsulation structure.

[0062] In this step, the first carrier plate 210 may be, but not limited to, a glass carrier plate, a resin carrier plate, etc., wherein the second carrier plate 220 may be the same carrier plate as or different carrier plates from the first carrier plate 210. In order to reduce the difference in thermal stress between the first plastic encapsulation layer 130 and the second plastic encapsulation layer 140, the material of the first plastic encapsulation layer 130 is the same as the material of the second plastic encapsulation layer 140.

[0063] Step S140: grinding the second plastic package structure to reduce the thickness of the second plastic package structure.

[0064] In this step, the second plastic package structure 102 can be ground according to the actual needs of the product until the surface of the second plastic package structure 102 is flat and meets the preset size range. Exemplarily, the second plastic package structure 102 can be ground until the side of the chip 121 opposite to the electrode pin is exposed to improve the heat dissipation performance of the chip 121.

[0065] In this embodiment, after the first plastic encapsulation layer 130 is manufactured, the first plastic encapsulation structure 101 is cut, which can reduce the thermal stress generated by the first plastic encapsulation layer 130 due to the inconsistency of the thermal expansion coefficient, and reduce the risk of carrier board rupture in the subsequent process. Then, the cut plastic encapsulation unit 1011 is transferred to the second carrier board 220, and a second plastic encapsulation process is performed on it to form the second plastic encapsulation layer 140. Since the material of the first plastic encapsulation layer 130 and the material of the second plastic encapsulation layer 140 are the same, the thermal stress difference between the first plastic encapsulation layer 130 and the second plastic encapsulation layer 140 is small, which further reduces the risk of carrier board rupture caused by the thermal stress difference, improves the production efficiency of the subsequent process, and can also recycle the carrier board to reduce production costs.

[0066] For further information, please refer to Figure 3 , step S110 can be implemented by the following method.

[0067] Step S111: providing a first carrier board, and forming a first adhesive layer on one side of the first carrier board.

[0068] In this step, the first adhesive layer can be made of thermal peeling and / or laser peeling material, wherein the first adhesive layer can be removed by heating and / or laser treatment. Preferably, the first carrier 210 is a glass carrier, and the first adhesive layer is made of laser peeling material.

[0069] Step S112: manufacturing a wiring layer on a side of the first adhesive layer away from the first carrier board.

[0070] Step S113: manufacturing a chip layer including a plurality of chips on a side of the wiring layer away from the first carrier board.

[0071] In this step, the chip 121 can be placed on the side of the wiring layer 110 away from the first carrier 210, wherein the electrode pins of the chip 121 can face the wiring layer 110, and can be electrically connected to the wiring layer 110 by welding. Then, a bottom filling glue layer filled between the chip 121 and the wiring layer 110 is formed to obtain the chip layer 120. Specifically, a suitable bottom filling material can be selected according to the material properties (such as thermal expansion coefficient) of the chip 121 and the wiring layer 110, and the bottom filling material can be applied between the chip 121 and the wiring layer 110, and finally filled between the gap between the chip 121 and the wiring layer 110 by heating, and the bottom filling glue layer is formed after the bottom filling material is cooled and solidified. The bottom filling glue layer can improve the mechanical connection strength between the chip 121 and the wiring layer 110 and protect the chip 121 from physical loss.

[0072] Step S114: using a first plastic encapsulation material to form a first plastic encapsulation layer on the peripheral sides of the wiring layer and the chip layer, and on a side of the chip layer away from the first carrier board, to obtain a first plastic encapsulation structure.

[0073] In this step, the first carrier board 210 with the chip layer 120 manufactured thereon can be placed in a plastic encapsulation mold, and the first plastic encapsulation material can be pressed into the plastic encapsulation mold by injection molding to form a first plastic encapsulation layer 130 on the surrounding sides of the routing layer 110 and the chip layer 120, as well as on the side of the chip layer 120 away from the first carrier board 210, thereby obtaining a first plastic encapsulation structure 101.

[0074] Furthermore, in step S130, a second carrier 220 may be provided first, and a second adhesive layer may be made on one side of the second carrier 220, and then a plurality of plastic encapsulation units 1011 may be transferred to a side of the second adhesive layer away from the second carrier 220. The second adhesive layer may be made of a thermal peeling and / or laser peeling material, and the second adhesive layer may be removed by heating and / or laser treatment. Then, a second plastic encapsulation material may be used to make a second plastic encapsulation layer 140 covering the plastic encapsulation unit 1011, and a second plastic encapsulation structure 102 may be obtained. Specifically, the second carrier 220 after the plastic encapsulation unit 1011 is transferred may be placed in a plastic encapsulation mold, and the second plastic encapsulation material may be pressed into the plastic encapsulation mold, and a second plastic encapsulation layer 140 may be formed on the peripheral side of the plastic encapsulation unit 1011 and on a side away from the second carrier 220, and a second plastic encapsulation structure 102 may be obtained, wherein the first plastic encapsulation material is the same as the second plastic encapsulation material, and the first plastic encapsulation material and the second plastic encapsulation material may be liquid and / or solid plastic encapsulation materials.

[0075] In this embodiment, the first plastic encapsulation layer 130 and the second plastic encapsulation layer 140 can protect the chip 121 from external water vapor invasion and external stress impact, thereby extending the service life of the chip 121. The first plastic encapsulation material is the same as the second plastic encapsulation material, which can reduce the thermal stress difference between the first plastic encapsulation layer 130 and the second plastic encapsulation layer 140, thereby reducing the risk of damage to the carrier board caused by the thermal stress difference in subsequent processes.

[0076] After step S140, please refer to Figure 4 and Figure 5 The chip packaging method provided in the embodiment of the present application may further include the following steps.

[0077] Step S150: removing the second carrier board, and bonding the ground second plastic package structure to the third carrier board.

[0078] In this step, the ground second plastic encapsulation structure 102 can be separated from the second carrier 220 by first removing the second adhesive layer, and then a third adhesive layer is made on one side of the third carrier 230 to achieve bonding between the second plastic encapsulation structure 102 and the third carrier 230 through the third adhesive layer, wherein the ground side of the second plastic encapsulation structure 102 is in contact with the third carrier 230.

[0079] Step S160: fabricating an interconnection structure on a side of the wiring layer away from the chip layer to obtain conductive balls or conductive pillars electrically connected to the wiring layer.

[0080] In this step, the routing layer 110 may be cleaned first to remove dirt and / or oxide layer on the routing layer 110 surface, and metal deposition may be performed on the routing layer 110 to form a plurality of conductive bumps or conductive pits on the routing layer 110. Next, the conductive bumps may be tinned to form conductive pillars 150 electrically connected to the routing layer 110, or prefabricated conductive balls 150 may be transferred to the conductive bumps and / or conductive pits to electrically connect the conductive balls 150 to the routing layer 110. The conductive balls 150 may play a role in adhesion and diffusion when the chip 121 packaging structure is welded to other electronic devices.

[0081] Step S170: removing the third carrier board, and cutting the second plastic package structure with the conductive balls formed thereon to obtain a chip package structure including at least a single chip.

[0082] In this step, the third carrier 230 and the second plastic package structure 102 with the conductive balls 150 made thereon can be separated by removing the third adhesive layer, and the second plastic package structure 102 can be cut by laser cutting or wire cutting to obtain a chip packaging structure including at least a single chip 121.

[0083] Based on the same invention concept, please refer to Figure 6The present application also provides a chip packaging structure 10, which includes a plastic packaging unit 1011 and a second packaging layer 140. The plastic packaging unit 1011 includes a wiring layer 110, a chip layer 120 and a first plastic packaging layer 130. The chip layer 120 is located on the wiring layer 110. The chip layer 120 includes at least one chip 121. The side of the chip 121 provided with pins is arranged toward the wiring layer 110 and is electrically connected to the wiring layer 110. The first plastic packaging layer 130 surrounds the peripheral side of the chip layer 120. The second packaging layer 140 surrounds the peripheral side of the first plastic packaging layer 130, wherein the first plastic packaging layer 130 and the second packaging layer 140 are made of the same material.

[0084] In this step, during the process of making the first plastic encapsulation layer 130 and the second encapsulation layer, after making the first plastic encapsulation layer 130, the first plastic encapsulation structure 101 is cut, which can reduce the thermal stress generated by the first plastic encapsulation layer 130 due to the inconsistent thermal expansion coefficient, and reduce the risk of carrier board rupture in the subsequent process. Then the second plastic encapsulation layer 140 is formed. Since the material of the first plastic encapsulation layer 130 and the material of the second plastic encapsulation layer 140 are the same, the difference in thermal stress between the first plastic encapsulation layer 130 and the second plastic encapsulation layer 140 is small, which further reduces the risk of carrier board rupture caused by the difference in thermal stress, improves the production efficiency of the subsequent process, and can also recycle the carrier board to reduce production costs.

[0085] For further information, please refer to Figure 7 The chip package structure 10 further includes a conductive ball 150 or a conductive pillar 150, which is located on a side of the wiring layer 110 away from the chip layer 120, and the conductive ball 150 or the conductive pillar 150 is connected to the wiring in the wiring layer 110. Exemplarily, the chip package structure 10 may include the conductive ball 150, which may play a role of adhesion and diffusion when the chip package structure is welded with other electronic devices.

[0086] In summary, the embodiment of the present application provides a chip packaging method and a chip packaging structure. After the first plastic encapsulation layer is manufactured, the first plastic encapsulation structure is cut, which can reduce the thermal stress generated by the first plastic encapsulation layer due to the inconsistent thermal expansion coefficient, and reduce the risk of carrier board breakage in the subsequent process. Then, the cut plastic encapsulation unit is transferred to the second carrier, and a second plastic encapsulation process is performed on it to form a second plastic encapsulation layer. Since the material of the first plastic encapsulation layer is the same as the material of the second plastic encapsulation layer, the difference in thermal stress between the first plastic encapsulation layer and the second plastic encapsulation layer is small, which further reduces the risk of carrier board breakage caused by the difference in thermal stress, improves the production efficiency of the subsequent process, and can also recycle the carrier board to reduce production costs.

[0087] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A chip packaging method, characterized in that: The method comprises: A first carrier board is provided, and a stacked wiring layer, a chip layer and a first plastic packaging layer are sequentially manufactured on one side of the first carrier board to obtain a first plastic packaging structure, wherein the chip layer includes a plurality of chips; Removing the first carrier board and cutting the first plastic packaging structure to obtain a plastic packaging unit including at least one chip; Providing a second carrier, transferring the plurality of the plastic encapsulation units onto the second carrier, and manufacturing a second plastic encapsulation layer covering the plastic encapsulation units to obtain a second plastic encapsulation structure, wherein the material of the first plastic encapsulation layer is the same as the material of the second plastic encapsulation layer; The second plastic packaging structure is ground to reduce the thickness of the second plastic packaging structure.

2. The chip packaging method according to claim 1, characterized in that: The step of providing a first carrier board, and sequentially manufacturing a stacked wiring layer, a chip layer, and a first plastic packaging layer on one side of the first carrier board to obtain a first plastic packaging structure includes: Providing a first carrier board, and forming a first adhesive layer on one side of the first carrier board; Making a wiring layer on a side of the first adhesive layer away from the first carrier board; Manufacturing a chip layer including a plurality of chips on a side of the wiring layer away from the first carrier board; A first plastic packaging material is used to make a first plastic packaging layer on the peripheral sides of the wiring layer and the chip layer, and on a side of the chip layer away from the first carrier board, to obtain a first plastic packaging structure.

3. The chip packaging method according to claim 2, characterized in that: The step of providing a second carrier, transferring the plurality of plastic encapsulation units onto the second carrier, and making a second plastic encapsulation layer covering the plastic encapsulation units to obtain a second plastic encapsulation structure includes: Providing a second carrier board, and forming a second adhesive layer on one side of the second carrier board; Transferring the plurality of plastic encapsulation units to a side of the second adhesive layer away from the second carrier board; A second plastic encapsulation material is used to make a second plastic encapsulation layer covering the plastic encapsulation unit to obtain a second plastic encapsulation structure, wherein the first plastic encapsulation material is the same as the second plastic encapsulation material.

4. The chip packaging method according to claim 3, characterized in that: The step of using a first plastic encapsulation material to form a first plastic encapsulation layer on the peripheral sides of the routing layer and the chip layer, and on a side of the chip layer away from the first carrier board to obtain a first plastic encapsulation structure includes: The first carrier board with the chip layer manufactured thereon is placed in a plastic encapsulation mold, the first plastic encapsulation material is pressed into the plastic encapsulation mold, a first plastic encapsulation layer is formed on the peripheral sides of the routing layer and the chip layer, and on the side of the chip layer away from the first carrier board, to obtain a first plastic encapsulation structure.

5. The chip packaging method according to claim 4, characterized in that: The step of using a second plastic encapsulation material to make a second plastic encapsulation layer covering the plastic encapsulation unit to obtain a second plastic encapsulation structure comprises: The second carrier plate after transferring the molding unit is placed in the molding mold, the second molding material is pressed into the molding mold, and a second molding layer is formed on the peripheral side of the molding unit and the side away from the second carrier plate to obtain a second molding structure.

6. The chip packaging method according to claim 2, characterized in that: The step of manufacturing a chip layer including a plurality of chips on a side of the wiring layer away from the first carrier board comprises: A plurality of chips are placed on a side of the wiring layer away from the first carrier board, wherein electrode pins of the plurality of chips face the wiring layer and are electrically connected to the wiring layer; A bottom filling glue layer is formed between the chip and the wiring layer to fill the two, so as to obtain the chip layer.

7. The chip packaging method according to claim 1, characterized in that: After the step of grinding the second plastic package structure to reduce the thickness of the second plastic package structure, the method further includes: removing the second carrier board, and bonding the ground second plastic package structure to a third carrier board, wherein the ground side of the second plastic package structure is in contact with the third carrier board; An interconnection structure is fabricated on a side of the routing layer away from the chip layer to obtain a conductive ball or conductive column electrically connected to the routing layer; The third carrier board is removed, and the second plastic packaging structure with the conductive balls manufactured thereon is cut to obtain a chip packaging structure including at least a single chip.

8. The chip packaging method according to claim 7, characterized in that: The step of manufacturing an interconnection structure on a side of the wiring layer away from the chip layer to obtain a conductive ball or a conductive column electrically connected to the wiring layer includes: Cleaning the wiring layer to remove dirt and / or an oxide layer on the surface of the wiring layer; Performing metal deposition on the wiring layer to form a plurality of conductive bumps or conductive pits on the wiring layer; Transferring the prefabricated conductive balls to the conductive bumps and / or conductive pits to electrically connect the conductive balls to the wiring layer; or, The conductive bumps are tinned to form conductive pillars electrically connected to the wiring layer.

9. A chip packaging structure, characterized in that: The chip packaging structure includes a plastic packaging unit, and the plastic packaging unit includes: Routing layer; A chip layer, the chip layer is located on the wiring layer, the chip layer includes at least one chip, and the chip is electrically connected to the wiring layer; A first plastic sealing layer surrounding the chip layer; The chip packaging structure further includes a second packaging layer, which surrounds the first plastic packaging layer, wherein the first plastic packaging layer and the second packaging layer are made of the same material.

10. The chip packaging structure according to claim 9, characterized in that: The chip packaging structure further includes a conductive ball or a conductive column, wherein the conductive ball or the conductive column is located on a side of the routing layer away from the chip layer, and the conductive ball or the conductive column is connected to a routing in the routing layer.

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