Semiconductor manufacturing apparatus and method for manufacturing semiconductor device

Abstract

The invention provides a semiconductor manufacturing apparatus and a semiconductor device manufacturing method capable of suppressing defects of a semiconductor wafer in a dicing process. A semiconductor manufacturing apparatus according to an embodiment cuts a semiconductor wafer into a plurality of semiconductor chips. The storage unit stores position information of a plurality of first lines to be cut on a first surface of the semiconductor wafer, and position information of a second line to be not cut among the plurality of first lines. The cutting section cuts the semiconductor wafer at a plurality of first lines other than the second lines.

Description

[0001] This application claims the priority of Japanese Patent Application No. 2023-146383 (filing date: September 8, 2023) as a basic application. The present application incorporates the entire contents of the basic application by reference. Technical Field

[0002] The present embodiment relates to a semiconductor manufacturing apparatus and a method for manufacturing a semiconductor device. Background Art

[0003] Sometimes, voids are generated at the bonding interface of a bonded wafer formed by bonding multiple semiconductor wafers. In such a case, during the dicing process of the bonded wafer, the semiconductor wafer may be defective at the position of the void. The defective semiconductor wafer may contaminate the dicing device and make it difficult to handle the bonded wafer and semiconductor chip in the subsequent process. Summary of the invention

[0004] An object of the present invention is to provide a semiconductor manufacturing apparatus and a method for manufacturing a semiconductor device that can suppress the chipping of a semiconductor wafer in a dicing process.

[0005] Technical solutions to solve problems

[0006] The semiconductor manufacturing apparatus according to the present embodiment cuts a semiconductor wafer into a plurality of semiconductor chips. The storage unit stores position information of a plurality of first lines on the first surface of the semiconductor wafer that are scheduled to be cut and position information of second lines among the plurality of first lines that are scheduled not to be cut. The cutting unit cuts the semiconductor wafer at the plurality of first lines except the second lines. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 This is a block diagram showing a configuration example of a cutting device according to the first embodiment.

[0008] Figure 2 This is a cross-sectional view showing an example of a defect of a semiconductor wafer.

[0009] Figure 3 This is a flowchart showing an example of a cutting method using the cutting device according to the first embodiment.

[0010] Figure 4 This is a conceptual plan view of a semiconductor wafer showing an example of a dicing method.

[0011] Figure 5 It is the successor Figure 4 A plan view showing an example of a cutting method.

[0012] Figure 6 It is the successor Figure 5A plan view showing an example of a cutting method.

[0013] Figure 7 It is the successor Figure 6 A plan view showing an example of a cutting method.

[0014] Figure 8 is a table showing position information of the cutout area.

[0015] Fig. 9 is a table showing position information of the cutout area.

[0016] Fig.10 It is a plan view showing a semiconductor chip that has not been singulated.

[0017] Fig.11 This is a table showing an example of position information of dicing lines surrounding semiconductor chips that have not been singulated.

[0018] Fig.12 This is a table showing an example of position information of dicing lines surrounding semiconductor chips that have not been singulated. DETAILED DESCRIPTION

[0019] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. The embodiments do not limit the present invention. The accompanying drawings are schematic or conceptual. In the specification and the accompanying drawings, the same elements are marked with the same symbols.

[0020] (First embodiment)

[0021] Figure 1 1 is a block diagram showing a configuration example of a dicing device according to a first embodiment. The dicing device 1 is a semiconductor manufacturing device for dicing a semiconductor wafer into a plurality of semiconductor chips. The semiconductor wafer may be composed of, for example, a single semiconductor substrate or a plurality of semiconductor chips. Figure 2 As shown, the semiconductor wafer is composed of a bonded wafer formed by bonding a plurality of semiconductor substrates S1 and S2. On the surface of the semiconductor wafer, semiconductor elements have been formed in the previous process of the semiconductor manufacturing process. After the previous process, the semiconductor wafer undergoes surface inspection and electrical characteristic inspection, etc., and is singulated into semiconductor chips in the dicing device 1.

[0022] The cutting device 1 includes a receiving unit 10 , a computing unit 20 , a control unit 30 , a cutting unit 40 , a transmitting unit 50 , a GUI (Graphical User Interface) 60 , and a storage unit 70 .

[0023] The receiving unit 10 receives the inspection result obtained in the surface inspection from the outside. The inspection result is received from the inspection device not shown. The inspection result is, for example, the position information of the defect on the surface of the semiconductor wafer. Figure 2As shown, the defect of the semiconductor wafer is, for example, a gap BD generated on the bonding surface FB of the bonded wafer, etc. The position information may be a plane coordinate with the center of the semiconductor wafer as the origin.

[0024] When the gap BD is cut in the dicing process, it may cause a defect in the semiconductor chip and may cause contamination in the subsequent back grinding process, etc. Therefore, the dicing device 1 according to the present embodiment is set not to cut the gap BD based on the position information of the defect, etc.

[0025] The operation unit 20 sets a skip line that is not cut in the cutting line of the semiconductor wafer based on the product information of the semiconductor wafer and the position information of the defect. The cutting line is an example of a first line that is scheduled to be cut on the surface of the semiconductor wafer. The cutting line is located between a plurality of adjacent semiconductor chips. On the other hand, a skip line is a cutting line that is scheduled not to be cut in the cutting process, for example, a line portion of the cutting line that is set to be not cut due to defects such as a gap BD. The skip line is an example of a second line. The operation unit 20 sets whether to set as a skip line or not to set as a skip line according to the line segment of the cutting line corresponding to the sides of a plurality of adjacent semiconductor chips. That is, the skip line is partially set according to the side of the semiconductor chip. The operation unit 20 can be, for example, a CPU (Central Processing Unit) or the like. In addition, the setting of the skip line will be described in detail later.

[0026] The control unit 30 controls the cutting unit 40. At this time, the control unit 30 controls the cutting unit 40 in such a manner that the cutting lines that are not set as skip lines are cut and the cutting lines set as skip lines are not cut. The control unit 30 may be, for example, a CPU, a PLC (Programable Logic Controller), or the like.

[0027] The cutting unit 40 is controlled by the control unit 30 to cut the semiconductor wafer. The cutting unit 40 cuts the cutting lines except the skipped lines. The cutting unit 40 includes, for example, a cutting blade that cuts the semiconductor wafer with a rotating blade or a laser generator that cuts the semiconductor wafer with a laser. Although not shown in the figure, the cutting unit 40 also includes a workbench on which the semiconductor wafer is placed, a conveying mechanism that conveys the semiconductor wafer to and from the workbench, and the like.

[0028] The transmission unit 50 transmits the position information of the semiconductor chip adjacent to the skip line to the outside. The reception unit 10 and the transmission unit 50 may be configured as one input-output circuit.

[0029] The GUI 60 displays inspection information of the semiconductor wafer, product information of the semiconductor wafer, cutting lines, cutting areas, and skipped lines on the surface of the semiconductor wafer, etc. In addition, the GUI 60 is configured to allow the user to input information. For example, the user selects a product to be cut in the GUI 60. The GUI 60 transmits the selected product information to the operation unit 20. The operation unit 20 extracts the product information selected by the user from the plurality of product information stored in the storage unit 70. The GUI 60 displays the product information of the semiconductor wafer to be cut. The GUI 60 may be, for example, a touch panel display, a keyboard, etc.

[0030] The storage unit 70 stores in advance product information of semiconductor wafers related to various products and inspection results of each semiconductor wafer received by the receiving unit 10. The product information of the semiconductor wafer is information determined by the product formed on the semiconductor wafer, and includes, for example, size information of the semiconductor chip, position information of a unique pattern set on the semiconductor chip, interval information between adjacent cutting lines, length information of the cutting line, etc. The unique pattern may be, for example, an alignment mark set on each semiconductor chip. The storage unit 70 stores in advance product information of a plurality of products. When the user selects a product using the GUI 60, the operation unit 20 receives the product information corresponding to the product from the storage unit 70.

[0031] In addition, the storage unit 70 stores the inspection information of the semiconductor wafer received by the receiving unit 10 during the dicing process. The inspection information is information specific to each semiconductor wafer and is stored in the storage unit 70 for each semiconductor wafer. In addition, the position information of the defect can be expressed by the position coordinates with the center of the surface of the semiconductor wafer as the origin.

[0032] The storage unit 70 also stores the position information of the skipped line set based on the position information of the defect in the cutting line. Thus, the cutting unit 40 can cut the cutting line except the line portion of the cutting line set as the skipped line in the cutting line.

[0033] Furthermore, the storage unit 70 stores the area to be removed when the cutting line is cut by the cutting unit 40 as the cutting area. The cutting area is an area on the surface of the semiconductor wafer with a width centered on the cutting line to be removed by cutting. In other words, the cutting area is an area other than the semiconductor chip cut from the semiconductor wafer. The storage unit 70 can be, for example, a memory or storage such as an SSD (Solid State Drive) or an HDD (Hard Disc Drive).

[0034] Figure 22 is a cross-sectional view showing an example of a defect of a semiconductor wafer. The semiconductor wafer W is, for example, a bonded wafer formed by bonding a plurality of semiconductor substrates S1 and S2 on a bonding surface FB. In such a semiconductor wafer W, a gap BD sometimes remains as a defect on the bonding surface FB. As described above, if the gap BD is cut, it will cause a defect in the semiconductor chip. Therefore, when a cutting line includes a defect such as a gap BD, the calculation unit 20 sets the line portion of the cutting line as a skip line and does not cut the defect.

[0035] Figure 3 This is a flowchart showing an example of a cutting method using the cutting device according to the first embodiment. Figure 4 to Figure 7 1 is a conceptual plan view of a semiconductor wafer showing an example of a dicing method. In addition, the storage unit 70 stores in advance product information of semiconductor wafers related to various products.

[0036] First, the receiving unit 10 receives the inspection result of the semiconductor wafer W from an external inspection device (not shown) (S10). The inspection result includes the position information of the defect (for example, the gap BD) on the surface of the semiconductor wafer W. The inspection result is stored in the storage unit 70. In addition, the user uses the GUI 60 to input or select the product information of the semiconductor wafer W to be cut (S11). The product information of the semiconductor wafer W to be cut is stored in the storage unit 70. Then, the cutting device 1 carries the semiconductor wafer W to be cut into the chamber of the cutting unit 40, and places the semiconductor wafer W on a workbench (not shown) (S12).

[0037] Then, if Figure 4 As shown, the operation unit 20 detects the unique patterns (for example, alignment marks) UP1 to UP3 of multiple semiconductor chips in the semiconductor wafer W based on the product information (S20). The control unit 30 uses the position information of the unique patterns UP1 to UP3 to perform the position alignment of the semiconductor wafer W (S30). The position alignment of the semiconductor wafer W is performed with respect to the X direction, the Y direction intersecting the X direction, and the rotation direction in the XY plane. At this time, in order to suppress the deviation in the rotation direction when observing from the plane on the surface of the semiconductor wafer W, the position information of the unique patterns of more than two semiconductor chips is used. For example, Figure 4 As shown, the position alignment of the semiconductor wafer W can also be performed using three unique patterns UP1 to UP3.

[0038] Then, if Figure 5As shown, the calculation unit 20 sets the cutting lines DLa~DLg, ​​DL1~DL5 on the surface of the semiconductor wafer W based on the spacing information between the cutting lines and the length information of the cutting lines (S40). The spacing information between the cutting lines, for example, represents the spacing between the plurality of cutting lines DLa~DLg adjacent in the X direction and the spacing between the plurality of cutting lines DL1~DL5 adjacent in the Y direction. In the same semiconductor wafer W, the spacing between the cutting lines DLa~DLg in the X direction can be equal, and be equidistant. In addition, in the same semiconductor wafer W, the spacing between the cutting lines DL1~DL5 in the Y direction can be equal, and be equidistant.

[0039] The length information of the cutting lines DLa to DLg, DL1 to DL5 can be set individually for each of the plurality of cutting lines DLa to DLg, DL1 to DL5. Figure 5 As shown, the lengths of the plurality of dicing lines DLa to DLg and DL1 to DL5 may be equal. In this case, the lengths of the dicing lines DLa to DLg and DL1 to DL5 are longer than the diameter of the semiconductor wafer W so that the dicing unit 40 can cut the semiconductor wafer W to the end thereof.

[0040] For example, Figure 5 As shown, the calculation unit 20 sets a plurality of cutting lines DL1 to DL5 extending in the X direction and a plurality of cutting lines DLa to DLg extending in the Y direction. The cutting lines DL1 to DL5 and the cutting lines DLa to DLg are, for example, substantially orthogonal to each other. The number of the cutting lines DL1 to DL5 and the number of the cutting lines DLa to DLg is not particularly limited, but depends on the chip size of the semiconductor chip.

[0041] The position information of the cutting lines DLa to DLg, DL1 to DL5 can be set using the coordinates of one end and the coordinates of the other end. The position information of the cutting lines DLa to DLg, DL1 to DL5 is stored in the storage unit 70. In addition, the coordinates of the intersections of the cutting lines DLa to DLg, DL1 to DL5 are also stored in the storage unit 70. Thus, the calculation unit 20 can determine a portion of the intersections of the cutting lines DLa to DLg, DL1 to DL5.

[0042] Then, if Figure 6 and Figure 7As shown, the calculation unit 20 sets the cutting areas DRa~DRg, DR1~DR5 on the surface of the semiconductor wafer W based on the position information of the cutting lines DLa~DLg, ​​DL1~DL5, the interval information between the cutting lines DLa~DLg, ​​DL1~DL5, the length information of the cutting lines DLa~DLg, ​​DL1~DL5, and the size information of the semiconductor chip CH (S50). The cutting areas DRa~DRg, DR1~DR5 are areas that are scheduled to be removed when the cutting unit 40 cuts the cutting lines DLa~DLg, ​​DL1~DL5. Therefore, the area of ​​the semiconductor wafer W other than the cutting areas DRa~DRg, DR1~DR5 becomes the area of ​​the semiconductor chip CH. The size information of the semiconductor chip CH is the size of the semiconductor chip CH cut from the semiconductor wafer W in the XY plane.

[0043] Here, for example, Figure 7 As shown, the width of the semiconductor chip CH in the X direction is cX, and the width of the semiconductor chip CH in the Y direction is cY. The intervals between adjacent dicing lines (second scheduled cutting lines) DLa to DLg in the X direction are pX, and the intervals between adjacent dicing lines (first scheduled cutting lines) DL1 to DL5 in the Y direction are pY.

[0044] At this time, the calculation unit 20 sets the area having a width of ±(pY-cY) / 2 in the Y direction from each of the cutting lines DL1 to DL5 as the cutting areas DR1 to DR5. In addition, the calculation unit 20 sets the area having a width of ±(pX-cX) / 2 in the X direction from each of the cutting lines DLa to DLg as the cutting areas DRa to DRg.

[0045] Figure 8 is a table showing the position information of the cutting areas DR1 to DR5. Figure 8 The X column of the table shows the length of the cutting areas DR1 to DR5 in the X direction (for example, -150 mm to 150 mm). Figure 8 The Y column of the table shows the width of the cutting areas DR1 to DR5 in the Y direction. Y_DL1 to Y_DL5 represent the Y coordinates of the cutting lines DL1 to DL5, respectively. Therefore, it can be seen that the cutting areas DR1 to DR5 are areas on the surface of the semiconductor wafer W with a width of ±(pY-cY) / 2 in the Y direction with the cutting lines DL1 to DL5 as the center, respectively. In addition, the length of the cutting areas DR1 to DR5 in the X direction (for example, -150 mm to 150 mm) can be the same as the length of the cutting lines DL1 to DL5 in the X direction, respectively, and can be equal to or larger than the diameter of the semiconductor wafer W.

[0046] Fig. 9 is a table showing the position information of the cutting areas DRa to DRg. Fig. 9 The Y column of the table shows the length of the cutting areas DRa to DRg in the Y direction (-150 mm to 150 mm). Fig. 9 The X column of the table shows the width of the dicing areas DRa to DRg in the X direction. X_DLa to X_DLg represent the X coordinates of the dicing lines DLa to DLg, respectively. Therefore, it can be seen that the dicing areas DRa to DRg are areas on the surface of the semiconductor wafer W with a width of ±(pX-cX) / 2 in the X direction with the dicing lines DLa to DLg as the center, respectively. In addition, the length of the dicing areas DRa to DRg in the Y direction (for example, -150 mm to 150 mm) can be the same as the length of the dicing lines DLa to DLg in the X direction, and can be equal to or larger than the diameter of the semiconductor wafer W.

[0047] The calculation unit 20 stores the position information of the cutout regions DR1 to DR5 and DRa to DRg set as described above in the storage unit 70 .

[0048] Next, the calculation unit 20 sets the skip line based on the position information of the defect and the position information of the dicing area (S60). The position information of the defect indicates the coordinates of the defect within the surface of the semiconductor wafer W. For example, Figure 7 As shown in FIG. 1 , it is assumed that defects BD1 and BD2 exist. Defect BD1 exists in dicing region DR2. Therefore, the operation unit 20 sets a skip line SL in dicing line DL2 corresponding to dicing region DR2. More specifically, the operation unit 20 sets a line segment between adjacent semiconductor chips CHsk1 and CHsk2 as a skip line SL1 in dicing region DR2 where defect BD1 exists. The skip line SL1 corresponds to the sides of adjacent semiconductor chips CHsk1 and CHsk2. Figure 7 The dotted line indicates .

[0049] In addition, the defect BD2 is located in the overlapping area of ​​the cutting area DR4 and the cutting area DRd. In this case, the operation unit 20 sets the skip line SL in the cutting lines DL4 and DLd corresponding to the cutting areas DR4 and DRd. The overlapping area where the defect BD2 exists corresponds to the corners of the semiconductor chips CHsk3 to CHsk6. Therefore, the operation unit 20 sets the line segment SL2 between the adjacent semiconductor chips CHsk3 and CHsk4, the line segment SL3 between the semiconductor chips CHsk3 and CHsk5, the line segment SL4 between the semiconductor chips CHsk5 and CHsk6, and the line segment SL5 between the semiconductor chips CHsk6 and the semiconductor chips CHsk4 as skip lines in the overlapping area where the defect BD2 exists. The skip line SL2 corresponds to one side between the semiconductor chips CHsk3 and CHsk4. The skip line SL3 corresponds to one side between the semiconductor chips CHsk3 and CHsk5. The skip line SL4 corresponds to one side between the semiconductor chips CHsk5 and CHsk6. The skip line SL5 corresponds to one side between the semiconductor chips CHsk6 and CHsk5. Skip lines SL2 to SL5 to Figure 7 The dotted line indicates .

[0050] As described above, in this embodiment, the operation unit 20 sets the portions within the cutting lines DL2, DL4, DLd corresponding to the cutting areas DR2, DR4, DRd where defects BD1, BD2 exist as skip lines SL1 to SL5 according to the line segments corresponding to the edges of the adjacent plurality of semiconductor chips CHsk1 to CHsk5.

[0051] The position information of the skip lines SL1 to SL5 is stored in the storage unit 70. The position information of the skip lines SL1 to SL5 can be the position coordinates of the cutting lines corresponding to them (the coordinates of the intersections at both ends). For example, the position information of the skip line SL1 can be represented by the coordinates of the intersections of the cutting lines DL2 and DLd and the coordinates of the intersections of the cutting lines DL2 and DLe. The position information of the skip line SL2 can be represented by the coordinates of the intersections of the cutting lines DL3 and DLd and the coordinates of the intersections of the cutting lines DL4 and DLd. The position information of the skip line SL3 can be represented by the coordinates of the intersections of the cutting lines DL4 and DLc and the coordinates of the intersections of the cutting lines DL4 and DLd. The position information of the skip line SL4 can be represented by the coordinates of the intersections of the cutting lines DL4 and DLd and the coordinates of the intersections of the cutting lines DL5 and DLd. The position information of the skip line SL5 can be represented by the coordinates of the intersections of the cutting lines DL4 and DLd and the coordinates of the intersections of the cutting lines DL4 and DLe.

[0052] Next, the control unit 30 controls the cutting unit 40 so as to skip the skipped lines SL1 to SL5 among the cutting lines DL1 to DL5 and DLa to DLg and cut the other cutting lines. The cutting unit 40 cuts the cutting lines other than the skipped lines SL1 to SL5 (S70) and cuts the singulated semiconductor chips CH from the semiconductor wafer W. Here, since the skipped lines SL1 to SL5 are not cut, the adjacent semiconductor chips CHsk1 and CHsk2 remain connected, and the semiconductor chips CHsk3 to CHsk6 also remain connected. The semiconductor chips CHsk1, CHsk2, and CHsk3 to CHsk6 are not singulated and become defective chips.

[0053] Next, the transmission unit 50 transmits the position information of the semiconductor chips CHsk1 and CHsk2 and the semiconductor chips CHsk3 to CHsk6 that have not been singulated to the outside ( S80 ). Fig.10 The plan view shows the semiconductor chips CHsk1 to CHsk6 that have not been singulated. The position information of the semiconductor chips CHsk1, CHsk2, and the semiconductor chips CHsk3 to CHsk6 that have not been singulated is the position information of the cutting lines surrounding the semiconductor chips CHsk1 and CHsk2 adjacent to the skipping line SL1 and the position information of the cutting lines surrounding the semiconductor chips CHsk3 to CHsk6 adjacent to the skipping lines SL2 to SL5.

[0054] For example, Fig.11 This is a table showing an example of position information of cutting lines surrounding the semiconductor chips CHsk1 and CHsk2 that have not been singulated. The storage unit 70 stores the position information of the cutting lines DL1 to DL5, DLa to DLg and the coordinates of their intersections. Thus, the position information of the cutting lines surrounding the semiconductor chips CHsk1 and CHsk2 can be the coordinates of the corners of the cutting lines surrounding the semiconductor chips CHsk1 and CHsk2. For example, the semiconductor chips CHsk1 and CHsk2 are represented by the intersection coordinates 1d of the cutting lines DL1 and DLd, the intersection coordinates 1e of the cutting lines DL1 and DLe, the intersection coordinates 3d of the cutting lines DL3 and DLd, and the intersection coordinates 3e of the cutting lines DL3 and DLe.

[0055] In addition, for example, Fig.12This is a table showing an example of position information of the cutting lines surrounding the semiconductor chips CHsk3 to CHsk6 that are not singulated. The position information of the cutting lines surrounding the semiconductor chips CHsk3 to CHsk6 may be the coordinates of the corners of the cutting lines surrounding the semiconductor chips CHsk3 to CHsk6. For example, the semiconductor chips CHsk3 to CHsk6 are represented by the coordinates 3c of the intersection of the cutting lines DL3 and DLc, the coordinates 3e of the intersection of the cutting lines DL3 and DLe, the coordinates 5c of the intersection of the cutting lines DL5 and DLc, and the coordinates 5e of the intersection of the cutting lines DL5 and DLe.

[0056] The sending unit 50 sends Fig.11 and Fig.12 The intersection coordinates shown can be output to the outside. Fig.10 The semiconductor chips CHsk1 to CHsk6 are located on the outermost side of the semiconductor wafer W. In addition, the information outputted to the outside by the sending unit 50 may not be the position information corresponding to the plurality of semiconductor chips CH, but the position information corresponding to one semiconductor chip CH. For example, when the skip line is set to be a line segment of a cutting line corresponding to the edge on the outer peripheral side of the semiconductor wafer W of the semiconductor chip CH arranged at the outermost periphery of the semiconductor wafer W rather than between the plurality of adjacent semiconductor chips CH, the semiconductor chip CH adjacent to the skip line on the center side of the semiconductor wafer W is not singulated and becomes a defective chip. Therefore, the position information of the cutting line surrounding the one semiconductor chip CH is outputted to the outside as the position information of the semiconductor chip CH that has not been singulated. That is, the sending unit 50 sends the position information of one or more semiconductor chips CH adjacent to the skip line to the outside as the position information of the semiconductor chip CH that has not been singulated.

[0057] According to the present embodiment, the operation unit 20 automatically sets the cutting areas DR1 to DR5, DRa to DRg based on the position information of the cutting lines DL1 to DL5, DLa to DLg, the size information cX and cY of the semiconductor chip CH, and the spacing information pX and pY of the cutting lines DL1 to DL5, DLa to DLg. In addition, the operation unit 20 sets the line segment between the semiconductor chips CHsk1 and CHsk2 adjacent to the defect BD1 in the cutting line DL2 corresponding to the cutting area DR2 with the defect BD1 as the skip line SL1. In addition, the operation unit 20 automatically sets the line segment between the semiconductor chips CHsk3 to CHsk6 adjacent to the defect BD2 in the cutting lines DL4 and DLd corresponding to the cutting areas DR4 and DRd with the defect BD2 as the skip lines SL2 to SL5. Thus, the cutting unit 40 can cut other line portions in the cutting lines DL1 to DL5, DLa to DLg without cutting the skip lines SL1 and SL2 to SL5 where the defects BD1 and BD2 exist. As a result, it is possible to suppress the semiconductor wafer W from being damaged during the dicing process.

[0058] In addition, the skip line is set as a line segment of the dicing line corresponding to the side of the adjacent semiconductor chip CH. Thereby, the number of semiconductor chips CHsk1 to CHsk6 that are not used as products can be reduced.

[0059] (Second embodiment)

[0060] Reference Figure 6 and Figure 7 , the second embodiment is described.

[0061] In the second embodiment, the GUI 60 is as follows Figure 7 As shown in FIG. 1 , defects BD1 and BD2, dicing lines DL1 to DL5, DLa to DLg, and dicing regions DR1 to DR5, DRa to DRg in the semiconductor wafer W are displayed. Figure 7 As shown in FIG. 1 , a part of the semiconductor wafer W having defects BD1 and BD2 is enlarged and displayed, or as shown in FIG. Figure 6 The entire semiconductor wafer W is shown as shown.

[0062] The user refers to GUI60 and selects skip lines based on the positions of defects BD1 and BD2 and cutting areas DR1 to DR5, DRa to DRg. For example, among the cutting lines DL1 to DL5, DLa to DLg, the user selects and sets skip lines SL1 and SL2 to SL5 according to the line segments corresponding to the sides of the adjacent semiconductor chips CHsk1 to CHsk6 in the cutting lines DL2, DL4, and DLd corresponding to the cutting areas DR2, DR4, and DRd where defects BD1 and BD2 exist. In this way, the user can arbitrarily select skip lines while referring to defects BD1, BD2 and cutting areas DR1 to DR5, DRa to DRg through GUI60. Therefore, for example, the user can also exclude the line segments (skipping lines SL2 and SL5) in the cutting lines DL4 and DLd corresponding to the two sides of the semiconductor chip CHsk4 that is relatively far from the defect BD2 from the skip lines. In addition, the user can use the input function of GUI60 (for example, input using a touch panel or input using a keyboard) to perform the selection or release of the skip line.

[0063] The other configurations and operations of the second embodiment may be the same as those of the first embodiment. Thus, the second embodiment cannot automatically set a skip line, but can suppress the defect of the semiconductor wafer W in the dicing process similarly to the first embodiment.

[0064] Several embodiments of the present invention have been described, but these embodiments are provided as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other ways, and various omissions, substitutions, and changes can be made without departing from the scope of the invention. These embodiments and their variations are included in the scope and purpose of the invention, and are also included in the invention described in the claims and their equivalents.

[0065] Description of Reference Numerals

[0066] 1 cutting device; 10 receiving unit; 20 computing unit; 30 control unit; 40 cutting unit; 50 sending unit; 60 GUI; 70 storage unit; DLa~DLg, ​​DL1~DL5 cutting lines; DRa~DRg, DR1~DR5 cutting areas; SL1~SL5 skip lines

Claims

1. A semiconductor manufacturing device that cuts a semiconductor wafer into a plurality of semiconductor chips. The semiconductor manufacturing apparatus comprises: a storage unit storing position information of a plurality of first lines on the first surface of the semiconductor wafer that are scheduled to be cut and position information of second lines among the plurality of first lines that are scheduled not to be cut; and The cutting unit cuts the semiconductor wafer along the plurality of first lines excluding the second lines.

2. The semiconductor manufacturing apparatus according to claim 1, The second lines are set for line segments of each of the plurality of first lines corresponding to sides of the plurality of semiconductor chips adjacent to the plurality of first lines, respectively.

3. The semiconductor manufacturing apparatus according to claim 2, The semiconductor manufacturing apparatus further includes a receiving unit configured to receive position information of a defect of the semiconductor wafer. The storage unit further stores position information of the defect and position information of a first region to be removed by cutting between the adjacent plurality of semiconductor chips, and stores a line portion within the plurality of first lines corresponding to the first region where the defect exists as the second line.

4. The semiconductor manufacturing apparatus according to claim 3, The storage unit further stores product information about a plurality of products, the product information including size information of the plurality of semiconductor chips and interval information between the plurality of adjacent first lines. The semiconductor manufacturing apparatus further includes a calculation unit configured to set the first region based on the position information of the plurality of first lines, the size information, and the interval information.

5. The semiconductor manufacturing apparatus according to claim 4, The plurality of first lines include a plurality of first planned cutting lines extending in a first direction on the semiconductor wafer and a plurality of second planned cutting lines extending in a second direction intersecting the first direction. If the width of the plurality of semiconductor chips in the first direction is cX, the width of the plurality of semiconductor chips in the second direction is cY, the interval between the plurality of second predetermined cutting lines adjacent in the first direction is pX, and the interval between the plurality of first predetermined cutting lines adjacent in the second direction is pY, The calculation unit then sets an area having a width of ±(pY-cY) / 2 in the second direction from each of the multiple first predetermined cutting lines and an area having a width of ±(pX-cX) / 2 in the first direction from each of the multiple second predetermined cutting lines as the first area.

6. The semiconductor manufacturing apparatus according to claim 3, The semiconductor manufacturing apparatus further includes a calculation unit configured to set the second line within the plurality of first lines corresponding to the first region where the defect exists, based on the position information of the defect and the position information of the first region.

7. The semiconductor manufacturing apparatus according to claim 6, The calculation unit sets the second line for each line segment of each of the lines corresponding to the sides of the plurality of adjacent semiconductor chips among the plurality of first lines corresponding to the first region where the defect exists.

8. The semiconductor manufacturing apparatus according to claim 3, The semiconductor manufacturing device further includes a display unit and an input unit. The display unit displays the position of the defect in the semiconductor wafer, the plurality of first lines, and the first region, The input unit allows a user to select the second line from among the plurality of first lines based on the position of the defect and the first region.

9. The semiconductor manufacturing apparatus according to claim 1, The semiconductor manufacturing apparatus further includes a transmission unit configured to externally transmit position information of one or more semiconductor chips adjacent to the second line among the plurality of semiconductor chips.

10. The semiconductor manufacturing apparatus according to claim 9, The position information of the semiconductor chip is position information of the plurality of first lines surrounding the one or more semiconductor chips adjacent to the second line.

11. The semiconductor manufacturing apparatus according to claim 1, The cutting unit is a blade or a laser generator that cuts the semiconductor wafer into the plurality of semiconductor chips.

12. A method for manufacturing a semiconductor device, comprising using a semiconductor manufacturing device having a cutting unit, wherein the cutting unit cuts a semiconductor wafer into a plurality of semiconductor chips. The method for manufacturing a semiconductor device comprises: Based on position information of a plurality of first lines to be cut on the first surface of the semiconductor wafer and position information of second lines which are line portions of a portion of the plurality of first lines, the semiconductor wafer is cut along the plurality of first lines excluding the second lines.

13. The manufacturing method according to claim 12, The second lines are set for line segments of each of the plurality of first lines corresponding to sides of the plurality of semiconductor chips adjacent to the plurality of first lines, respectively.

14. The manufacturing method according to claim 13, The second line is set in the plurality of first lines corresponding to the first region where the defect exists based on position information of the defect of the semiconductor wafer and position information of a first region to be removed by cutting between the adjacent plurality of semiconductor chips.

15. The manufacturing method according to claim 14, The semiconductor manufacturing device further includes a calculation unit, the calculation unit setting the first area, The manufacturing method further comprises: Before cutting the semiconductor wafer, the calculation unit sets the first region based on the position information of the plurality of first lines, the size information of the plurality of semiconductor chips, and the interval information between the plurality of adjacent first lines.

16. The manufacturing method according to claim 15, The plurality of first lines include a plurality of first planned cutting lines extending in a first direction on the semiconductor wafer and a plurality of second planned cutting lines extending in a second direction intersecting the first direction. If the width of the plurality of semiconductor chips in the first direction is cX, the width of the plurality of semiconductor chips in the second direction is cY, the interval between the plurality of second predetermined cutting lines adjacent in the first direction is pX, and the interval between the plurality of first predetermined cutting lines adjacent in the second direction is pY, The calculation unit then sets as the first area an area having a width of ±(pY-cY) / 2 in the second direction from each of the multiple first predetermined cutting lines and an area having a width of ±(pX-cX) / 2 in the first direction from each of the multiple second predetermined cutting lines.

17. The manufacturing method according to claim 14, The semiconductor manufacturing device further includes a calculation unit for setting the second line. The manufacturing method further comprises: Before cutting the semiconductor wafer, the calculation unit sets a line portion of the plurality of first lines corresponding to the first region where the defect exists as the second line based on the position information of the defect and the position information of the first region.

18. The manufacturing method according to claim 17, The calculation unit sets the second line for each line segment of each of the lines corresponding to the sides of the plurality of adjacent semiconductor chips among the plurality of first lines corresponding to the first region where the defect exists.

19. The manufacturing method according to claim 14, The semiconductor manufacturing device further includes a display unit and an input unit. The manufacturing method further comprises: Before cutting the semiconductor wafer, the position of the defect in the semiconductor wafer, the plurality of first lines, and the first region are displayed on the display unit, and the second line selected by a user from among the plurality of first lines is input through the input unit.

20. The manufacturing method according to claim 12, The semiconductor manufacturing device further includes a transmitting unit. The manufacturing method further comprises: Position information of one or more semiconductor chips adjacent to the second line among the plurality of semiconductor chips is transmitted to the outside.

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