Method for improving isolation performance of semiconductor transistor device
By forming a trench isolation structure and trench capacitance between the P-type and N-type doped well regions of the semiconductor device, the problems of insufficient transistor density and high power consumption in the prior art are solved, and higher isolation performance and lower power consumption are achieved.
Patent Information
- Application Number
- CN202311142010.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-09-05
- Publication Date
- 2025-03-11
AI Technical Summary
In existing semiconductor manufacturing processes, shallow trench isolation (STI) technology leads to insufficient transistor density, resulting in waste of area and cost, while also leading to functional errors and higher power consumption.
A trench isolation structure is formed between the P-type doped well region and the N-type doped well region, and a trench isolation structure and trench capacitance are formed by depositing polysilicon to improve the isolation performance of semiconductor devices.
By increasing the trench isolation structure and trench capacitance, the isolation effect between semiconductor devices is improved, power consumption is reduced and the possibility of functional errors is reduced, thereby improving the performance and efficiency of integrated circuits.
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Figure CN119601526A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of integrated circuits, and in particular to a method for improving the isolation performance of a semiconductor transistor device. Background Art
[0002] In integrated circuit design, the transistor density per unit area is directly related to the design cost, so increasing the transistor density per unit area can effectively reduce the cost. In current semiconductor manufacturing processes, shallow trench isolation (STI) is mainly used to isolate NMOS transistors and PMOS transistors.
[0003] STI has relatively large requirements for spacing, so the area of a single transistor will be limited by the spacing, so that the transistor density per unit area cannot reach the optimal level, resulting in a waste of area and an increase in cost. When using STI, there is a probability that the n+ region in the P-type doped well region is connected to the N-type doped well region, which will cause transistor functional errors, and the entire chip may not work properly. Therefore, in order to ensure the correct functionality of the chip, technicians are required to analyze and solve the above problems, which increases the mass production cycle of the chip, increases labor costs, and the chip may need to be re-manufactured, which will also increase manufacturing costs. At the same time, a higher transistor density will inevitably lead to higher power consumption. In order to ensure the performance of the integrated circuit, the stability of the power supply must be guaranteed, that is, the resistance of the power supply network must be reduced, and the decoupling capacitor in the area must be increased. The only way to reduce the resistance of the power supply network is to increase the metal overhead of the power line, which will reduce the integration of the transistor, or use more layers of metal for the power supply network reinforcement. Both methods will increase manufacturing costs. For decoupling capacitors, they are often added to the design after the functional circuit is implemented, and this is already in the later stage of integrated circuit design. Therefore, designers will face a very embarrassing situation. If the decoupling capacitors added in the remaining places after the functional circuit is implemented cannot meet the voltage drop requirements of the design, it is necessary to re-plan and complete the design again, which wastes time and increases the design cycle, indirectly leading to an increase in design costs. Designers often estimate the area with large voltage drop in the early stage of design and add decoupling capacitors in this area in advance. This method can reduce the probability of rework, but it will lead to a waste of chip area and is not conducive to the unit optimization of integrated circuit layout and wiring, thereby reducing the frequency performance of the integrated circuit. In addition, in the design of process nodes below 28nm, leakage is caused by the reduction of gate oxide thickness. In some low-power designs, the addition of decoupling capacitors will lead to a further increase in leakage. In addition, in some high-performance mixed-signal circuit designs, in order to isolate the noise between different voltage domains, either a complex isolation ground line design is adopted, or external decoupling capacitors are added, which increases the cost of the design. Summary of the invention
[0004] Based on the above problems, an embodiment of the present invention provides a method for improving the isolation performance of a semiconductor transistor device, comprising: providing a substrate; etching the front side of the substrate to form a groove between a P-type doped well region and an N-type doped well region; forming a dielectric layer on the surface of the groove; depositing polysilicon to fill the groove to form a trench isolation structure, so that the trench isolation structure separates the P-type doped well region and the N-type doped well region.
[0005] In some embodiments, before depositing polysilicon to fill the trench and form a trench isolation structure, the process also includes: removing the dielectric layer at the bottom of the trench by etching to expose the substrate, so that the trench separates the P-type doped well region and the N-type doped well region, thereby forming a trench capacitor after depositing polysilicon.
[0006] In some embodiments, the method further includes: thinning the back side of the substrate to expose the polysilicon, so that the trench separates the P-type doped well region and the N-type doped well region and forms a trench capacitor.
[0007] In some embodiments, the trench is formed at a junction of the P-type doped well region and the N-type doped well region.
[0008] In some embodiments, the polysilicon is grounded.
[0009] In some embodiments, the method is applied to an image sensor.
[0010] In some embodiments, the substrate includes a first substrate of a first doping type located below, and a second substrate of a second doping type opposite to the first doping type formed by epitaxy above the first substrate; the P-type doped well region and the N-type doped well region are formed in the second substrate by ion implantation or diffusion; the depth of the trench extends to the first substrate, so that the polysilicon is electrically connected to the first substrate.
[0011] In some embodiments, the substrate includes a first substrate of a first doping type located below, a second substrate of a second doping type opposite to the first doping type formed by epitaxy above the first substrate, and a third substrate of the first doping type formed by epitaxy above the second substrate; the P-type doped well region and the N-type doped well region are formed in the third substrate by ion implantation or diffusion; the depth of the trench extends to the first substrate, so that the polysilicon is electrically connected to the first substrate.
[0012] In some embodiments, the second substrate at both sides of the trench is connected to a positive potential.
[0013] In some embodiments, the first doping type is P-type and the second doping type is N-type.
[0014] In some embodiments, the method further includes: etching the substrate of the P-type doped well region to form a first hole; the depth of the first hole extends into the second substrate; and forming an electrical connection in the first hole by depositing a conductive material and connecting it to a positive potential.
[0015] In some embodiments, the method further includes: etching the polysilicon to form a second hole; and forming an electrical connection in the second hole by depositing a conductive material and connecting to a ground terminal.
[0016] In some embodiments, the trench capacitor is formed in a peripheral logic circuit of the image sensor.
[0017] In some embodiments, the method further includes: forming a gate, a source, and a drain of an NMOS transistor in the P-type doped well region, and forming a gate, a source, and a drain of a PMOS transistor in the N-type doped well region.
[0018] In some embodiments, one of the PMOS transistors and one of the NMOS transistors form a standard cell; and the peripheral logic circuit of the image sensor includes a plurality of the standard cells arranged in an array.
[0019] In some embodiments, the P-type doped well region and the N-type doped well region are formed by ion implantation or diffusion before the trench is formed.
[0020] The embodiment of the present invention can increase the isolation effect between semiconductor devices by adding a trench isolation structure between a P-type doped well region and an N-type doped well region and forming a trench capacitor. BRIEF DESCRIPTION OF THE DRAWINGS
[0021] The present invention will be further explained in the form of exemplary embodiments, which will be described in detail by means of the accompanying drawings. These embodiments are not restrictive, and in these embodiments, the same numerals represent the same structure.
[0022] Figure 1 The present invention is a flowchart of a method for improving the isolation performance of a semiconductor transistor device according to an embodiment of the present invention.
[0023] Figures 2 to 16 The cross-sectional schematic diagram of a semiconductor structure during a method for improving isolation performance of a semiconductor transistor device according to an embodiment of the present invention. DETAILED DESCRIPTION
[0024] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some examples or embodiments of the present invention. For ordinary technicians in this field, the present invention can also be applied to other similar scenarios based on these drawings without creative work. Unless it is obvious from the language environment or otherwise explained, the same reference numerals in the figures represent the same structure or operation.
[0025] Figure 1 Flow chart of a method 100 for improving isolation performance of a semiconductor transistor device according to an embodiment of the present invention.
[0026] A method 100 for improving isolation performance of a semiconductor transistor device includes: Step 101: Provide a substrate.
[0027] Step 102: Etching the front surface of the substrate to form a trench between the P-type doped well region and the N-type doped well region.
[0028] Step 103: forming a dielectric layer on the surface of the groove.
[0029] Step 104: depositing polysilicon to fill the trench and form a trench isolation structure, so that the trench isolation structure separates the P-type doped well region and the N-type doped well region.
[0030] Specifically, for step 101 , the embodiment of the present invention provides two substrates.
[0031] refer to Figure 2 , an embodiment of the present invention provides a first substrate, which may include a first substrate 201 of a first doping type (e.g., P type) located below, and a second substrate 202 of a second doping type (e.g., N type) opposite to the first doping type formed by epitaxy located above the first substrate 201. Further, a P-type doped well region and an N-type doped well region may be formed in the second substrate 202 by ion implantation or diffusion.
[0032] refer to Figure 3 , an embodiment of the present invention provides a second substrate, which may include a first substrate 201 of a first doping type (e.g., P type) located below, a second substrate 202 of a second doping type (e.g., N type) opposite to the first doping type formed by epitaxy located above the first substrate 201, and a third substrate 203 of the first doping type formed by epitaxy located above the second substrate. Further, a P-type doped well region and an N-type doped well region may be formed in the third substrate 202 by ion implantation or diffusion.
[0033] For the convenience of description, the embodiments of the present invention are described as follows. Figure 3 The following description is made taking the substrate shown as an example.
[0034] Before step 102, refer to Figure 4 , an ion implantation or diffusion process is performed on the substrate to form a P-type doped well region 203a and an N-type doped well region 203b on the substrate.
[0035] For step 102, refer to Figure 5 , the front side of the substrate is etched to form a trench 204 between the P-type doped well region 203a and the N-type doped well region 203b. The depth of the trench 204 extends to the first substrate 201. In the embodiment of the present invention, the trench 204 is formed at the junction of the P-type doped well region 203a and the N-type doped well region 203b.
[0036] For step 103, refer to Figure 6 A dielectric layer 205 is formed on the surface of the groove 204. The dielectric layer 205 may be silicon oxide, silicon nitride, silicon oxynitride or a combination thereof.
[0037] For step 104 , in order to separate the P-type doped well region 203 a from the N-type doped well region 203 b , the present invention provides two embodiments.
[0038] For the first embodiment, refer to Figures 7 to 11 .
[0039] refer to Figure 7 , polysilicon 206 is deposited to fill the trench 204 .
[0040] refer to Figure 8 The gate, source and drain of the NMOS transistor 207a are formed in the P-type doped well region 203a, and the gate, source and drain of the PMOS transistor 207b are formed in the N-type doped well region 203b.
[0041] refer to Fig. 9 , the P-type doped well region is etched to form a first hole 208a; the depth of the first hole 208a extends into the second substrate 202, and the polysilicon 206 is etched to form a second hole 208b.
[0042] refer to Fig.10 By depositing a conductive material, an electrical connection is formed in the first hole 208a and connected to a positive potential, and an electrical connection is formed in the second hole 208b and connected to a ground terminal. The conductive material can be a metal or alloy material such as tungsten, copper, aluminum, etc.
[0043] refer to Fig.11, the back side of the substrate is thinned to expose the polysilicon 206, so that the trench isolation structure separates the P-type doped well region 203a from the N-type doped well region 203b, and forms a trench capacitor of polysilicon-dielectric layer-substrate. For example, in the manufacturing process of a back-illuminated image sensor, a support wafer can be bonded to the front side of the substrate, and then the back side of the substrate is subjected to chemical mechanical polishing.
[0044] For the second embodiment, refer to Figures 12 to 16 .
[0045] refer to Fig.12 Before depositing polysilicon 206 to fill the trench 204 , the dielectric layer 205 at the bottom of the trench 204 is removed by etching to expose the substrate (or the first substrate 201 ).
[0046] refer to Fig.13 , polysilicon 206 is deposited to fill the trench 204 to form a trench isolation structure.
[0047] refer to Fig.14 The gate, source and drain of the NMOS transistor 207a are formed in the P-type doped well region 203a, and the gate, source and drain of the PMOS transistor 207b are formed in the N-type doped well region 203b.
[0048] refer to Fig.15 , the P-type doped well region is etched to form a first hole 208a; the depth of the first hole 208a extends into the second substrate 202, and the polysilicon 206 is etched to form a second hole 208b.
[0049] refer to Fig.16 By depositing a conductive material, an electrical connection is formed in the first hole 208a and connected to a positive potential, and an electrical connection is formed in the second hole 208b and connected to the ground end to form a trench capacitor of polysilicon-dielectric layer-substrate.
[0050] The embodiment of the present invention can be applied to the manufacturing process of an image sensor. For example, the trench capacitor can be formed in the peripheral logic circuit of the image sensor. The polysilicon 206 is connected to the ground. The second substrate 202 on both sides of the trench 204 is connected to a positive potential. A PMOS transistor and an NMOS transistor can form a standard unit; the peripheral logic circuit of the image sensor can include multiple standard units arranged in an array.
[0051] It should be noted that some process steps are omitted in the above-mentioned formation process, such as exposure, development, chemical mechanical polishing, etc. The basic concepts have been described above. Obviously, for those skilled in the art, the above detailed disclosure is only an example and does not constitute a limitation of the present invention. Although it is not explicitly stated here, those skilled in the art may make various modifications, improvements and corrections to the present invention. Such modifications, improvements and corrections are suggested in the present invention, so such modifications, improvements and corrections still belong to the spirit and scope of the exemplary embodiments of the present invention. It should be understood that the embodiments described in the present invention are only used to illustrate the principles of the embodiments of the present invention. Other variations may also fall within the scope of the present invention. Therefore, as an example and not a limitation, the alternative configurations of the embodiments of the present invention may be regarded as consistent with the teachings of the present invention. Accordingly, the embodiments of the present invention are not limited to the embodiments explicitly introduced and described in the present invention.
Claims
1. A method for improving the isolation performance of a semiconductor transistor device, characterized in that: include: providing a substrate; Etching the front surface of the substrate to form a groove between the P-type doped well region and the N-type doped well region; forming a dielectric layer on the surface of the groove; Polysilicon is deposited to fill the trench to form a trench isolation structure, so that the trench isolation structure separates the P-type doped well region and the N-type doped well region.
2. The method according to claim 1, characterized in that Before depositing polysilicon to fill the trench and form a trench isolation structure, the method further includes: The dielectric layer at the bottom of the trench is removed by etching to expose the substrate, so that the trench separates the P-type doped well region and the N-type doped well region, thereby forming a trench capacitor after depositing polysilicon.
3. The method according to claim 1, characterized in that Also includes: The back side of the substrate is thinned to expose the polysilicon, so that the trench separates the P-type doped well region and the N-type doped well region and forms a trench capacitor.
4. The method according to claim 1, characterized in that The trench is formed at the junction of the P-type doped well region and the N-type doped well region.
5. The method according to claim 2 or 3, characterized in that: The polysilicon is grounded.
6. The method according to claim 1, characterized in that The method is applied to an image sensor.
7. The method according to claim 5, characterized in that The substrate comprises a first substrate of a first doping type located below, and a second substrate of a second doping type opposite to the first doping type formed by epitaxy and located above the first substrate; Forming the P-type doped well region and the N-type doped well region in the second substrate by ion implantation or diffusion; The depth of the trench extends to the first substrate, so that the polysilicon is electrically connected to the first substrate.
8. The method according to claim 5, characterized in that The substrate comprises a first substrate of a first doping type located below, a second substrate of a second doping type opposite to the first doping type formed by epitaxy located above the first substrate, and a third substrate of the first doping type formed by epitaxy located above the second substrate; Forming the P-type doped well region and the N-type doped well region in the third substrate by ion implantation or diffusion; The depth of the trench extends to the first substrate, so that the polysilicon is electrically connected to the first substrate.
9. The method according to claim 7 or 8, characterized in that The second substrate at both sides of the groove is connected to a positive potential.
10. The method according to claim 7 or 8, characterized in that The first doping type is P type, and the second doping type is N type.
11. The method according to claim 7 or 8, characterized in that The method further comprises: etching the substrate of the P-type doped well region to form a first hole; the depth of the first hole extends into the second substrate; By depositing a conductive material, an electrical connection is formed in the first hole and connected to a positive potential.
12. The method according to claim 7 or 8, characterized in that The method further includes: etching the polysilicon to form a second hole; By depositing a conductive material, an electrical connection is formed in the second hole and connected to a ground terminal.
13. The method according to claim 1, characterized in that The trench capacitor is formed in a peripheral logic circuit of the image sensor.
14. The method according to claim 11, characterized in that The method further comprises: The gate, source and drain of the NMOS transistor are formed in the P-type doped well region, and the gate, source and drain of the PMOS transistor are formed in the N-type doped well region.
15. The method according to claim 14, characterized in that One PMOS transistor and one NMOS transistor form a standard unit; the peripheral logic circuit of the image sensor includes a plurality of the standard units arranged in an array.
16. The method according to claim 1, wherein: The P-type doped well region and the N-type doped well region are formed by ion implantation or diffusion before the trench is formed.