Three-dimensional packaging structure and manufacturing method thereof

Abstract

The invention provides a three-dimensional packaging structure and a manufacturing method thereof, and the method comprises the steps: arranging a first chip and a second chip on a first rewiring layer in a stacking manner before a second rewiring layer is formed, enabling the first chip to be welded on the first rewiring layer in a flip-chip manner, enabling the second chip to be electrically connected with the first rewiring layer through lead bonding, and enabling the second chip to be electrically connected with the second rewiring layer through lead bonding; the chips can be electrically coupled by using the first rewiring layer, so that chip stacking packaging is realized, a TSV (Through Silicon Via) process on the chips is not needed, and the process complexity of chip stacking packaging is greatly reduced; and then, the first chip, the second chip and the first rewiring layer are coated with a plastic package layer, and bottom filling, wrapping and plastic package of multiple chips can be completed through a one-step plastic package process, so that the manufacturing cost is saved. The three-dimensional packaging structure comprises the metal connecting columns formed through the sintering process, the through hole filling efficiency is effectively improved, the interconnection yield is improved, and a series of complex processes such as deposition of a barrier layer and a conductive layer and electroplating of a metal layer are avoided.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor packaging, and in particular relates to a three-dimensional packaging structure and a manufacturing method thereof. Background Art

[0002] Semiconductor technology continues to evolve in the direction of Moore's Law. As the signal rate doubles every 3 to 4 years, the distance that electrical signals can be transmitted is gradually decreasing. Based on cost considerations, people are still trying to extend the life of electrical signal transmission. However, since chip packaging and process capabilities cannot be infinitely improved, the increase in power consumption caused by the continuous increase in IO rate will eventually hit the power wall of chip packaging. Therefore, as semiconductor products develop from two-dimensional to three-dimensional, 2.5D / 3D advanced packaging technology with through silicon via (TSV) as the core has been proposed. Through silicon via (TSV) technology refers to the vertical interconnection between the upper and lower surfaces of silicon. Through silicon vias can be formed on functional chips or on silicon adapters. Silicon adapters with TSV vertical interconnection vias and high-density metal wiring can increase system integration density and achieve system-level heterogeneous integration. Mixed interconnection of multiple / heterogeneous computing units under the requirements of extremely high bandwidth and reliable rate can greatly reduce product size, increase packaging connection speed, reduce signal delay, and improve product performance.

[0003] At present, the 2.5D or 3D packaging technology based on silicon adapter board is used to realize chip interconnection. Multiple chips are often arranged side by side, or the chip and silicon adapter board are stacked and packaged. The chip and silicon adapter board stacked packaging scheme often needs to perform the following series of steps: a single-layer chip is bonded to the front rewiring layer of the silicon adapter board; a bottom filling layer is formed between the chip and the front rewiring layer; and then a thinning process is performed on the silicon adapter board. Before performing the thinning process, the chip needs to be bonded to a temporary carrier as a carrier, which increases the cost and also increases the bonding and debonding steps of the temporary carrier. For example, patent CN102460677A uses low temperature or room temperature to perform debonding of device wafers and carriers, including: applying a UV-curable adhesive or a laser absorbing release layer to the surface of the device wafer by spin coating or lamination; applying a UV-curable adhesive or a laser absorbing release layer to the surface of the carrier as appropriate; bonding the device wafer to the carrier by hot compression bonding or liquid phase curing; mechanically or excimer laser-assisted debonding of the device wafer and the carrier at low temperature or room temperature. It can be seen that the above operation of temporarily bonding the device wafer to the carrier is relatively complicated and will cause waste of process materials. In addition, the through silicon via (TSV) process on the chip can also be used to implement a chip stacking solution on the same side of the silicon adapter, but this process flow is complicated and costly.

[0004] It should be noted that the above introduction to the technical background is only for the convenience of providing a clear and complete description of the technical solutions of the present application and for the convenience of understanding by those skilled in the art. It cannot be considered that the above technical solutions are well known to those skilled in the art simply because they are described in the background technology section of the present application. Summary of the invention

[0005] In view of the shortcomings of the prior art described above, the purpose of the present invention is to provide a three-dimensional packaging structure and a manufacturing method thereof, so as to solve the problems in the prior art of chip stacking solutions based on packaging adapter plates, such as complex processes, excessively high equipment and material costs, and low production efficiency.

[0006] To achieve the above objectives and other related objectives, the present invention provides a method for manufacturing a three-dimensional packaging structure, comprising:

[0007] A substrate is provided, wherein the substrate has a first main surface and a second main surface opposite to each other, and the substrate includes a metal column formed through the first main surface of the substrate along a thickness direction thereof;

[0008] forming a first redistribution layer on the first main surface of the substrate, wherein the first main surface of the first redistribution layer is electrically connected to the metal pillar;

[0009] Flip-chip bonding a first chip on a second main surface of the first redistribution layer opposite to the first main surface;

[0010] stacking a second chip on the first chip, the second chip being electrically connected to the first redistribution layer through wire bonding so that the second chip is electrically coupled to the first chip;

[0011] Forming a plastic packaging layer covering the stacked first chip and the second chip and the first redistribution layer;

[0012] Thinning the second main surface of the substrate until the metal pillar in the blind hole is exposed;

[0013] A second redistribution layer is formed on the second main surface of the substrate, and the second redistribution layer is electrically connected to the metal pillar.

[0014] Optionally, the second chip is attached to the first chip by using a chip bonding layer; after curing the chip bonding layer, the second chip is electrically connected to the first redistribution layer by using metal wires.

[0015] Optionally, the step of forming the metal pillar includes:

[0016] Providing a substrate, and etching at least one blind hole from a first main surface of the substrate along a thickness direction thereof;

[0017] forming a passivation layer at least on the sidewall and bottom of the blind hole;

[0018] The passivation layer is covered with a metal filling material and the blind hole is filled.

[0019] Furthermore, the step of forming the metal pillar further includes:

[0020] Applying a sintering precursor containing a metal into the blind hole, and mixing and filling the sintering precursor into the blind hole by shaking, wherein the sintering precursor is in powder form and mainly consists of metal powder and glass powder;

[0021] Removing the sintering precursor covering the surface of the substrate;

[0022] The sintering precursor is sintered under a protective atmosphere to form a metal column filling the blind hole.

[0023] Furthermore, the content of the glass powder is in the range of 10% to 15%, the metal powder is mainly copper powder, the content of the copper powder is in the range of 85% to 90%, and the metal column obtained by sintering has a conductive network structure with the glass component around the copper particles as the network skeleton and physical contact between the copper particles.

[0024] Furthermore, the particle size of the metal powder is in the range of ≤500 nm, and the particle size of the glass powder is in the range of 0.8 μm to 1.2 μm.

[0025] Optionally, the first chip is flip-chip bonded to the second main surface of the first redistribution layer by a thermocompression bonding process, wherein the first redistribution layer comprises at least two layers of organic dielectric layers and metal wiring layers that are alternately arranged.

[0026] Optionally, the plastic encapsulation layer is used as a carrier to thin the substrate from the second main surface of the substrate until the metal column in the blind hole is exposed.

[0027] Optionally, the step of forming a second rewiring layer on the second main surface of the substrate includes: removing the passivation layer at the bottom of the blind hole by a chemical mechanical polishing process to expose the metal column; forming a second rewiring layer on the second main surface of the substrate, the second rewiring layer being electrically connected to the metal column exposed on the second main surface of the substrate; and forming a metal bump on the side of the second rewiring layer away from the substrate.

[0028] The present invention also provides a three-dimensional packaging structure, which is manufactured based on the aforementioned method for manufacturing the three-dimensional packaging structure.

[0029] As described above, the three-dimensional packaging structure and the manufacturing method thereof of the present invention, before forming the second rewiring layer, stack the first chip and the second chip on the first rewiring layer, the first chip is flip-chip soldered on the first rewiring layer, the second chip is electrically connected to the first rewiring layer by wire bonding, and the first rewiring layer can be used to electrically couple the first chip and the second chip, thereby realizing chip stacking packaging, without the need to achieve electrical connection between the stacked chips through the TSV process on the chip, greatly reducing the process complexity of chip stacking packaging, and helping to save manufacturing costs; subsequently, a plastic sealing layer is formed on the first chip, the second chip and the first rewiring layer, and the bottom filling, wrapping and plastic sealing of multiple chips can be completed through a one-step plastic sealing process; in addition, the molded plastic sealing layer can act as a carrier during the back thinning process, without the need for an additional temporary carrier, and the above process effectively reduces the process complexity and manufacturing cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 The graph shows the relationship between the process parameters of the electroplating process and the sample filling effect.

[0031] Figures 2 to 11 Shown are structural schematic diagrams corresponding to various stages in an exemplary process flow of a three-dimensional packaging structure in a comparative example of the present invention.

[0032] Figures 12 to 30 Shown are structural schematic diagrams corresponding to various stages in the process flow of the three-dimensional packaging structure in an embodiment of the present invention.

[0033] Fig.31 It is a schematic structural diagram of a wafer boat used in step S10 of the method for manufacturing a packaging adapter of the present invention.

[0034] Component number description

[0035] 100 Silicon Wafer

[0036] 102 Photoresist layer

[0037] 110 Silicon Blind Via

[0038] 112 Passivation layer

[0039] 114 Conductive layer

[0040] 115 Metal Layer

[0041] 116 Metal Column

[0042] 117 Front Rewiring Layer

[0043] 118 Temporary slide

[0044] 119 Backside redistribution layer

[0045] 120 metal bumps

[0046] 130 Chip

[0047] 131 Bottom Fill

[0048] 200 substrates

[0049] 200a First main surface

[0050] 200b Second main surface

[0051] 202 photoresist layer

[0052] 203 Patterned photoresist layer

[0053] 204 Mask

[0054] 210 Blind hole

[0055] 212 Passivation layer

[0056] 213 Protective film

[0057] 214 Sintering Precursor

[0058] 216 Metal Column

[0059] 217 First redistribution layer

[0060] 219 Second redistribution layer

[0061] 220 metal bumps

[0062] 217a Patterned dielectric layer

[0063] 217b Inlaid metal wiring layer

[0064] 30 First Chip

[0065] 40 Second Chip

[0066] 50 SMD components

[0067] 610 Interconnect

[0068] 620 Metal Lead

[0069] 710 Die Attach Layer

[0070] 720 plastic layer

[0071] 80 Crystal Boat DETAILED DESCRIPTION

[0072] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0073] See also Figures 1 to 31 It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0074] See also Figures 2 to 11 , which is a schematic structural diagram corresponding to each stage of an exemplary process flow of a three-dimensional packaging structure in a comparative example of the present invention:

[0075] (1) Figure 2-3 As shown, a silicon wafer 100 is provided. The silicon wafer 100 has a first main surface and a second main surface opposite to each other. The silicon wafer 100 includes at least one silicon blind hole 110 formed by etching along the thickness direction of the first main surface of the silicon wafer.

[0076] (2) Figures 4 to 6 As shown, a passivation layer 112, a barrier layer (not shown), a conductive layer 114 and a metal layer 115 are sequentially formed on the bottom and sidewalls of the silicon blind hole 110 and the surface of the silicon wafer 100. The passivation layer 112 is arranged between the silicon wafer 100 and the conductive layer 114 to prevent direct contact between the silicon material and the subsequently deposited metal.

[0077] (3) Figure 7 As shown, the structure surface obtained by the planarization process step (2) removes the metal layer, barrier layer and passivation layer covering the silicon wafer to form a metal column 116;

[0078] (4) Figure 8-Figure 9 As shown, a front rewiring layer 117 is formed on the first main surface of the silicon wafer 100, and the first main surface of the front rewiring layer 117 is electrically connected to the metal pillar 116;

[0079] (5) Fig.10 As shown, a chip 130 is flip-chip-bonded on the second main surface of the front rewiring layer 117 , and an underfill layer 131 is formed between the chip 130 and the front rewiring layer 117 ;

[0080] (6) Continue to see Fig.10, bonding the chip 130 to the temporary carrier 118 as a carrier, and thinning the silicon wafer 100 from the second main surface of the silicon wafer until the metal pillar in the blind hole is exposed;

[0081] Thereafter, steps (7) to (8) are performed, and steps of backside rewiring layer 119 and backside electrical lead-out are performed in sequence based on the silicon wafer obtained in step (6). The obtained structure is as follows: Fig.11 shown.

[0082] like Figure 4 As shown, a passivation layer 112 is deposited on the inner surface of the silicon blind hole 110. Since silicon is a semiconductor and cannot directly contact with the subsequently deposited metal, an insulating layer needs to be deposited.

[0083] like Figure 5 As shown, a barrier layer (not shown) and a conductive layer 114 are deposited on the passivation layer 112. The thickness and uniformity of the conductive layer deposited in this step will affect the crystal quality and filling capacity of the metal layer formed by the subsequent electroplating process. Typically, a physical vapor deposition (PVD) process is used to deposit the barrier layer and the conductive layer 114. The PVD process is very challenging to achieve a conformal continuous thin film layer of a micro-hole with a high aspect ratio, which can easily cause poor film thickness and uniformity on the sidewalls of the micro-hole, especially the sidewalls near the bottom, and the required equipment is relatively expensive.

[0084] like Figure 6 As shown, the electroplating process is performed with the pre-deposited conductive layer 114 as the cathode. The deposition of the conductive layer will affect the filling capacity and electrical properties of the metal layer in the subsequent filling process. Typically, the conductive layer 114 is deposited using a physical vapor deposition process such as an electron beam evaporation process, and the coverage of the sidewalls of the blind hole or through hole is not ideal, especially for blind holes or through holes with a high aspect ratio, resulting in uneven film layers or cracks. The electroplating process is performed based on this conductive layer, and the metal filling in the blind hole finally has defects such as voids.

[0085] like Fig.10 As shown, at step (6), a temporary carrier 118 is bonded to the front side of the silicon wafer through processes such as gluing and curing. The temporary carrier 118 may have substantially the same size as the silicon wafer to protect the front side graphics during subsequent processes to avoid loss during subsequent processes.

[0086] like Fig.11 As shown, step (8) also includes removing the temporary carrier 118, and the removal step of the temporary carrier 118 is performed by laser debonding, physical disassembly or chemical solution immersion.

[0087] In addition, the inventors also realized that there are the following problems in manufacturing a three-dimensional packaging structure through the above process flow:

[0088] 1. Factors that need to be considered in the filling efficiency of the electroplating process, especially for blind holes, through holes or similar structures with a large depth-to-width ratio, the specific process parameters in the electroplating process will be appropriately adjusted to reduce the efficiency of electroplating, such as current density, thereby avoiding the appearance of seams or voids in the metal filler. Figure 1 As shown in the figure, it reflects the relationship between the filling effect of the sample and the duration of the electroplating process. It can be seen that the filling step itself takes a long time in the production process of the silicon adapter. As can be seen from the figure, comparing the electroplating efficiency of sample A and sample C, to increase the filling effect of the metal layer by 20%, sample C needs to consume several times the process time of sample A. The electroplating time of a single piece can reach more than 6 hours, which is inefficient, and the price of the electroplating equipment is very expensive;

[0089] Second, after performing single-layer chip bonding, the bottom filling needs to be performed first, and then the chip and the front rewiring layer are plastic-sealed. The chip plastic sealing needs to be achieved through a one-step bottom filling process and a one-step plastic sealing process. The process steps are complicated and increase the production cost, and the three-dimensional packaging of chip stacking cannot be achieved;

[0090] Third, it is necessary to bond a temporary carrier to the front side of the silicon wafer, and then use the temporary carrier as a carrier to perform back side processing, which increases the bonding and debonding steps of the temporary carrier and also increases the equipment cost; further, the above process flow cannot achieve 3D stacking.

[0091] In view of the above, the process flows of the comparative examples have high production costs, and the difficulty and process complexity of electrical interconnection between the stacked chips are relatively large, which cannot meet the needs of practical applications. The inventors of the present application have proposed a three-dimensional packaging structure and a method for manufacturing the same, which includes flip-chip welding a first chip to a first rewiring layer, then stacking a second chip on the first chip, electrically connecting the second chip to the first rewiring layer through wire bonding, forming a plastic encapsulation layer on the stacked first chip and second chip, and on the first rewiring layer, and using the plastic encapsulation layer as a carrier to thin the second main surface of the substrate. At the same time, it has low cost and low process difficulty, and therefore has broad application prospects.

[0092] Embodiment 1

[0093] See also Figures 12 to 30 It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and the illustrations only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0094] Based on this, this embodiment provides a method for manufacturing a three-dimensional packaging structure, and the manufacturing method includes the following steps:

[0095] S10: providing a substrate, wherein the substrate has a first main surface and a second main surface opposite to each other, and the substrate includes a metal column formed through the first main surface of the substrate along a thickness direction thereof;

[0096] S20: forming a first redistribution layer on the first main surface of the substrate, wherein the first main surface of the first redistribution layer is electrically connected to the metal pillar;

[0097] S30: flip-chip bonding a first chip on a second main surface of the first redistribution layer opposite to the first main surface;

[0098] S40: stacking a second chip on the first chip, wherein the second chip is electrically connected to the first redistribution layer through wire bonding so that the second chip is electrically coupled to the first chip;

[0099] S50: forming a plastic packaging layer covering the stacked first chip and the second chip and the first redistribution layer;

[0100] S60: thinning the second main surface of the substrate until the metal pillar in the blind hole is exposed;

[0101] S70: forming a second redistribution layer on the second main surface of the substrate, wherein the second redistribution layer is electrically connected to the metal pillar.

[0102] The manufacturing method of the three-dimensional packaging structure of this embodiment is to stack the first chip and the second chip on the second main surface of the first redistribution layer before forming the second redistribution layer, and use the first redistribution layer to achieve electrical coupling between the chips, without the need for TSV process on the chip, thereby effectively reducing process complexity and manufacturing cost.

[0103] The method for manufacturing the three-dimensional packaging structure of this embodiment is described in detail below with reference to the specific drawings.

[0104] See also Figures 12 to 20 First, step S10 is performed to provide a substrate 200, wherein the substrate 200 has a first main surface 200a and a second main surface 200b opposite to each other, and the substrate 200 includes a metal column 216 formed through the first main surface 200a of the substrate along the thickness direction thereof.

[0105] It should be noted here that the first main surface 200a and the second main surface 200b only represent that the substrate 200 has two opposite surfaces. Only when one of the surfaces is defined as the first main surface, the other opposite surface is the second main surface. The first and the second have no specific meanings. In addition, the thickness of the substrate 200 is selected according to actual needs, and the incoming material can be thinned as appropriate, and no excessive restrictions are made here.

[0106] Specifically, the step of forming the metal pillar 216 includes:

[0107] S11, providing a substrate 200, wherein the substrate 200 has a first main surface 200a and a second main surface 200b opposite to each other, and etching the first main surface 200a of the substrate along a thickness direction thereof to form at least one blind hole 210;

[0108] S12, forming a passivation layer 212 at least on the sidewall and bottom of the blind hole;

[0109] S13 , covering the passivation layer 212 and filling the blind hole 210 with a metal filling material.

[0110] As an example, the substrate 200 may be made of any base material suitable for preparing an adapter plate, including but not limited to a silicon substrate or a glass substrate.

[0111] like Figure 13 to Figure 16 As shown, at step S11, the steps of coating, exposing and developing the photoresist layer 202 are performed to form a patterned photoresist layer 203 on the first main surface 200a of the substrate; based on the patterned photoresist layer 203, dry etching is adopted to etch from the first main surface 200a of the substrate along the thickness direction to form at least one blind hole 210. The depth, diameter, shape, number and other parameters of the blind hole 210 are set according to the actual packaging requirements, and no excessive restrictions are made here.

[0112] For example, a vacuum etching machine is used to anisotropically etch the substrate 200 using an etching gas such as one containing SF6 and O2, and a corresponding depth is etched without significantly changing the opening of the blind hole.

[0113] As an example, step S11 also includes: after the blind hole 210 is formed by dry etching, the residual photoresist on the surface of the substrate can be removed by wet etching with a chemical solution, and the specific steps are as follows: first perform alkaline washing and then perform acid washing.

[0114] like Fig.17 As shown, in step S12, a passivation layer 212 is formed at least on the sidewall and the bottom of the blind hole.

[0115] For example, a passivation layer 212 is formed on the inner surface of the blind hole and the first main surface of the substrate by plasma enhanced chemical vapor deposition (PECVD) to separate the substrate material from the subsequently deposited metal material. In the through silicon via technology, a silicon substrate is used to manufacture an adapter. Since silicon is a semiconductor material, an insulating layer needs to be formed to separate silicon from a metal material with good conductivity.

[0116] In some embodiments, at step S13, the metal filling material is selected as a sintering precursor containing a metal, and the blind hole 210 is filled in the following manner: Figure 18 to Figure 21 As shown, a sintering precursor 214 containing metal is applied into the blind hole 210, and the sintering precursor 214 is mixed and filled into the blind hole 210 by an oscillation method. The sintering precursor 214 is in powder form and mainly consists of metal powder and glass powder.

[0117] Different from the above-mentioned manufacturing method using the electroplating process, the present embodiment preferably uses a sintering process to form the metal column, without the need to form a barrier layer and a conductive layer. The manufacturing method can quickly form a metal column without holes, with low process difficulty, while greatly reducing equipment costs and material costs.

[0118] Specifically, the substrate 200 is placed on a machine with ultrasonic oscillation in a vacuum environment, and a sintering precursor 214 containing a metal is applied to the blind hole 210, so that the sintering precursor 214 is fully mixed and fills the blind hole 210, wherein the metal powder and the glass powder can be applied separately or pre-mixed before application. The component content of the sintering precursor and the physical properties of each component can be determined based on the required electrical properties of the interconnection through hole.

[0119] As an example, the content of the glass powder is in the range of 10% to 15%, and the metal powder is mainly or includes copper powder, and the content of the copper powder is in the range of 85% to 90%.

[0120] It should be noted that the content of each component in the sintering precursor referred to herein is a percentage based on the total weight of the powdered sintering precursor, that is, mass percentage (wt%).

[0121] As an example, the metal powder also includes metal column materials commonly used in the art, including alloys of one or more metals selected from gold, silver, tin, titanium, nickel, magnesium, bismuth, palladium, nickel, chromium, iron, and indium, and the composition of the glass powder includes network formers, such as silicon oxide, boron oxide, and network intermediates, such as zinc oxide and aluminum oxide. The appropriate particle size of the metal powder can be selected according to the melting behavior of the glass powder and its wettability to the metal powder. In this embodiment, the particle size of the metal powder is ≤500nm, and the particle size of the glass powder is 0.8μm to 1.2μm, preferably 1μm to 1.2μm, and more preferably, the particle size is 1μm, which is beneficial to improve the density and bonding strength of the copper particles in the metal column, thereby optimizing the reliability and conductivity of the metal column as a whole.

[0122] like Fig.21 As shown, after completing the blind hole filling step, the process further includes: cleaning the surface of the substrate 200, cleaning the excess powder covering the surface, and collecting the metal powder as appropriate.

[0123] Furthermore, step S13 further includes: sintering the sintering precursor 214 containing metal under a protective atmosphere to form a metal column 216 filling the blind hole.

[0124] Specifically, the sintering process is performed under a protective atmosphere at a temperature lower than the melting temperature of the glass powder. During the sintering process, the glass powder is slightly melted and incompletely transformed into a liquid state. The powder is then condensed and formed into a metal column 216 by cooling. The metal column 216 has a conductive network structure with a glass component as a network skeleton and physical contact between copper particles. The conductive network structure has a network skeleton composed of the glass component around the copper particles, so that physical contact is formed between the copper particles.

[0125] Based on the above technical solution, a metal column is formed through a sintering process. The metal column has a conductive network structure with a glass component as a network skeleton, so it has good adhesion to the side wall of the passivation layer, effectively improving the efficiency of through-hole filling and the yield of interconnection. The conductivity is sufficient to meet the impedance requirements of products such as CMOS image sensors and MEMS.

[0126] As an example, the sintering process is performed in the following manner: nitrogen is introduced to provide a protective atmosphere; a sintering precursor containing a metal is sintered at a temperature of 350° C. to 400° C. in the protective atmosphere to form a metal column 216. The obtained metal column is as shown in FIG. Fig. 22 As shown, the amount of oxygen contained in the protective atmosphere is controlled to be no more than 10 ppm, which inhibits the oxidation reaction of copper particles in the conductive network structure, thereby reducing the conductivity of the metal column, and the sintering process is performed for more than 10 minutes, for example 10 minutes.

[0127] like Fig.31 As shown, the wafer boat 80 is used to carry multiple substrates and perform the sintering step at the same time. In some examples, the wafer boat 80 can be used as a carrier to perform the sintering of dozens of wafers at the same time. The wafer boat 80 shown in the figure can perform the sintering of more than 25 wafers at the same time, which greatly improves the output rate.

[0128] For example, the sintering process is performed when the oxygen content is less than 100 ppm to avoid oxidation that affects the conductivity of the copper column. The copper powder is mainly used for conductivity, and the glass component provides a network skeleton for physical contact of the copper particles and also enhances the adhesion to the side wall, without the need to form a barrier layer and a conductive layer before filling the blind hole, thereby avoiding the poor coverage of the conductive layer on the side wall of the blind hole and the generation of pores or seams.

[0129] After sintering to form the metal pillar 216, step S10 also includes: S14, performing an annealing process at a temperature higher than 600°C to destress the sintered metal pillar 216 and the substrate 100, release the residual stress in the metal filler, and reduce the thermal stress caused by the mismatch in thermal expansion coefficients between the metal filler and the substrate, thereby improving the thermal mechanical reliability of the interconnect structure.

[0130] Next, step S20 is performed to form a first redistribution layer 217 on the first main surface 200 a of the substrate, wherein the first redistribution layer 217 is electrically connected to the metal pillars 216 .

[0131] Specifically, Figure 23-24 As shown, step S20 includes: pre-processing the first main surface 200a of the substrate; forming a first rewiring layer 217 on the first main surface 200a of the substrate, the first rewiring layer 217 having a first main surface and a second main surface relative to each other, and the first rewiring layer 217 includes a patterned dielectric layer 217a and an embedded metal wiring layer 217b.

[0132] As an example, the method for forming the first rewiring layer 217 includes: forming a dielectric layer on the first main surface 200a of the substrate, and etching the dielectric layer by conventional photolithography and etching processes to form a patterned dielectric layer 217a, wherein the patterned dielectric layer 217a is formed with an opening or groove (not shown) that exposes the metal pillar 216; filling the opening or groove with metal wiring material, and then forming a mosaic metal wiring layer 217b by a patterning process, wherein the mosaic metal wiring layer 217b is formed by, for example, a single mosaic process or a double mosaic process. It should be noted here that the first rewiring layer 217 can be multi-layered according to actual needs, and the manufacturing method of each layer of the first rewiring layer 217 is the same, and the above method can be used.

[0133] For example, the first rewiring layer 217 includes at least two alternating patterned organic dielectric layers and embedded metal wiring layers, wherein the organic dielectric layers include but are not limited to one or a combination of two or more of epoxy resin, silica gel, polyimide (PI), PBO, and BCB.

[0134] Furthermore, step S20 further includes: after forming the first redistribution layer 217, forming micro bumps on the embedded metal wiring layer 217b by using a bump process.

[0135] Then, if Fig.26 As shown, step S30 is performed to flip-chip bond the first chip 30 on the second main surface of the first redistribution layer opposite to the first main surface.

[0136] As an example, a first chip 30 with solder joints is flip-chip soldered to the micro-bumps using a thermocompression bonding (TCB) process to form an interconnect 610 between the first chip 30 and the first rewiring layer 217, wherein the material of the interconnect 610 includes one or a combination of tin, silver, gold, and copper; and a patch component 50 is bonded to the second main surface of the first rewiring layer, wherein the patch component 50 is a passive device, such as a resistor, an inductor, a capacitor, etc.

[0137] For example, the first chip 30 is a silicon chip, and the interconnection 610 is made of tin, silver, and copper; when the thickness of the first chip is 100 μm, the diameter of the interconnection 610 is not less than 40 μm, and the overall height is not less than 30 μm. For example, when the height of Cu is not less than 20 μm, the height of SnAg is not less than 10 μm.

[0138] Then, if Fig.26 As shown, step S40 is performed to stack the second chip 40 on the first chip 30 , and the second chip 40 is electrically connected to the first redistribution layer 217 by wire bonding so that the second chip 40 is electrically coupled to the first chip 30 .

[0139] Specifically, the second chip 40 is attached to the first chip 30 by using a chip attach layer (DAF) 710 , and the chip attach layer 710 is cured; and the second chip 40 is electrically connected to the first redistribution layer 217 by using metal wires 620 .

[0140] As an example, the step of curing the chip bonding layer 710 may be performed before the wire bonding process of the second chip 40. Since the chip bonding layer 710 is cured by heating, it can play a stress buffering role during the wire bonding process and provide sufficient supporting force.

[0141] Next, see Fig. 27, proceed to step S50 to form a plastic encapsulation layer 720 covering the stacked first chip 30 and the second chip 40 and the first redistribution layer 217 .

[0142] As an example, a C-type molding machine is used to apply molding material on the stacked first chip 30 and the second chip 40, and the first redistribution layer 217; the molding material is melted and formed into a molding layer 720 by heating and / or pressurizing. In this embodiment, the molded molding layer 720 has a thickness of not less than 300 μm, for example, a thickness of 400 μm.

[0143] For example, the molding material includes, but is not limited to, resin-based materials, epoxy resins, liquid thermosetting epoxy resins, plastic compounds, polyamides, and any combination thereof.

[0144] Those skilled in the art will appreciate that the shape and size of the plastic encapsulation layer can be appropriately determined according to the overall coverage of the adapter board, the chip stack, and the interconnection therebetween, and no excessive limitation is made herein.

[0145] Next, step S60 is performed to thin the substrate 200 from the second main surface 200 b of the substrate until the metal pillar 216 in the blind hole 210 is exposed.

[0146] Specifically, in step S60, the substrate 200 is thinned from the second main surface 200b of the substrate using the plastic encapsulation layer 720 as a carrier.

[0147] Based on the above technical solution, after the plastic encapsulation layer is formed, the subsequent back-side process is performed using the plastic encapsulation layer as a carrier without the need to use temporary bonding technology, thus avoiding the bonding and debonding steps of the temporary carrier and simplifying the manufacturing process.

[0148] As an example, the step of thinning the substrate 200 includes: first, thinning the substrate by a predetermined thickness from the second main surface 200b of the substrate through a back thinning process so that the exposed surface of the substrate is not lower than the bottom surface of the blind hole; then, using a dry etching process to further thin the substrate 200 to expose the passivation layer at the bottom of the blind hole 210; and using a chemical mechanical polishing (CMP) process to remove the passivation layer at the bottom of the blind hole.

[0149] In this embodiment, Fig.28As shown, step S60 also includes: using a dry etching process to thin the substrate, depositing a protective film 213 on the second main surface of the substrate; using a chemical mechanical polishing (CMP) process to flatten the second main surface of the substrate 100 to remove the passivation layer at the bottom of the blind hole. Taking the substrate 100 as a silicon substrate as an example, during the CMP process, the surface of the substrate 200 is covered with a protective film 213, so as to prevent the metal pillar from being exposed during the CMP process and causing metal diffusion, thereby avoiding the above process from affecting the impedance of silicon.

[0150] Then, if Figure 29-30 As shown, step S70 is performed to form a second redistribution layer 219 on the second main surface 200 b of the substrate, and the second redistribution layer 219 is electrically connected to the metal pillar 216 .

[0151] As an example, Fig.30 As shown, after forming the second rewiring layer 219, the step of forming a metal bump 220 on the second rewiring layer 219 is also included. The metal bump 220 includes one of a gold-tin solder ball, a silver-tin solder ball, and a copper-tin solder ball. In this embodiment, the metal bump 220 is formed on the pad of the second rewiring layer by using the C4 process, and the steps include: first, a series of processes such as passivation, photolithography, masking, etching, and sputtering are performed on the pad of the second rewiring layer 219 to form an adhesion layer and a barrier layer of an under-bump metal layer (UBM); then, a solder bump is formed, such as Fig.30 As shown, the final three-dimensional packaging structure is thus manufactured, and the solder bumps can be formed into solder balls by using a high temperature reflow process. In other examples, the solder balls are formed by using a ball planting process.

[0152] Embodiment 2

[0153] The present invention further provides a three-dimensional packaging structure, which is preferably manufactured using the manufacturing method of the three-dimensional packaging structure of the above embodiment, and of course other methods may also be used.

[0154] See also Fig.30 The three-dimensional packaging structure includes: an adapter board, the adapter board has a first main surface and a second main surface relative to each other, a first redistribution layer 217 is arranged on the first main surface of the adapter board, and a second redistribution layer 219 is arranged on the second main surface of the adapter board. The adapter board includes at least one metal column 216 passing through its first main surface and the second main surface, and the metal column 216 is electrically coupled between the first redistribution layer 217 and the second redistribution layer 219.

[0155] As an example, the metal pillar 216 is configured to have an interconnection area through which current passes, and its shape includes but is not limited to: square, rectangular, circular, cylindrical, polygonal or similar shapes, and the side surface of the metal pillar 216 has a cylindrical or conical cross-section.

[0156] As mentioned above, the metal pillar 216 can be formed by a sintering process, and the metal pillar 216 includes a conductive network structure with a glass component as a network skeleton.

[0157] As an example, the material of the metal pillar 216 mainly consists of copper particles or includes copper particles, wherein the copper particles are adhered to form physical contact with the surrounding glass components.

[0158] In summary, the present invention provides a three-dimensional packaging structure and a manufacturing method thereof. Before forming the second rewiring layer, a first chip and a second chip are stacked on the first rewiring layer of the adapter board, the first chip is flip-chip soldered on the first rewiring layer, the second chip is electrically connected to the first rewiring layer by wire bonding, and the first rewiring layer can be used to electrically couple the first chip and the second chip, thereby realizing chip stacking packaging, without the need to achieve electrical connection between stacked chips through the TSV process on the chip, greatly reducing the process complexity of chip stacking packaging; then, a plastic sealing layer is formed on the first chip, the second chip and the first rewiring layer, and the bottom filling, wrapping and plastic sealing of multiple chips can be completed through a one-step plastic sealing process, significantly reducing the equipment and material costs; in addition, the present invention forms a metal connection column through a sintering process, effectively improving the efficiency of through-hole filling, and improving the yield of interconnection, avoiding the deposition of barrier layers and conductive layers, and a series of complex processes such as electroplating of metal layers, effectively reducing the process complexity and manufacturing costs. Therefore, the present invention effectively overcomes the various shortcomings of the prior art and has a high industrial utilization value.

[0159] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A method for manufacturing a three-dimensional packaging structure, characterized in that: The production method comprises: A substrate is provided, wherein the substrate has a first main surface and a second main surface opposite to each other, and the substrate includes a metal column formed through the first main surface of the substrate along a thickness direction thereof; forming a first redistribution layer on the first main surface of the substrate, wherein the first main surface of the first redistribution layer is electrically connected to the metal pillar; Flip-chip bonding a first chip on a second main surface of the first redistribution layer opposite to the first main surface; stacking a second chip on the first chip, the second chip being electrically connected to the first redistribution layer through wire bonding so that the second chip is electrically coupled to the first chip; A plastic packaging layer is formed by covering the stacked first chip and the second chip and the first redistribution layer; Thinning the second main surface of the substrate until the metal pillar in the blind hole is exposed; A second redistribution layer is formed on the second main surface of the substrate, and the second redistribution layer is electrically connected to the metal pillar.

2. The method for manufacturing a three-dimensional packaging structure according to claim 1, characterized in that: The second chip is attached to the first chip by using a chip bonding layer; after curing the chip bonding layer, the second chip is electrically connected to the first redistribution layer by using metal wires.

3. The method for manufacturing a three-dimensional packaging structure according to claim 1, characterized in that: The step of forming the metal pillar comprises: Providing a substrate, and etching at least one blind hole from a first main surface of the substrate along a thickness direction thereof; forming a passivation layer at least on the sidewall and bottom of the blind hole; The passivation layer is covered with a metal filling material and the blind hole is filled.

4. The method for manufacturing a three-dimensional packaging structure according to claim 3, characterized in that: The step of forming the metal pillar further includes: Applying a sintering precursor containing a metal into the blind hole, and mixing and filling the sintering precursor into the blind hole by shaking, wherein the sintering precursor is in powder form and mainly consists of metal powder and glass powder; Removing the sintering precursor covering the surface of the substrate; The sintering precursor is sintered under a protective atmosphere to form a metal column filling the blind hole.

5. The method for manufacturing a three-dimensional packaging structure according to claim 4, characterized in that: The content of the glass powder is in the range of 10% to 15%, the metal powder is mainly copper powder, and the content of the copper powder is in the range of 85% to 90%. The sintered metal column has a conductive network structure with the glass component around the copper particles as the network skeleton and physical contact between the copper particles.

6. The method for manufacturing a three-dimensional packaging structure according to claim 5, characterized in that: The particle size range of the metal powder is ≤500nm, and the particle size range of the glass powder is 0.8μm to 1.2μm.

7. The method for manufacturing a three-dimensional packaging structure according to claim 1, characterized in that: The first chip is flip-chip soldered onto the second main surface of the first redistribution layer by using a thermocompression bonding process, wherein the first redistribution layer comprises at least two layers of organic dielectric layers and metal wiring layers that are alternately arranged.

8. The method for manufacturing a three-dimensional packaging structure according to claim 1, characterized in that: The plastic encapsulation layer is used as a carrier to thin the substrate from the second main surface of the substrate until the metal column in the blind hole is exposed.

9. The method for manufacturing a three-dimensional packaging structure according to claim 8, characterized in that: The step of forming a second rewiring layer on the second main surface of the substrate includes: removing the passivation layer at the bottom of the blind hole by a chemical mechanical polishing process to expose the metal column; forming a second rewiring layer on the second main surface of the substrate, the second rewiring layer is electrically connected to the metal column exposed on the second main surface of the substrate; forming a metal bump on the side of the second rewiring layer away from the substrate.

10. A three-dimensional packaging structure, characterized in that: The three-dimensional packaging structure is manufactured based on the method for manufacturing a three-dimensional packaging structure according to any one of claims 1 to 9.

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