Semiconductor structure and forming method thereof

Abstract

The invention discloses a semiconductor structure and a forming method thereof, and the method comprises the steps: providing a substrate; forming a dielectric layer on the substrate; forming a contact hole in the dielectric layer; forming a barrier layer on the side wall and the bottom surface of the contact hole, wherein the barrier layer also covers the surface of the dielectric layer; forming a suppression layer, wherein the suppression layer is located on the surface of the barrier layer on the dielectric layer; forming a plug material layer in the contact hole, wherein the top surface of the plug material layer is higher than the top surface of the inhibition layer; and performing planarization processing on the plug material layer until the surface of the dielectric layer is exposed, and forming a contact plug in the contact hole. According to the forming method provided by the embodiment of the invention, the planarization processing difficulty of the plug material layer can be reduced, the planarization processing time is reduced, and the production efficiency is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor preparation, and in particular to a semiconductor structure and a forming method thereof. Background Art

[0002] In semiconductor devices, reducing RC delay (Resistance Capacitance Delay) can improve the performance of semiconductor devices. With the advancement of semiconductor process technology nodes, the integration of devices is getting higher and higher, and the critical dimension (CD) of devices is getting smaller and smaller. Accordingly, further reducing RC delay has become one of the important measures to improve the performance of semiconductor devices.

[0003] As the size of semiconductor devices continues to decrease, the critical dimensions of metal contacts and interconnect structures in the devices are also getting smaller and smaller. At present, in order to reduce RC delay, the material used for contact plugs is usually a metal material with a small resistance, such as cobalt or tungsten, so as to improve the performance of semiconductor devices.

[0004] However, the process of forming contact plugs in contact holes still needs to be improved. Summary of the invention

[0005] The technical problem solved by the present invention is to provide a semiconductor structure and a method for forming the same, which can simplify the planarization process in the process of forming a contact plug, reduce production time and improve production efficiency.

[0006] To solve the above technical problems, an embodiment of the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate; forming a dielectric layer on the substrate; forming a contact hole in the dielectric layer; forming a barrier layer on the sidewall and bottom surface of the contact hole, wherein the barrier layer also covers the surface of the dielectric layer; forming an inhibition layer, wherein the inhibition layer is located on the surface of the barrier layer on the dielectric layer; forming a plug material layer in the contact hole, wherein the top surface of the plug material layer is higher than the top surface of the inhibition layer; and flattening the plug material layer until the surface of the dielectric layer is exposed, thereby forming a contact plug in the contact hole.

[0007] Optionally, the method for forming an inhibition layer includes: forming a mask layer in the contact hole, the mask layer exposing the surface of the barrier layer on the dielectric layer; forming an inhibition layer on the surface of the barrier layer exposed by the mask layer; and removing the mask layer.

[0008] Optionally, the method for forming the mask layer includes: forming a mask material layer in the contact hole, wherein the mask material layer also covers the surface of the barrier layer on the dielectric layer; patterning the mask material layer, removing the mask material layer on the dielectric layer, and forming a mask layer.

[0009] Optionally, the material of the mask layer includes photoresist.

[0010] Optionally, the material of the inhibition layer includes silicon dioxide, silicon nitride or silicon oxynitride.

[0011] Optionally, the process of forming the inhibition layer includes a chemical vapor deposition process or an atomic layer deposition process.

[0012] Optionally, the inhibition layer has a thickness of 100 to 500 angstroms.

[0013] Optionally, the material of the barrier layer includes metal or metal nitride, the metal includes titanium or tantalum, and the metal nitride includes titanium nitride or tantalum nitride.

[0014] Optionally, the process of forming the barrier layer includes a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process.

[0015] Optionally, the material of the plug material layer includes tungsten.

[0016] Optionally, the process of forming the plug material layer includes a physical vapor deposition process or an atomic layer deposition process.

[0017] Optionally, the process for planarizing the plug material layer is a chemical mechanical polishing process, and the process parameters of the chemical mechanical polishing include: a polishing pressure of 1.5 to 3.5 psi, and a polishing rotation speed of 90 to 140 rpm.

[0018] Optionally, the method for planarizing the plug material layer includes: performing chemical mechanical grinding on the plug material layer until the top surface of the plug material layer is flush with the top surface of the inhibition layer; performing chemical mechanical grinding on the plug material layer, the inhibition layer and the barrier layer until the surface of the dielectric layer is exposed.

[0019] Optionally, the method further includes: forming a gate structure on the substrate, wherein the gate structure is located in the dielectric layer.

[0020] Optionally, the method further includes: forming source-drain doping regions, wherein the source-drain doping regions are located in the substrate on both sides of the gate structure.

[0021] Optionally, the contact hole includes a gate contact hole and a source-drain contact hole, the gate contact hole exposes a top surface of the gate structure, and the source-drain contact hole exposes a top surface of the source-drain doped region.

[0022] Correspondingly, an embodiment of the present invention also provides a semiconductor structure formed by the above method, comprising: a substrate; a dielectric layer, the dielectric layer being located on the substrate; a contact hole, the contact hole being located in the dielectric layer; a barrier layer, the barrier layer being located on the sidewall and bottom surface of the contact hole, the barrier layer also covering the surface of the dielectric layer; an inhibition layer, the inhibition layer being located on the surface of the barrier layer on the dielectric layer; and a plug material layer, the plug material layer being located in the contact hole, the top surface of the plug material layer being higher than the top surface of the inhibition layer.

[0023] Optionally, the material of the barrier layer includes metal or metal nitride, the metal includes titanium or tantalum, and the metal nitride includes titanium nitride or tantalum nitride.

[0024] Optionally, the material of the inhibition layer includes silicon dioxide, silicon nitride or silicon oxynitride.

[0025] Optionally, the inhibition layer has a thickness of 100 to 500 angstroms.

[0026] Optionally, the material of the plug material layer includes tungsten.

[0027] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0028] The formation method provided by the technical solution forms an inhibition layer on the surface of the barrier layer on the dielectric layer after forming the barrier layer and before forming the plug material layer. The inhibition layer can inhibit the nucleation growth of the plug material layer, thereby avoiding the regional growth of the plug material layer on the dielectric layer and limiting it to the contact hole area, thereby reducing the difficulty of subsequent planarization of the plug material layer, reducing the process time, and improving production efficiency.

[0029] The semiconductor structure provided by the technical solution has an inhibition layer on the surface of the barrier layer on the dielectric layer. The inhibition layer can inhibit the nucleation growth of the plug material layer, so that the plug material layer is located in the contact hole instead of growing in the non-contact hole area. When the plug material layer is subsequently planarized to form a contact plug, the planarization process can be simplified, production time can be saved, and production efficiency can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 is a schematic structural diagram of a semiconductor structure in one embodiment;

[0031] Figures 2 to 11It is a schematic structural diagram corresponding to each step in a semiconductor structure forming process in one embodiment of the present invention. DETAILED DESCRIPTION

[0032] As can be seen from the background art, the process of forming a contact plug in a contact hole still needs to be improved. The reason is now analyzed in conjunction with a semiconductor structure.

[0033] refer to Figure 1 , shows a semiconductor structure, the semiconductor structure comprising: a substrate 10; a gate structure 20, the gate structure 20 is located on the substrate 10; source-drain doped regions 30, the source-drain doped regions 30 are located in the substrate 10 on both sides of the gate structure 20; a dielectric layer 40, the dielectric layer 40 is located on the substrate 10, the dielectric layer 40 covers the gate structure 20 and the source-drain doped regions 30; a contact hole 50, the contact hole 50 is located in the dielectric layer 40, the bottom of the contact hole 50 exposes the top surface of the gate structure 20 and the top surface of the source-drain doped regions 30; a barrier layer 60, the barrier layer 60 is located on the sidewall and bottom surface of the contact hole 50, the barrier layer 60 also covers the top surface of the dielectric layer 40; a plug material layer 70, the plug material layer 70 fills the contact hole 50, and the plug material layer 70 is also located on the surface of the barrier layer 60.

[0034] At present, metal materials with low resistance, such as tungsten, are usually used as materials for forming contact plugs, and the barrier layer is usually made of materials with good stability, such as titanium or titanium nitride, to prevent the diffusion of metal tungsten. When the plug material layer is formed without the selective deposition method, tungsten is easy to nucleate on the surface of the barrier layer. Therefore, the formed plug material layer 70 not only covers the surface of the barrier layer 60 located on the dielectric layer 40 in the contact hole 50. When the plug material layer is subsequently planarized, the plug material layer 70 on the surface of the barrier layer 60 needs to be ground off, which is difficult to grind and takes a long time, which is not conducive to improving production efficiency.

[0035] In order to solve the above problems, an embodiment of the present invention provides a semiconductor structure and a method for forming the same. After a barrier layer is formed on the bottom and sidewall surfaces of a contact hole and a dielectric layer, an inhibition layer is formed on the surface of the barrier layer located on the dielectric layer. The formed plug material layer is not easy to grow on the inhibition layer, so the plug material layer is confined within the contact hole and prevented from growing in non-contact hole areas. When planarizing the plug material layer, only the plug material layer in the contact hole area needs to be ground, which reduces the process difficulty of the planarization process, saves process time, and improves production efficiency.

[0036] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0037] Figures 2 to 11 It is a schematic structural diagram corresponding to each step in a semiconductor structure forming process in one embodiment of the present invention.

[0038] refer to Figure 2 , providing a substrate 100, wherein the substrate 100 serves as a process basis for forming a semiconductor structure.

[0039] The material of the substrate 100 is at least one of the following materials: silicon, germanium, silicon germanium, silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI), etc. In this embodiment, the material of the substrate 100 is silicon.

[0040] refer to Figure 3 , a dielectric layer 101 and a gate structure 102 are formed on the substrate 100 , and the gate structure is located in the dielectric layer 101 .

[0041] In this embodiment, the dielectric layer 101 includes a first dielectric layer 103 and a second dielectric layer 104 . The gate structure 102 is located in the first dielectric layer 103 . The second dielectric layer 104 is located on the first dielectric layer 103 and covers the top surface of the gate structure 102 .

[0042] The material of the first dielectric layer 103 is an insulating dielectric material. In this embodiment, the material of the first dielectric layer 103 is silicon dioxide. In other embodiments, the material of the first dielectric layer 103 may also be silicon nitride or silicon oxynitride.

[0043] The material of the second dielectric layer 104 is an insulating dielectric material. In this embodiment, the material of the second dielectric layer 104 is silicon dioxide. In other embodiments, the material of the second dielectric layer 104 may also be silicon nitride or silicon oxynitride.

[0044] In this embodiment, the gate structure 102 includes a gate oxide layer 105 located on the substrate 100 and a gate layer 106 located on the gate oxide layer 105 .

[0045] In this embodiment, the material of the gate oxide layer 105 is silicon dioxide.

[0046] In this embodiment, the gate structure 102 is a metal gate structure, and the material of the gate layer 106 includes copper, aluminum or tungsten.

[0047] Specifically, the method for forming the dielectric layer 101 and the gate structure 102 includes: forming a gate oxide material layer (not shown) on the substrate 100; forming a dummy gate material layer (not shown) on the surface of the gate oxide material layer; graphically processing the dummy gate material layer and the gate oxide material layer to form a gate oxide layer 105 and a dummy gate layer (not shown); forming a first dielectric layer 103 on the substrate 100, wherein the first dielectric layer 103 exposes the top of the dummy gate layer; removing the dummy gate layer to form a gate groove in the first dielectric layer 103; forming a gate layer 106 in the gate groove; forming a second dielectric layer 104 on the first dielectric layer 103 and the top of the gate structure 102, wherein the first dielectric layer 103 and the second dielectric layer 104 constitute the dielectric layer 101.

[0048] In this embodiment, before forming the first dielectric layer 103 , a spacer 107 is formed on both sides of the dummy gate layer and the gate oxide layer 105 .

[0049] The material of the sidewall spacer 107 includes one or more of silicon nitride, silicon oxide and silicon oxynitride. In this embodiment, the material of the sidewall spacer 107 is silicon nitride.

[0050] In this embodiment, after forming the sidewall spacer 107 , the process further includes forming source-drain doped regions 108 in the substrate 100 on both sides of the dummy gate layer.

[0051] In this embodiment, the doping ions of the source / drain doping region 108 are N-type ions, such as P, As or Sb. In other embodiments, the doping ions of the source / drain doping region 108 may also be P-type ions, which may be determined according to the type of semiconductor device.

[0052] refer to Figure 4 , a contact hole is formed in the dielectric layer 101 .

[0053] In this embodiment, the contact holes include a gate contact hole 109 and a source-drain contact hole 110. The gate contact hole 109 exposes the top surface of the gate structure 102 for subsequent formation of a gate contact plug; the source-drain contact hole 110 exposes the top surface of the source-drain doped region 108 for subsequent formation of a source-drain contact plug.

[0054] The process steps for forming the gate contact hole 109 include: forming a first photoresist layer (not shown) on the dielectric layer 101, wherein the first photoresist layer defines the position and size of the gate contact hole 109 to be formed; using the first photoresist layer as a mask, etching the dielectric layer 101 to form a gate contact hole 109 penetrating the dielectric layer 101, and the bottom of the gate contact hole 109 exposes the surface of the gate structure 102; and removing the first photoresist layer.

[0055] The process steps for forming the source-drain contact hole 110 include: forming a second photoresist layer (not shown) on the dielectric layer 101, the second photoresist layer defining the position and size of the source-drain contact hole 110 to be formed; using the second photoresist layer as a mask, etching the dielectric layer 101 to form the source-drain contact hole 110 penetrating the dielectric layer 101, and the bottom of the source-drain contact hole 110 exposes the surface of the source-drain doped region 108; and removing the second photoresist layer.

[0056] refer to Figure 5 A barrier layer 111 is formed on the bottom and sidewall surfaces of the contact hole, and the barrier layer 111 also covers the surface of the dielectric layer 101 .

[0057] The material of the barrier layer 111 includes metal or metal nitride, the metal includes titanium or tantalum, and the metal nitride includes titanium nitride or tantalum nitride. In this embodiment, the material of the barrier layer 111 is titanium nitride.

[0058] In this embodiment, the method for forming the barrier layer 111 includes chemical vapor deposition; in other embodiments, the barrier layer may also be formed by physical vapor deposition or atomic layer deposition.

[0059] In this embodiment, the function of the blocking layer 111 is to prevent the subsequent conductive metal in the gate contact hole 109 and the source-drain contact hole 110 from diffusing into the dielectric layer 101. The blocking layer 111 located on the dielectric layer 102 can serve as a grinding stop layer for subsequent grinding of the conductive metal material.

[0060] After the barrier layer 111 is formed, an inhibition layer is formed on the surface of the barrier layer 111 located on the dielectric layer 101 .

[0061] Specific methods for forming the inhibition layer include, referring to Figure 6 , a mask material layer 112 is formed in the contact hole, and the mask material layer 112 also covers the surface of the barrier layer 111 on the dielectric layer 101 .

[0062] In this embodiment, the mask material layer 112 is used to subsequently form a mask layer, and the mask layer provides a mask for subsequently forming an inhibition layer.

[0063] In this embodiment, the mask material layer 112 is a photoresist layer, which can be easily removed by exposure and development without affecting other material layers.

[0064] refer to Figure 7 , patterning the mask material layer 112, removing the mask material layer 112 on the dielectric layer 101, and forming a mask layer 113 in the contact hole.

[0065] In this embodiment, the patterning process includes exposing and developing the mask material layer 112 ; in other embodiments, the mask material layer 112 on the dielectric layer 101 may also be removed by etching or other processes.

[0066] refer to Figure 8 , using the mask layer 113 as a mask, an inhibition layer 114 is formed on the barrier layer 111 . Since the mask layer 113 has filled the contact hole, the inhibition layer 114 is formed on the surface of the barrier layer 111 on the dielectric layer 101 .

[0067] In this embodiment, the material of the inhibition layer 114 is silicon dioxide; in other embodiments, the inhibition layer 114 may also be made of dielectric materials such as silicon nitride or silicon oxynitride.

[0068] Silicon dioxide, silicon nitride or silicon oxynitride is used as the inhibition layer 114 because most of the contact plugs are made of metal materials, including metal materials such as tungsten, and metal materials such as tungsten are non-affinity with dielectric materials such as silicon dioxide, and have a high nucleation barrier. Therefore, tungsten is difficult to adhere to the surface of these dielectric materials and is not easy to nucleate. It is difficult to form on the inhibition layer 114, so the formation of the plug material in the area outside the contact hole can be suppressed, and there is no need to grind and remove the plug material layer above the dielectric layer 101 later, which can reduce the process difficulty and process time, which is conducive to improving production efficiency.

[0069] The process of forming the inhibition layer 114 includes a chemical vapor deposition process or an atomic layer deposition process. In this embodiment, the inhibition layer 114 is formed by a chemical vapor deposition process.

[0070] The thickness of the inhibition layer 114 is in the range of 100 to 500 angstroms. The inhibition layer 114 has such a thickness range. On the one hand, it can isolate the barrier layer 111 from the plug material formed subsequently, so that the plug material will not be formed on the barrier layer 111. On the other hand, the thickness of the inhibition layer 114 cannot be too thick, so that the subsequent removal of the inhibition layer 114 itself is convenient.

[0071] refer to Fig. 9 After forming the inhibition layer 114, the mask layer 113 is removed.

[0072] In this embodiment, the mask layer 113 is removed by developing and exposing the mask layer 113 , and the suppression layer 114 will not be damaged during the removal.

[0073] refer to Fig.10 , a plug material layer 115 is filled in the contact hole, and a top surface of the plug material layer 115 is higher than a top surface of the inhibition layer 114 .

[0074] In this embodiment, the material of the plug material layer 115 is metal, and the metal is tungsten. In other embodiments, the material of the plug material layer 115 may also be aluminum, copper, platinum, cobalt, etc.

[0075] In the present embodiment, the material forming the contact plug is tungsten, and tungsten is more easily formed on a conductive material layer such as a metal or metal nitride. Therefore, an inhibition layer 114 is covered on the barrier layer 111 to prevent tungsten from being formed on the barrier layer 111. During the subsequent planarization process, only the higher tungsten layer needs to be ground off. Compared with grinding the tungsten layer from the barrier layer, the process difficulty is greatly reduced, the time required for the process is reduced, and the production efficiency is improved.

[0076] In this embodiment, the plug material layer 115 is filled by atomic layer deposition. In other embodiments, the plug material layer 115 may be filled by chemical vapor deposition, physical vapor deposition or electrochemical plating.

[0077] refer to Fig.11 , planarizing the plug material layer 115 until the top surface of the dielectric layer 101 is exposed, and forming a contact plug in the contact hole.

[0078] In this embodiment, a gate contact plug 116 is formed in the gate contact hole 109 , and a source-drain contact plug 117 is formed in the source-drain contact plug 110 .

[0079] In this embodiment, the process for planarizing the plug material layer 115 is a chemical mechanical polishing process, and the process parameters of the chemical mechanical polishing include: a polishing pressure of 1.5 to 3.5 psi, and a polishing speed of 90 to 140 rpm.

[0080] In this embodiment, due to the existence of the inhibition layer 114, the plug material layer 115 is only formed in the contact hole area, and is not formed on the barrier layer 111. When grinding the plug material layer 115, it is only necessary to grind the plug material layer 115 to a suitable height without grinding it off from the barrier layer 111, which can reduce the process difficulty and shorten the time for the planarization process.

[0081] In this embodiment, the step of planarizing the plug material layer 115 includes: performing chemical mechanical polishing on the plug material layer 115 until the top surface of the plug material layer 115 is flush with the top surface of the inhibition layer 114; and continuing to perform chemical mechanical polishing on the plug material layer 115, the inhibition layer 114 and the barrier layer 111 until the surface of the dielectric layer 101 is exposed.

[0082] Accordingly, an embodiment of the present invention further provides a semiconductor structure, referring to Fig.10The semiconductor structure includes: a substrate 100; a dielectric layer 101, wherein the dielectric layer 101 is located on the substrate 100; a contact hole, wherein the contact hole is located in the dielectric layer 101; a barrier layer 111, wherein the barrier layer 111 is located on the sidewall and bottom surface of the contact hole, and wherein the barrier layer 111 also covers the surface of the dielectric layer 101; an inhibition layer 114, wherein the inhibition layer 114 is located on the surface of the barrier layer 111 on the dielectric layer 101; and a plug material layer 115, wherein the plug material layer 115 is located in the contact hole, and wherein the top surface of the plug material layer 115 is higher than the top surface of the inhibition layer 114.

[0083] The material of the substrate 100 is at least one of the following materials: silicon, germanium, silicon germanium, silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI), etc. In this embodiment, the material of the substrate 100 is silicon.

[0084] In this embodiment, the present invention further includes: a gate structure 102 , which is located in the dielectric layer 101 .

[0085] In this embodiment, the dielectric layer 101 includes a first dielectric layer 103 and a second dielectric layer 104 . The gate structure 102 is located in the first dielectric layer 103 . The second dielectric layer 104 is located on the first dielectric layer 103 and covers the top surface of the gate structure 102 .

[0086] The material of the first dielectric layer 103 is an insulating dielectric material. In this embodiment, the material of the first dielectric layer 103 is silicon dioxide. In other embodiments, the material of the first dielectric layer 103 may also be silicon nitride or silicon oxynitride.

[0087] The material of the second dielectric layer 104 is an insulating dielectric material. In this embodiment, the material of the second dielectric layer 104 is silicon dioxide. In other embodiments, the material of the second dielectric layer 104 may also be silicon nitride or silicon oxynitride.

[0088] In this embodiment, the gate structure 102 includes a gate oxide layer 105 located on the substrate 100 and a gate layer 106 located on the gate oxide layer 105 .

[0089] In this embodiment, the material of the gate oxide layer 105 is silicon dioxide.

[0090] In this embodiment, the gate structure 102 is a metal gate structure, and the material of the gate layer 106 includes copper, aluminum or tungsten.

[0091] In this embodiment, the gate structure 102 further includes sidewall spacers 107 . The sidewall spacers 107 are located on two sides of the gate structure 102 .

[0092] In this embodiment, the gate structure 102 further includes: a source-drain doping region 108 , and the source-drain doping region 108 is located in the substrate 100 on both sides of the gate structure 102 .

[0093] In this embodiment, the contact hole includes a gate contact hole 109 (refer to Figure 4 ) and source-drain contact holes 110 (reference Figure 4 ), the gate contact hole 109 exposes the top surface of the gate structure 102, and the source-drain contact holes 110 expose the top surface of the source-drain doped region 108.

[0094] The material of the barrier layer 111 includes metal or metal nitride, the metal includes titanium or tantalum, and the metal nitride includes titanium nitride or tantalum nitride. In this embodiment, the material of the barrier layer 111 is titanium nitride.

[0095] In this embodiment, the material of the inhibition layer 114 is silicon dioxide; in other embodiments, the inhibition layer 114 may also be made of dielectric materials such as silicon nitride or silicon oxynitride.

[0096] The thickness of the inhibition layer 114 is in the range of 100 to 500 angstroms.

[0097] In this embodiment, the material of the plug material layer 115 is metal tungsten; in other embodiments, the material of the plug material layer 115 may also be aluminum, copper, platinum, cobalt, etc.

[0098] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: providing a substrate; forming a dielectric layer on the substrate; forming a contact hole in the dielectric layer; forming a barrier layer on the sidewall and bottom surface of the contact hole, wherein the barrier layer also covers the surface of the dielectric layer; forming an inhibition layer, wherein the inhibition layer is located on the surface of the barrier layer on the dielectric layer; forming a plug material layer in the contact hole, wherein a top surface of the plug material layer is higher than a top surface of the inhibition layer; The plug material layer is planarized until the surface of the dielectric layer is exposed, and a contact plug is formed in the contact hole.

2. The method for forming a semiconductor structure according to claim 1, wherein: Also includes: The method for forming the inhibition layer comprises: forming a mask layer in the contact hole, wherein the mask layer exposes the surface of the barrier layer on the dielectric layer; forming the inhibition layer on the surface of the barrier layer exposed by the mask layer; and removing the mask layer.

3. The method for forming a semiconductor structure according to claim 2, wherein: The method for forming the mask layer includes: forming a mask material layer in the contact hole, the mask material layer also covering the surface of the barrier layer on the dielectric layer; patterning the mask material layer, removing the mask material layer on the dielectric layer, and forming a mask layer.

4. The method for forming a semiconductor structure according to claim 1, wherein: The material of the inhibition layer includes silicon dioxide, silicon nitride or silicon oxynitride.

5. The method for forming a semiconductor structure according to claim 4, wherein: The process of forming the inhibition layer includes a chemical vapor deposition process or an atomic layer deposition process.

6. The method for forming a semiconductor structure according to claim 1, wherein: The thickness of the inhibition layer is 100 to 500 angstroms.

7. The method for forming a semiconductor structure according to claim 1, wherein: The material of the barrier layer includes metal or metal nitride, the metal includes titanium or tantalum, and the metal nitride includes titanium nitride or tantalum nitride.

8. The method for forming a semiconductor structure according to claim 7, wherein: The process of forming the barrier layer includes a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process.

9. The method for forming a semiconductor structure according to claim 1, wherein: The material of the plug material layer includes tungsten.

10. The method for forming a semiconductor structure according to claim 9, wherein: The process of forming the plug material layer includes a physical vapor deposition process or an atomic layer deposition process.

11. The method for forming a semiconductor structure according to claim 1, wherein: The process for planarizing the plug material layer is a chemical mechanical polishing process, and the process parameters of the chemical mechanical polishing include: a polishing pressure of 1.5 to 3.5 psi and a polishing speed of 90 to 140 rpm.

12. The method for forming a semiconductor structure according to claim 11, wherein: The method for planarizing the plug material layer includes: performing chemical mechanical grinding on the plug material layer until the top surface of the plug material layer is flush with the top surface of the inhibition layer; performing chemical mechanical grinding on the plug material layer, the inhibition layer and the barrier layer until the surface of the dielectric layer is exposed.

13. The method for forming a semiconductor structure according to claim 1, wherein: Also includes: A gate structure is formed on the substrate, and the gate structure is located in the dielectric layer.

14. The method for forming a semiconductor structure according to claim 13, wherein: Also includes: Source and drain doping regions are formed, and the source and drain doping regions are located in the substrate at both sides of the gate structure.

15. The method for forming a semiconductor structure according to claim 14, wherein: The contact holes include a gate contact hole and a source-drain contact hole. The gate contact hole exposes a top surface of the gate structure, and the source-drain contact hole exposes a top surface of the source-drain doped region.

16. A semiconductor structure, characterized in that: include: substrate; a dielectric layer, the dielectric layer being located on the substrate; A contact hole, wherein the contact hole is located in the dielectric layer; a barrier layer, the barrier layer being located on the sidewall and bottom surface of the contact hole, and the barrier layer also covering the surface of the dielectric layer; an inhibition layer, the inhibition layer being located on a surface of the barrier layer on the dielectric layer; A plug material layer is located in the contact hole, and a top surface of the plug material layer is higher than a top surface of the inhibition layer.

17. The semiconductor structure according to claim 16, wherein: The material of the barrier layer includes metal or metal nitride, the metal includes titanium or tantalum, and the metal nitride includes titanium nitride or tantalum nitride.

18. The semiconductor structure according to claim 16, wherein: The material of the inhibition layer includes silicon dioxide, silicon nitride or silicon oxynitride.

19. The semiconductor structure according to claim 16, wherein: The thickness of the inhibition layer is 100 to 500 angstroms.

20. The semiconductor structure according to claim 16, wherein: The material of the plug material layer includes tungsten.

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