Half-bridge circuit driving chip

Abstract

The invention relates to a half-bridge circuit driving chip, which comprises a control module for receiving an enable signal and an input signal and outputting a set signal and a reset signal; the level conversion unit is used for receiving the setting signal and the reset signal and outputting a relative setting signal and a relative reset signal; the programming module is used for decoding according to the relative set signal and the relative reset signal and outputting a circuit parameter when the enable signal is at a low level and is in a programming mode; and the driving unit is used for generating an output signal according to the relative set signal and the relative reset signal when the enable signal is at a high level and is in a working mode. The driving chip has the beneficial effect that the problem that an existing driving chip needs to be additionally electrically connected with programming and decoding elements can be solved.

Description

Technical Field

[0001] The present invention relates to the technical field of electronic components, and in particular to a half-bridge circuit driving chip capable of switching to a programming mode inside the chip and performing decoding and adjustment in a high-side circuit. Background Art

[0002] The half-bridge circuit is composed of a driver chip electrically connected to a high-side switch, a low-side switch and a power supply. The half-bridge circuit can receive an input signal through the driver chip and switch the high-side switch and the low-side switch to be on or off according to the signal level. The input signal can be a pulse width modulation (PWM) signal used to control the switch to alternately turn on the power supply. A square wave signal can be output at a load end electrically connected to the high-side switch and the low-side switch. The half-bridge circuit has the advantages of low cost and easy operation.

[0003] The above-mentioned existing half-bridge circuit can switch between high and low voltage values ​​at the load end. However, more complex operating functions, such as dead time control, undervoltage lockout, overcurrent protection, overtemperature protection and driver strength control, must be connected to the half-bridge circuit through additional electrical connections to perform decoding, adjustment and programming of circuit parameters, resulting in an increase in the number of components that need to be soldered on the driver chip, increased overall circuit energy consumption and complex control functions.

[0004] In view of this, the existing half-bridge circuit driver chip still needs to be improved. Summary of the invention

[0005] 1. Technical issues to be resolved

[0006] In view of the above-mentioned shortcomings and deficiencies of the prior art, the present invention provides a half-bridge circuit driver chip.

[0007] (II) Technical solution

[0008] In order to solve the above problems, in a first aspect, the present invention provides a half-bridge circuit driving chip, which can integrate the programming module into the chip.

[0009] In a second aspect, the present invention provides a half-bridge circuit driver chip that can reduce the number of pin soldering.

[0010] In a third aspect, the present invention provides a half-bridge circuit driver chip that can save chip energy consumption.

[0011] The quantifier "a" or "an" is used in the elements and components described throughout the present invention only for convenience of use and to provide a general meaning of the scope of the present invention; it should be interpreted in the present invention as including one or at least one, and the concept of a single one also includes plural cases, unless it is obvious that it means otherwise.

[0012] The half-bridge circuit driving chip of the present invention comprises: a control module, receiving an enable signal and an input signal, the control module outputting a set signal and a reset signal; a level conversion unit, coupled to the control module, the level conversion unit receiving the set signal and the reset signal, and outputting a relative set signal and a relative reset signal; a programming module, coupled to the level conversion unit, when the enable signal is at a low level, it is a programming mode, the programming module decodes according to the relative set signal and the relative reset signal, and outputs a circuit parameter, when the enable signal is at a high level, the circuit parameter remains unchanged; and a driving unit, coupled to the level conversion unit, when the enable signal is at a high level, it is a working mode, the driving unit generates an output signal according to the relative set signal and the relative reset signal, when the enable signal is at a low level, the output signal remains at a low level.

[0013] Accordingly, the half-bridge circuit driver chip of the present invention transmits the programming signal to the high-side circuit of the chip through the level conversion unit and integrates the programming module into the high-side circuit. By adjusting and programming the high-side circuit parameters, the working mode of switching the high-side switch and the programming mode of decoding and programming input signals can be respectively executed without using additional pins and electrically connecting external electronic components. It has the effects of reducing the number of pin welding, saving chip energy consumption and reducing the complexity of the half-bridge circuit.

[0014] The control module has a pulse control unit coupled to a setting unit and a reset unit respectively, and the pulse control unit generates a positive edge pulse signal and a negative edge pulse signal according to the input signal, and transmits them to the setting unit and the reset unit respectively. In this way, a pulse signal can be generated at the moment of high and low level conversion of the input signal, which has the effect of switching the switch.

[0015] The set unit receives the input signal, the enable signal and the positive edge pulse signal. When the enable signal is at a low level, the set signal output by the set unit is the input signal. When the enable signal is at a high level, the set signal is the positive edge pulse signal. The reset unit receives the enable signal and the negative edge pulse signal. When the enable signal is at a low level, the reset signal output by the reset unit maintains a high level. When the enable signal is at a high level, the set signal is the negative edge pulse signal. In this way, in the programming mode, decoding can be performed according to the pulse width or pulse number of the set signal, and in the working mode, the switch can be controlled according to the positive and negative pulse signals, which has the effect of switching decoding and switching.

[0016] The setting unit receives the positive edge pulse signal, and when the enable signal is at a high level or a low level, the setting signal output by the setting unit is the positive edge pulse signal; the reset unit receives the enable signal and the negative edge pulse signal, and when the enable signal is at a low level, the reset signal output by the reset unit maintains a high level, and when the enable signal is at a high level, the setting signal is the negative edge pulse signal. In this way, decoding can be performed according to the number of pulses of the setting signal in the programming mode, and the switch can be controlled according to the positive and negative pulse signals in the working mode, which has the effect of switching decoding and switching.

[0017] The set unit receives the enable signal and the positive edge pulse signal. When the enable signal is at a low level, the set signal output by the set unit maintains a low level. When the enable signal is at a high level, the set signal is the positive edge pulse signal. The reset unit receives the input signal, the enable signal and the negative edge pulse signal. When the enable signal is at a low level, the reset signal output by the reset unit is the input signal. When the enable signal is at a high level, the set signal is the negative edge pulse signal. In this way, in the programming mode, decoding can be performed according to the pulse width or pulse number of the reset signal, and in the working mode, the switch can be controlled according to the positive and negative pulse signals, which has the effect of switching decoding and switching.

[0018] The setting unit receives the enable signal and the positive edge pulse signal. When the enable signal is at a low level, the setting signal output by the setting unit maintains a low level. When the enable signal is at a high level, the setting signal is the positive edge pulse signal. The reset unit receives the negative edge pulse signal. When the enable signal is at a high level or a low level, the reset signal output by the reset unit is the negative edge pulse signal. In this way, decoding can be performed according to the number of pulses of the reset signal in the programming mode, and the switch can be controlled according to the positive and negative pulse signals in the working mode, which has the effect of switching decoding and switching.

[0019] Wherein, the control module further has a comparison unit, the comparison unit receives the enable signal and is coupled to the setting unit and the reset unit respectively, the comparison unit sets a high level and a low level for comparison with the enable signal, when the enable signal is between the low level and the high level, a comparison signal output by the comparison unit is a low level, when the enable signal is lower than the low level or higher than the high level, the comparison signal is a high level, and the setting unit or the reset unit receives the comparison signal. In this way, the comparison unit increases the comparison signal according to the level of the enable signal, which has the effect of increasing the switchable options of the circuit.

[0020] The pulse control unit receives the enable signal, and when the enable signal is at a low level, the pulse control unit stops outputting the positive edge pulse signal and the negative edge pulse signal. In this way, the level of the enable signal can control the pulse output of the circuit, which has the effect of increasing the circuit control function.

[0021] When the enable signal is lower than the low level, it is a rest mode, and the set signal output by the set unit and the reset signal output by the reset unit are both low level; when the enable signal is between the low level and the high level, it is the programming mode; when the enable signal is higher than the high level, it is the working mode. In this way, it is possible to switch between the three modes of programming, working and rest, which has the effect of improving the controllability of the driver chip.

[0022] The half-bridge circuit driver chip of the present invention further comprises a low-side driver unit, the low-side driver unit receives the enable signal and the comparison signal, when the comparison signal is at a high level, it is the working mode, the low-side driver unit outputs a low-side output signal according to the enable signal, when the comparison signal is at a low level, it is the programming mode, the low-side output signal maintains a low level. In this way, the low-side output signal can be additionally generated to control another low-side switch to turn on or off, which has the effect of increasing the circuit control function.

[0023] The programming module has a decoding unit and a preset unit coupled to the decoding unit, the decoding unit receives the relative reset signal and the relative set signal, the decoding unit decodes the signal according to the pulse width or the number of pulses and outputs it to the preset unit, and the preset unit outputs the circuit parameters. In this way, the data decoded by the decoding unit can correspond to the preset circuit parameters, and the circuit parameters can be time delay, voltage, current and other parameters used to adjust and program the circuit function, which has the function of driving the chip function.

[0024] Beneficial Effects

[0025] The half-bridge circuit driver chip provided by the present invention transmits the programming signal to the high-side circuit of the chip through the level conversion unit, and integrates the programming module into the high-side circuit. By adjusting and programming the high-side circuit parameters, the working mode of switching the high-side switch and the programming mode of decoding and programming input signals can be respectively executed without using additional pins and electrically connecting external electronic components. It has the effects of reducing the number of pin welding, saving chip energy consumption and reducing the complexity of the half-bridge circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 is a circuit diagram of a first embodiment of the present invention;

[0027] Figure 2 for Figure 1 A timing diagram of each signal provided in the embodiment;

[0028] Figure 3 is a circuit diagram of a second embodiment of the present invention;

[0029] Figure 4 for Figure 3 A timing diagram of each signal provided in the embodiment;

[0030] Figure 5 is a circuit diagram of a third embodiment of the present invention;

[0031] Figure 6 for Figure 5 A timing diagram of each signal provided in the embodiment;

[0032] Figure 7 is a circuit diagram of a fourth embodiment of the present invention;

[0033] Figure 8 for Figure 7 A timing diagram of each signal provided in the embodiment;

[0034] Fig. 9 is a circuit diagram of a fifth embodiment of the present invention;

[0035] Fig.10 for Fig. 9 A timing diagram of each signal provided in the embodiment;

[0036] Fig.11 is a circuit diagram of a sixth embodiment of the present invention;

[0037] Fig.12 for Fig.11 The timing diagram of each signal provided in the embodiment.

[0038] Description of Reference Numerals

[0039] 1: control module;

[0040] 11: Pulse control unit;

[0041] 12: setting unit;

[0042] 13: Reset unit;

[0043] 14: comparison unit;

[0044] 2: Level conversion unit;

[0045] 3: Programming module;

[0046] 31: decoding unit;

[0047] 32: preset unit;

[0048] 4: drive unit;

[0049] 5: low side drive unit;

[0050] E: enable signal;

[0051] I: input signal;

[0052] S: set signal;

[0053] R: reset signal;

[0054] S r: Relative position signal;

[0055] R r :Relative reset signal;

[0056] D: Circuit parameters;

[0057] O: output signal;

[0058] O L : Low side output signal;

[0059] P S : Positive edge pulse signal;

[0060] P F : Negative edge pulse signal;

[0061] C: programming mode;

[0062] W: working mode;

[0063] B: rest mode;

[0064] M: Comparison signal. DETAILED DESCRIPTION

[0065] In order to make the above and other purposes, features and advantages of the present invention more obvious and easy to understand, the preferred embodiments of the present invention are specifically cited below and described in detail with reference to the accompanying drawings; in addition, those marked with the same symbols in different drawings are regarded as the same and their descriptions are omitted.

[0066] Reference Figure 1 As shown, Figure 1The first embodiment of the half-bridge circuit driver chip of the present invention comprises a control module 1, a level conversion unit 2, a programming module 3 and a driving unit 4, wherein the control module 1 is coupled to the level conversion unit 2, and the level conversion unit 2 is coupled to the programming module 3 and the driving unit 4 respectively, and the control module 1 receives an enable signal E and an input signal I, so that the control module 1 outputs a set signal S and a reset signal R to the level conversion unit 2 respectively, and the level conversion unit 2 outputs a relative set signal S r and a relative reset signal R r , to the programming module 3 and the driving unit 4, and make the programming module 3 output a circuit parameter D, and the driving unit 4 output an output signal O.

[0067] The control module 1 has a pulse control unit 11, which can receive the input signal I and generate a positive edge pulse signal P according to the input signal I. S And a negative edge pulse signal P F Specifically, when the input signal I changes from a low level to a high level, the positive edge pulse signal P S When the input signal I changes from a high level to a low level, the negative edge pulse signal P F The pulse control unit 11 may also be coupled to a setting unit 12 and a reset unit 13, wherein the setting unit 12 outputs the setting signal S and the reset unit 13 outputs the reset signal R. In this embodiment, the setting unit 12 receives the input signal I, the enable signal E and the positive edge pulse signal P. S Please refer to FIG. 2, which is a timing diagram of the above-mentioned signals. When the enable signal E is at a low level, the set signal S output by the set unit 12 is the input signal I. When the enable signal E is at a high level, the set signal S is the positive edge pulse signal P. S The reset unit 13 receives the enable signal E and the negative edge pulse signal P F As shown in FIG. 2, when the enable signal E is at a low level, the reset signal R output by the reset unit 13 maintains a high level. When the enable signal E is at a high level, the set signal S is the negative edge pulse signal P. F .

[0068] The level conversion unit 2 receives the set signal S and the reset signal R, and swaps the high and low levels of the set signal S and the reset signal R to generate the relative set signal S. r and the relative reset signal Rr For example, as shown in FIG. 2, when the enable signal E is at a low level, the reset signal R maintains a high level, then the relative reset signal R r Keep it low.

[0069] The programming module 3 is used to execute a programming mode C. When the enable signal E is at a low level, the programming module 3 can be coupled to the level conversion unit 2 by a decoding unit 31 and receive the relative reset signal R at a low level. r and the relative setting signal S r The decoding unit 31 can be based on the relative setting signal S r The pulse width or the number of pulses of the input signal I included in the decoding unit 31 is decoded. In this embodiment, the decoding unit 31 is a single wire decoder. In addition, the decoding unit 31 is coupled to a preset unit 32. The preset unit 32 makes the data decoded by the decoding unit 31 correspond to the preset circuit parameter D. The circuit parameter D can be a parameter such as time delay, voltage, current, etc. for adjusting and programming circuit functions. The circuit parameter D can be used to drive the control function inside the chip and can also be used for circuits outside the chip. In addition, when the enable signal E is at a high level, the relative reset signal R r If the voltage level is not low, the programming module 3 stops programming, and the circuit parameter D remains unchanged.

[0070] The driving unit 4 is used to execute a working mode W. When the enable signal E is at a high level, the driving unit 4 can receive the relative reset signal R r and the relative setting signal S r , and the relative reset signal R r The negative edge pulse signal P is a high level and a low level interchangeable F , the relative setting signal S r The positive edge pulse signal P is a high-low level switching positive edge pulse signal S The driving unit 4 can be based on the relative reset signal R r and the relative setting signal S r Generate the output signal O, which is used to control a switch to turn on or off, such as Figure 2 As shown, in the relative setting signal S r When a pulse is formed, the output signal O switches from a low level to a high level, and the relative reset signal R rWhen a pulse is formed, the output signal O switches from a high level to a low level, and the driving unit 4 can output the output signal O having the same square wave as the input signal I in the working mode W. In addition, when the enable signal E is at a low level, the relative reset signal R r Maintaining a low level, the driving unit 4 is in a reset state, regardless of the input signal I or the relative setting signal S r No matter how it changes, the output signal O remains at a low level.

[0071] Reference Figure 3 and Figure 4 As shown, it is a second embodiment of the half-bridge circuit driving chip of the present invention and its signal timing diagram. This embodiment is substantially the same as the first embodiment described above. In this embodiment, the setting unit 12 only receives the positive edge pulse signal P S ,like Figure 4 As shown, when the enable signal E is at a high level or a low level, the setting signal S output by the setting unit 12 is the positive edge pulse signal P S When the enable signal E is at a low level, the program mode C is switched to the program mode C. The decoding unit 31 can r The positive edge pulse signal P included S The pulse number is decoded, and the driving unit 4 is in a reset state and the output signal O is maintained at a low level; when the enable signal E is at a high level, it is switched to the working mode W, and the driving unit 4 can be based on the relative reset signal R r and the relative setting signal S r The output signal O is generated, and the programming module 3 stops programming and the circuit parameter D remains unchanged.

[0072] Reference Figure 5 and Figure 6 As shown, it is a third embodiment of the half-bridge circuit driving chip of the present invention and its signal timing diagram. This embodiment is substantially the same as the first embodiment described above. In this embodiment, the setting unit 12 receives the enable signal E and the positive edge pulse signal P S ,like Figure 6 As shown, when the enable signal E is at a low level, the set signal S output by the set unit 12 maintains a low level, and when the enable signal E is at a high level, the set signal S is the positive edge pulse signal P S The reset unit 13 receives the input signal I, the enable signal E and the negative edge pulse signal P F ,like Figure 6As shown, when the enable signal E is at a low level, the reset signal R output by the reset unit 13 is the input signal I, and when the enable signal E is at a high level, the set signal S is the negative edge pulse signal P F When the enable signal E is at a low level, the program mode C is switched to the program mode C. The decoding unit 31 can r The negative edge pulse signal P F The pulse width or pulse number is decoded, and the driving unit 4 is in a reset state and the output signal O is maintained at a low level; when the enable signal E is at a high level, it is switched to the working mode W, and the driving unit 4 can be based on the relative reset signal R r and the relative setting signal S r The output signal O is generated, and the programming module 3 stops programming and the circuit parameter D remains unchanged.

[0073] Reference Figure 7 and Figure 8 As shown, it is a fourth embodiment of the half-bridge circuit driver chip of the present invention and its signal timing diagram. This embodiment is substantially the same as the first embodiment described above. In this embodiment, the setting unit 12 receives the enable signal E and the positive edge pulse signal P S ,like Figure 8 As shown, when the enable signal E is at a low level, the set signal S output by the set unit 12 maintains a low level, and when the enable signal E is at a high level, the set signal S is the positive edge pulse signal P S The reset unit 13 only receives the negative edge pulse signal P F ,like Figure 8 As shown, when the enable signal E is at a high level or a low level, the reset signal R output by the reset unit 13 is the negative edge pulse signal P F When the enable signal E is at a low level, the program mode C is switched to the program mode C. The decoding unit 31 can r The negative edge pulse signal P F The pulse number is decoded, and the driving unit 4 is in a reset state and the output signal O is maintained at a low level; when the enable signal E is at a high level, it is switched to the working mode W, and the driving unit 4 can be based on the relative reset signal R r and the relative setting signal S r The output signal O is generated, and the programming module 3 stops programming and the circuit parameter D remains unchanged.

[0074] Reference Fig. 9 and Fig.10As shown, it is the fifth embodiment of the half-bridge circuit driver chip of the present invention and its signal timing diagram. This embodiment is roughly the same as the first embodiment mentioned above. In this embodiment, the control module 1 further has a comparison unit 14. The comparison unit 14 receives the enable signal E and is coupled to the setting unit 12 and the reset unit 13 respectively. The comparison unit 14 can set a high level and a low level for comparison with the enable signal E. When the enable signal E is between the low level and the high level, the comparison signal M output by the comparison unit 14 is a low level; when the enable signal E is lower than the low level or higher than the high level, the comparison signal M is a high level. In addition, the pulse control unit 11 can receive the enable signal E. When the enable signal E is at a low level, the pulse control unit 11 stops outputting the positive edge pulse signal P S And the negative edge pulse signal P F In addition, the setting unit 12 receives the input signal I, the comparison signal M and the positive edge pulse signal P S The reset unit 13 receives the comparison signal M and the negative edge pulse signal P F .

[0075] like Fig.10 As shown, when the enable signal E is lower than the low level, the comparison signal M is at a high level, which is a dormant mode B. The set signal S output by the set unit 12 and the reset signal R output by the reset unit 13 are both at a low level, and the programming module 3 and the driving unit 4 will not be triggered. When the enable signal E is between the low level and the high level, it is the programming mode C, the comparison signal M is at a low level, the set signal S is the input signal I, and the reset signal R is at a high level. The decoding unit 31 can be based on the relative set signal S r The pulse width or pulse number of the input signal I is decoded, and the driving unit 4 is in a reset state and the output signal O is maintained at a low level; when the enable signal E is higher than the high level, the comparison signal M is at a high level, which is the working mode W, and the set signal S is the positive edge pulse signal P S , the reset signal R is the negative edge pulse signal P F The driving unit 4 can be based on the relative reset signal R r and the relative setting signal S r The output signal O is generated, and the programming module 3 stops programming and the circuit parameter D remains unchanged.

[0076] It is worth mentioning that the comparison unit 14 disclosed in the aforementioned fifth embodiment and the comparison signal M outputted therefrom can be used in the first to fourth embodiments, where the comparison signal M replaces the enable signal E inputted into the set unit 12 and / or the reset unit 13, and the enable signal E is received by the pulse control unit 11, so that the half-bridge circuit driver chip of the present invention can be switched to the sleep mode B in addition to the programming mode C and the working mode W. The aforementioned embodiments can be used individually or in combination according to usage requirements, and are not limited to the types disclosed in the drawings of each embodiment.

[0077] Reference Fig.11 and Fig.12 As shown, it is the sixth embodiment of the half-bridge circuit driver chip of the present invention and its signal timing diagram. This embodiment is roughly the same as the first embodiment mentioned above. In this embodiment, the control module 1 has the comparison unit 14, and the comparison unit 14 receives the enable signal E and is coupled to the setting unit 12, the reset unit 13 and a low-side drive unit 5 respectively. When the enable signal E is between the low level and the high level, the comparison unit 14 outputs the comparison signal M at a low level; when the enable signal E is lower than the low level or higher than the high level, the comparison signal M is at a high level. In addition, the setting unit 12 receives the input signal I, the comparison signal M and the positive edge pulse signal P S The reset unit 13 receives the comparison signal M and the negative edge pulse signal P F In addition, the low-side driving unit 5 receives the enable signal E and the comparison signal M.

[0078] like Fig.12 As shown, when the enable signal E is between the low level and the high level, it is the programming mode C, the comparison signal M is at a low level, the set signal S is the input signal I, and the reset signal R is at a high level. The decoding unit 31 can r The pulse width or pulse number of the input signal I is decoded, the driving unit 4 is in a reset state and the output signal O is maintained at a low level, and the low-side driving unit 5 is in a reset state and outputs a low-side output signal O L Maintain low level; when the enable signal E is lower than the low level or higher than the high level, the comparison signal M is high level, which is the working mode W, and the set signal S is the positive edge pulse signal P S , the reset signal R is the negative edge pulse signal P F The driving unit 4 can be based on the relative reset signal R r and the relative setting signal S rThe output signal O is generated, and the low-side driving unit 5 can generate the low-side output signal O according to the enable signal E L , and the programming module 3 stops programming and the circuit parameter D remains unchanged.

[0079] It is worth mentioning that the low-side driving unit 5, the comparison unit 14 and the comparison signal M outputted therefrom disclosed in the aforementioned sixth embodiment can be used in the first to fourth embodiments, and the comparison signal M is used to replace the enable signal E inputted to the setting unit 12 and / or the reset unit 13, and the low-side driving unit 5 receives the enable signal E and the comparison signal M, so that the half-bridge circuit driving chip of the present invention can also generate the low-side output signal O in the working mode W. L , used to control another low-side switch to turn on or off. The aforementioned embodiments can be used individually or in combination according to usage requirements, so they are not limited to the types disclosed in the drawings of each embodiment.

[0080] In summary, the half-bridge circuit driver chip of the present invention transmits the programming signal to the high-side circuit of the chip through the level conversion unit and integrates the programming module into the high-side circuit. It can adjust and program the high-side circuit parameters to execute the switching of the high-side switch working mode and the decoding and programming input signal programming mode respectively without the need to use additional pins and electrically connect external electronic components. It has the effects of reducing the number of pin welding, saving chip energy consumption and reducing the complexity of the half-bridge circuit.

[0081] Although the present invention has been disclosed using the above-mentioned preferred embodiments, they are not intended to limit the present invention. Those skilled in the art may make various changes and modifications to the above-mentioned embodiments without departing from the spirit and scope of the present invention, and these changes and modifications still fall within the technical scope protected by the present invention. Therefore, the scope of protection of the present invention shall be based on the definition of the claims.

Claims

1. A half-bridge circuit driver chip, characterized in that: include: A control module receives an enable signal and an input signal, and outputs a set signal and a reset signal; a level conversion unit, coupled to the control module, the level conversion unit receiving the set signal and the reset signal, and outputting a relative set signal and a relative reset signal; A programming module is coupled to the level conversion unit. When the enable signal is at a low level, it is a programming mode. The programming module decodes according to the relative set signal and the relative reset signal and outputs a circuit parameter. When the enable signal is at a high level, the circuit parameter remains unchanged. and A driving unit is coupled to the level conversion unit. When the enable signal is at a high level, it is a working mode. The driving unit generates an output signal according to the relative set signal and the relative reset signal. When the enable signal is at a low level, the output signal maintains a low level.

2. The half-bridge circuit driver chip according to claim 1, characterized in that: The control module has a pulse control unit which is coupled to a setting unit and a reset unit respectively. The pulse control unit generates a positive edge pulse signal and a negative edge pulse signal according to the input signal, and transmits them to the setting unit and the reset unit respectively.

3. The half-bridge circuit driver chip as claimed in claim 2, characterized in that: The set unit receives the input signal, the enable signal and the positive edge pulse signal. When the enable signal is at a low level, the set signal output by the set unit is the input signal. When the enable signal is at a high level, the set signal is the positive edge pulse signal. The reset unit receives the enable signal and the negative edge pulse signal. When the enable signal is at a low level, the reset signal output by the reset unit maintains a high level. When the enable signal is at a high level, the set signal is the negative edge pulse signal.

4. The half-bridge circuit driver chip according to claim 2, characterized in that: The set unit receives the positive edge pulse signal, and when the enable signal is at a high level or a low level, the set signal output by the set unit is the positive edge pulse signal; the reset unit receives the enable signal and the negative edge pulse signal, and when the enable signal is at a low level, the reset signal output by the reset unit maintains a high level, and when the enable signal is at a high level, the set signal is the negative edge pulse signal.

5. The half-bridge circuit driver chip as claimed in claim 2, characterized in that: The set unit receives the enable signal and the positive edge pulse signal. When the enable signal is at a low level, the set signal output by the set unit maintains a low level. When the enable signal is at a high level, the set signal is the positive edge pulse signal. The reset unit receives the input signal, the enable signal and the negative edge pulse signal. When the enable signal is at a low level, the reset signal output by the reset unit is the input signal. When the enable signal is at a high level, the set signal is the negative edge pulse signal.

6. The half-bridge circuit driver chip as claimed in claim 2, characterized in that: The set unit receives the enable signal and the positive edge pulse signal. When the enable signal is at a low level, the set signal output by the set unit maintains a low level. When the enable signal is at a high level, the set signal is the positive edge pulse signal. The reset unit receives the negative edge pulse signal. When the enable signal is at a high level or a low level, the reset signal output by the reset unit is the negative edge pulse signal.

7. The half-bridge circuit driver chip according to claim 2, characterized in that: The set unit receives the enable signal and the positive edge pulse signal. When the enable signal is at a low level, the set signal output by the set unit maintains a low level. When the enable signal is at a high level, the set signal is the positive edge pulse signal. The reset unit receives the negative edge pulse signal. When the enable signal is at a high level or a low level, the reset signal output by the reset unit is the negative edge pulse signal.

8. The half-bridge circuit driver chip according to claim 7, characterized in that: The pulse control unit receives the enable signal, and when the enable signal is at a low level, the pulse control unit stops outputting the positive edge pulse signal and the negative edge pulse signal.

9. The half-bridge circuit driver chip according to claim 8, characterized in that: When the enable signal is lower than the low level, it is a dormant mode, and the set signal output by the set unit and the reset signal output by the reset unit are both low levels; when the enable signal is between the low level and the high level, it is the programming mode; when the enable signal is higher than the high level, it is the working mode.

10. The half-bridge circuit driver chip according to claim 7, characterized in that: In addition, it includes a low-side driving unit, which receives the enable signal and the comparison signal. When the comparison signal is at a high level, it is the working mode, and the low-side driving unit outputs a low-side output signal according to the enable signal. When the comparison signal is at a low level, it is the programming mode, and the low-side output signal maintains a low level.

11. The half-bridge circuit driver chip according to claim 1, characterized in that: The programming module has a decoding unit and a preset unit coupled to the decoding unit. The decoding unit receives the relative reset signal and the relative set signal. The decoding unit decodes the signal according to the pulse width or the number of pulses and outputs it to the preset unit. The preset unit outputs the circuit parameters.

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