Rail-to-rail input high-speed comparator circuit

Abstract

The invention discloses a rail-to-rail input high-speed comparator circuit, which relates to the field of integrated circuits, and comprises a pre-amplifier circuit, a latch circuit, a Buck type level conversion circuit design and a multi-selection mode circuit, the multi-selection-mode circuit module comprises a comparator reverse input end mode selection circuit, a comparator speed mode selection circuit, a comparator output polarity selection circuit and a comparator hysteresis end selection circuit. The control selection of eight reverse input ends, the control selection of four comparator speeds, the control selection of two comparator output polarities and the control selection of four comparator hysteresis ends can be completed on one comparator circuit, so that the circuit can freely control the reverse input ends, the speeds, the output polarities and the hysteresis ends of the comparators.

Description

Technical Field

[0001] The invention belongs to the field of analog integrated circuit design and integrated system, in particular to a rail-to-rail input high-speed comparator circuit. Background Art

[0002] At present, A / D converters are widely used as interface components connecting analog and digital, and are widely used in radar, audio and video signal processing, image processing, sonar, communication and other fields. Today's A / D converters are developing towards low power consumption, high speed and high resolution. High-speed and low-power comparator circuits are suitable for A / D converters. They are a core module in A / D converters. They compare two analog signals to obtain digital signals 0 or 1. Its accuracy, speed and other indicators directly affect the overall performance of the entire analog-to-digital converter. Because of this, it is particularly important to realize a high-precision and fast comparator. Summary of the invention

[0003] The purpose of the present invention is to overcome the shortcomings of the prior art and provide a high-speed comparator circuit structure with rail-to-rail input, which can meet the urgent needs of applications in fields such as A / D converters. The development of the present invention can complete the control selection of eight reverse input terminals, four comparator speeds, two comparator output polarities, and four comparator hysteresis terminals on a comparator circuit, so that the circuit can freely control the reverse input terminal, speed, output polarity, and hysteresis terminal of the comparator. The present invention designs a high-speed comparator with rail-to-rail input and selectable speed for the A / D converter circuit. The rail-to-rail input structure of the comparator circuit can detect a differential mode level of about 2mV.

[0004] The technical solution adopted by the present invention to achieve the above-mentioned purpose is:

[0005] A rail-to-rail input high-speed comparator circuit, comprising:

[0006] The pre-amplifier circuit is used to amplify the differential voltage at the differential input terminal and output it to the latch circuit;

[0007] Latch circuit, used for latching the output voltage of the pre-amplifier circuit;

[0008] Buck type level conversion circuit, used to convert the 3.3V level output by the Latch latch circuit into 1.2V and output it;

[0009] The multi-selection mode circuit is used to control the comparator according to the input bias current.

[0010] The multi-select mode circuit comprises:

[0011] A comparator reverse input terminal mode selection circuit, used for controlling and selecting eight reverse input terminals, wherein the reverse input terminals are COMP_INM<3:0>, VREF14, VREF24, VREF34 and VREF;

[0012] A comparator speed mode selection circuit, used to control and select four comparator speeds through the port COMP_MODE<1:0>, wherein the comparator speeds are high speed, medium speed, low speed and ultra-low speed;

[0013] The comparator output polarity selection circuit is used to control the output polarity of the two comparators through the port POL_SEL;

[0014] The comparator hysteresis terminal selection circuit is used to control and select four comparator hysteresis terminals through the port COMP_HYST_SEL[3:0], where the comparator hysteresis terminals are no hysteresis, low hysteresis, medium hysteresis and high hysteresis.

[0015] The amplifier circuit includes: a differential pair of NMOS tubes M1 and M2, a differential pair of PMOS tubes M3 and M4, and MOS tubes M7 to M14, wherein:

[0016] The gates of M1 and M2 and the gates of M3 and M4 serve as the input terminals of the amplifier circuit, wherein the gates of M1 and M4 serve as the in-phase voltage input terminals, the gates of M2 and M3 serve as the inverting voltage input terminals, the gates of M11 and M12 serve as the output terminals of the amplifier circuit, the drains of M1 and M2 and the sources of M3, M4, M7 and M8 are all connected to the sources of M11 and M12, the sources of M1, M2, M9 and M10 and the drains of M3 and M4 are all connected to the sources of M11 and M12. They are all connected to the source of M13 and M14, the gates of M7 and M8 are connected and connected to the voltage Vbias1, the gates of M9 and M10 are connected and connected to the voltage Vbias2, the drains of M7 and M9 are all connected to the gate of M13, the drains of M8 and M10 are all connected to the gate of M14, the drains of M8 and M10 are all connected to the drain of M11, the drain of M13 is respectively connected to the gate and drain of M11, and the drain of M14 is respectively connected to the gate and drain of M12.

[0017] Each MOS tube differential pair in the amplifier circuit meets the following conditions:

[0018] (W / L)M1=(W / L)M2

[0019] (W / L)M3=(W / L)M4

[0020] Among them, W represents the groove width of the MOS tube, and L represents the groove length of the MOS tube.

[0021] The latch circuit includes: MOS tubes M15 to M20, wherein:

[0022] The gates of M15 and M16 serve together as the input end of the Latch latch circuit, the drain of M16 serves as the output end of the Latch latch circuit, the source of M15 is connected to the source of M16, the drain of M15 is connected to the drain of M17 and the gate of M19 respectively, the source of M17 is connected to the drain of M19, the gate of M17 is connected to the gate of M20, the gate of M19 is connected to the gate of M18, the source of M19 is connected to the source of M20, the drain of M16 is connected to the drain of M18 and the gate of M20 respectively, and the source of M18 is connected to the drain of M20.

[0023] The Buck type level conversion circuit includes: MOS tubes M21 to M27, wherein:

[0024] The gate of M21 serves as the input end of the Buck type level conversion circuit, the drain of M26 and the drain of M27 are connected to serve as the output end of the Buck type level conversion circuit, the drain of M21 is connected to the source of M23 and the source of M26 respectively, the source of M21 is connected to the drain of M22, the gate of M23 and the gate of M24 respectively, the gate of M22 is connected to the voltage Vbias1, the source of M22 is connected to the source of M25 and the source of M27 respectively, the drain of M23 is connected to the drain of M24, the gate of M26 and the gate of M27 respectively, and the source of M24 is connected to the gate and drain of M25 respectively.

[0025] The multi-selection mode circuit includes: MOS tubes M1a to M7a, wherein:

[0026] The drain of M1a serves as a bias current input terminal of the multi-selection mode circuit, the gate of M1a is connected to the drain of M1a and the gate of M2a respectively, the sources of M1a and M2a are grounded, the drain of M2a is connected to the gate and drain of M3a respectively, the gate of M3a is connected to the gate of M4a, the gate of M5a, the gate of M6a and the gate of M7a respectively, the source of M3a, the source of M4a, the source of M5a, the source of M6a and the source of M7a are all connected to a 3.3V voltage, the drain of M4a, the drain of M5a, the drain of M6a and the drain of M7a are respectively connected to a transmission gate control circuit, and the output terminal of the transmission gate control circuit serves as a bias current output terminal of the multi-selection mode circuit.

[0027] The transmission gate control circuit is composed of a pair of MOS transistors. Among them, the source of MOS1 is connected to the drain of MOS2, which jointly serves as the input end of the transmission gate control circuit. The gates of MOS1 and MOS2 respectively serve as the control input ends of the transmission gate control circuit. The drain of MOS1 and the source of MOS2 are connected and jointly serve as the output end of the transmission gate control circuit.

[0028] A method for implementing a rail-to-rail input high-speed comparator circuit includes the following steps:

[0029] The preamplifier circuit amplifies the differential voltages Vin+ and Vin- at the differential input end and outputs voltages V3 and V4 to the Latch latch circuit;

[0030] The Latch latch circuit latches the output voltages V3 and V4 of the preamplifier circuit. When V3 increases and V4 decreases, the output V5 voltage of the Latch latch circuit decreases; when V3 decreases and V4 increases, the output V5 voltage of the Latch latch circuit increases, and V5 is output to the Buck type level conversion circuit;

[0031] The Buck type level conversion circuit converts the 3.3V level V5 output by the Latch latch circuit into 1.2V and outputs it;

[0032] The multi-selection mode circuit controls and selects the comparator according to the input bias current.

[0033] The multi-selection mode circuit performs the following steps:

[0034] The comparator inverting input terminal mode selection circuit makes eight kinds of control selections for the inverting input terminals, and the inverting input terminals are respectively COMP_INM<3:0>, VREF14, VREF24, VREF34, and VREF;

[0035] The comparator speed mode selection circuit makes four kinds of control selections for the comparator speed through the port COMP_MODE<1:0>, and the comparator speeds are respectively high speed, medium speed, low speed, and ultra-low speed;

[0036] The comparator output polarity selection circuit makes two kinds of control selections for the comparator output polarity through the port POL_SEL. When POL_SEL is at a high level, when INP>INM, the output is at a high level, and when INP<INM, the output is at a low level;

[0037] The comparator hysteresis terminal selection circuit makes four kinds of control selections for the comparator hysteresis terminal through the port COMP_HYST_SEL[3:0], and the comparator hysteresis terminals are respectively no hysteresis, low hysteresis, medium hysteresis, and high hysteresis.

[0038] The present invention has the following beneficial effects and advantages:

[0039] 1. The present invention improves the problem of excessive delay caused when converting from 3.3V to 1.2V.

[0040] 2. The present invention can freely control the selection of eight reverse input terminals.

[0041] 3. The present invention can freely control the selection of the hysteresis ends of the four comparators. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Figure 1 A schematic diagram of the structure of a high-speed comparator circuit with rail-to-rail input according to the present invention;

[0043] Figure 2 is a circuit diagram of a preamplifier circuit;

[0044] Figure 3 is a circuit diagram of a latch circuit;

[0045] Figure 4 The circuit diagram of the Buck type level conversion circuit from 3.3V to 1.2V;

[0046] Figure 5 A circuit diagram of a comparator speed mode selection circuit;

[0047] Figure 6 Delay simulation result diagram when ultra-high speed mode is selected among the four speed modes for the comparator;

[0048] Figure 7 A graph of hysteresis simulation results when No Hysteresis mode is selected among the four hysteresis modes for the comparator. DETAILED DESCRIPTION

[0049] The present invention is further described in detail below in conjunction with the accompanying drawings and embodiments.

[0050] like Figure 1 As shown, the present invention discloses a high-speed comparator circuit structure with rail-to-rail input. The comparator adopts a rail-to-rail input structure, and a two-stage differential amplifier forms a pre-amplifier of the high-speed comparator. The back end is sent to a latch circuit to obtain a comparison result, which reduces the delay of the comparator and improves the speed of the comparator.

[0051] The invention comprises: a preamplifier circuit, a latch circuit, a multi-selection mode circuit, a comparator reverse input end mode selection circuit, a comparator speed mode selection circuit, a comparator output polarity selection circuit, and a comparator hysteresis end selection circuit.

[0052] The pre-amplifier circuit is divided into a first-stage pre-amplifier circuit and a second-stage pre-amplifier circuit.

[0053] in:

[0054] The first stage preamplifier uses a double folded cascode op amp with a rail-to-rail input structure to achieve a wide common-mode input range while increasing output impedance and gain. The second stage preamplifier uses a simple differential input structure.

[0055] The Latch latch circuit, wherein:

[0056] The input voltage of the latch circuit comes from the output of the pre-amplifier circuit, and a positive feedback structure is adopted to speed up the flipping speed of the first stage.

[0057] The comparator Buck type level conversion circuit is designed, wherein:

[0058] The Buck type level conversion circuit realizes the level conversion from 3.3V to 1.2V, further speeds up the reversal speed of the second stage, reduces the delay, and realizes the requirements of the high-speed comparator.

[0059] The multi-select mode circuit, wherein:

[0060] The multi-selection mode circuit module includes a comparator reverse input terminal mode selection circuit, a comparator speed mode selection circuit, a comparator output polarity selection circuit, and a comparator hysteresis terminal selection circuit.

[0061] The comparator negative input terminal mode selection circuit, wherein:

[0062] Eight kinds of reverse input terminal control selection can be completed on a comparator circuit, so that the circuit can freely control the reverse input terminal of the comparator. The reverse input terminals are COMP_INM<3:0>, VREF14, VREF24, VREF34, and VREF.

[0063] The comparator speed mode selection circuit, wherein:

[0064] Four comparator speed control options can be completed on a comparator circuit, so that the circuit can freely control the speed of the comparator. The comparator speeds are high speed, medium speed, low speed, and ultra-low speed. A 2-4 decoder is used to provide four comparator speed control options, and the control signal is COMP_MODE<1:0>.

[0065] Comparator output polarity selection circuit, where:

[0066] The control selection of two comparator output polarities can be completed on a comparator circuit, enabling the circuit to freely control the output polarity of the comparator. The control signal is POL_SEL, which is the output polarity selection port of the comparator. When POL_SEL is at a high level, when INP > INM, the output is high; when INP < INM, the output is low.

[0067] The comparator hysteresis terminal selection circuit, where:

[0068] The control selection of four comparator hysteresis terminals can be completed on a comparator circuit, enabling the circuit to freely control the hysteresis terminals of the comparator. The comparator hysteresis terminals are respectively no hysteresis, low hysteresis, medium hysteresis, and high hysteresis. COMP_HYST_SEL[3:0] is the comparator hysteresis terminal selection port.

[0069] As Figure 2 shown, the first-stage preamplifier uses a rail-to-rail input structure dual-folded cascode operational amplifier to achieve a wide common-mode input range while increasing the output impedance and improving the gain. The second-stage preamplifier uses a simple differential input structure. Among them, M1 and M2 are an N-type differential pair, and M3 and M4 are a P-type differential pair. Among them, (W / L)M1 = (W / L)M2, (W / L)M3 = (W / L)M4, (W / L)M7 = (W / L)M8, (W / L)M9 = (W / L)M 10 , (W / L)M 13 = (W / L)M 14 , (W / L)M 11 = (W / L)M 12 . In order to improve the speed of the comparator, M 11 and M 12 here use small-sized transistors to improve the conversion rate.

[0070] When V IN+ is 2 mV higher than V IN- , the current flowing into M1 from the tail current source is higher than the current flowing into M2, the source voltage of M7 decreases, the voltage of V2 decreases, and the voltage of V3 increases; the current flowing into M3 from the tail current source is higher than the current flowing into M4, the source voltage of M 10 increases, the voltage of V1 increases, and the voltage of V4 decreases. Similarly, when V IN+ is 2 mV lower than V IN- , the current flowing into M2 from the tail current source is higher than the current flowing into M1, the source voltage of M8 decreases, the voltage of V1 decreases, and the voltage of V4 increases; the current flowing into M4 from the tail current source is higher than the current flowing into M3, the source voltage of M9 increases, the voltage of V2 increases, and the voltage of V3 decreases.

[0071] As Figure 3As shown in the figure, the input voltages V4 and V3 of the latch circuit come from the output of the pre-amplifier circuit. Through the analysis of the pre-amplifier circuit above, it is found that when V IN+ V IN- When it is 2mV higher, the voltage of V3 increases, the voltage of V4 decreases, and therefore the voltage of V5 decreases. IN+ V IN- When it is 2mV lower, the voltage of V4 increases, the voltage of V3 decreases, so the voltage of V5 increases. 15 、M 17 、M 19 The input V4 of the common source amplifier is connected to the 16 、M 18 、M 20 The output V5 of the common-source amplifier constitutes positive feedback, accelerating the flipping speed of V5.

[0072] Note that the power supply voltage in the preamplifier circuit and the latch circuit is 3.3V. The next level of the output of the latch circuit needs to be connected to a low-voltage circuit with a power domain of 1.2V, and a high-voltage to low-voltage level conversion circuit is required. At the same time, considering the requirements of high-speed comparators for speed and layout area, the high-voltage to low-voltage level conversion circuit needs to have a small transmission delay and a small layout area.

[0073] like Figure 4 As shown in the figure, the voltage of V5 comes from the latch circuit, and the power domain of the latch circuit is 3.3V. If the first stage of the 3.3V to 1.2V level conversion circuit uses a 1.2V tube, there is a risk of gate source breakdown, so a 3.3V tube is needed. The energy of 3.3V is too high compared to 1.2V. When the signal V5 turns from high to low, it needs to be reduced to below the conduction threshold of the next stage N tube, and the next stage will flip, resulting in excessive delay. Therefore, in the first stage, the M 23 、M 24 、M 25 The level conversion circuit is composed of a M 21 、M 22 The source follower circuit formed by V5 is reduced by one V GS The voltage is V O1 Input to the second stage to get V O2 The input is sent to the next stage and then shaped into a waveform through an inverter composed of a 1.2V tube.

[0074] Among them, M 25 To improve M 24 The conduction threshold of the second stage is further accelerated, the reversal speed is reduced, and the delay is reduced, thus achieving the requirements of a high-speed comparator.

[0075] like Figure 5As shown, Ibias is the bias current input, 00 / 01 / 10 / 11 / 00N / 01N / 10N / 11N is the transmission gate control input, and Ibias1 is the bias current output. Four bias currents are provided through the current mirror, and each bias current has a set of transmission gate controls. The switch of the transmission gate is controlled by the 2-4 decoder. They correspond to high speed, full power consumption (00 and 00N); medium speed, medium power consumption (01 and 01N); low speed, low power consumption (10 and 10N); ultra-low speed, ultra-low power consumption (11 and 11N).

[0076] refer to Figure 6 , INM0 is the inverting input terminal of the comparator, INP0 is the non-inverting input terminal of the comparator, and OUT represents the transmission delay under 100mV overdrive voltage.

[0077] refer to Figure 7 , OUT indicates that the comparator's non-inverting input is flipped when it is about 0.5mV higher than the comparator's inverting input, and the hysteresis is about 1mV.

[0078] The specific embodiments described above further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A high-speed comparator circuit with rail-to-rail input, characterized in that: include: The pre-amplifier circuit is used to amplify the differential voltage at the differential input terminal and output it to the latch circuit; Latch circuit, used for latching the output voltage of the pre-amplifier circuit; Buck type level conversion circuit, used to convert the 3.3V level output by the Latch latch circuit into 1.2V and output it; The multi-selection mode circuit is used to control the selection of the comparator according to the input bias current.

2. A rail-to-rail input high-speed comparator circuit according to claim 1, characterized in that: The multi-select mode circuit comprises: A comparator reverse input terminal mode selection circuit, used for controlling and selecting eight reverse input terminals, wherein the reverse input terminals are COMP_INM<3:0>, VREF14, VREF24, VREF34 and VREF; A comparator speed mode selection circuit, used to control and select four comparator speeds through the port COMP_MODE<1:0>, wherein the comparator speeds are high speed, medium speed, low speed and ultra-low speed; The comparator output polarity selection circuit is used to control the output polarity of the two comparators through the port POL_SEL; The comparator hysteresis terminal selection circuit is used to control and select four comparator hysteresis terminals through the port COMP_HYST_SEL[3:0], where the comparator hysteresis terminals are no hysteresis, low hysteresis, medium hysteresis and high hysteresis.

3. The rail-to-rail input high-speed comparator circuit according to claim 1, characterized in that: The amplifier circuit includes: a differential pair of NMOS tubes M1 and M2, a differential pair of PMOS tubes M3 and M4, and MOS tubes M7 to M14, wherein: The gates of M1 and M2 and the gates of M3 and M4 serve as the input terminals of the amplifier circuit, wherein the gates of M1 and M4 serve as the in-phase voltage input terminals, the gates of M2 and M3 serve as the inverting voltage input terminals, the gates of M11 and M12 serve as the output terminals of the amplifier circuit, the drains of M1 and M2 and the sources of M3, M4, M7 and M8 are all connected to the sources of M11 and M12, the sources of M1, M2, M9 and M10 and the drains of M3 and M4 are all connected to the sources of M11 and M12. They are all connected to the source of M13 and M14, the gates of M7 and M8 are connected and connected to the voltage Vbias1, the gates of M9 and M10 are connected and connected to the voltage Vbias2, the drains of M7 and M9 are all connected to the gate of M13, the drains of M8 and M10 are all connected to the gate of M14, the drains of M8 and M10 are all connected to the drain of M11, the drain of M13 is respectively connected to the gate and drain of M11, and the drain of M14 is respectively connected to the gate and drain of M12.

4. The rail-to-rail input high-speed comparator circuit according to claim 3, characterized in that: Each MOS tube differential pair in the amplifier circuit meets the following conditions: (W / L)M1=(W / L)M2 (W / L)M3=(W / L)M4 Among them, W represents the groove width of the MOS tube, and L represents the groove length of the MOS tube.

5. The rail-to-rail input high-speed comparator circuit according to claim 1, characterized in that: The latch circuit includes: MOS tubes M15 to M20, wherein: The gates of M15 and M16 serve together as the input end of the Latch latch circuit, the drain of M16 serves as the output end of the Latch latch circuit, the source of M15 is connected to the source of M16, the drain of M15 is connected to the drain of M17 and the gate of M19 respectively, the source of M17 is connected to the drain of M19, the gate of M17 is connected to the gate of M20, the gate of M19 is connected to the gate of M18, the source of M19 is connected to the source of M20, the drain of M16 is connected to the drain of M18 and the gate of M20 respectively, and the source of M18 is connected to the drain of M20.

6. The rail-to-rail input high-speed comparator circuit according to claim 1, characterized in that: The Buck type level conversion circuit includes: MOS tubes M21 to M27, wherein: The gate of M21 serves as the input end of the Buck type level conversion circuit, the drain of M26 and the drain of M27 are connected to serve as the output end of the Buck type level conversion circuit, the drain of M21 is connected to the source of M23 and the source of M26 respectively, the source of M21 is connected to the drain of M22, the gate of M23 and the gate of M24 respectively, the gate of M22 is connected to the voltage Vbias1, the source of M22 is connected to the source of M25 and the source of M27 respectively, the drain of M23 is connected to the drain of M24, the gate of M26 and the gate of M27 respectively, and the source of M24 is connected to the gate and drain of M25 respectively.

7. The rail-to-rail input high-speed comparator circuit according to claim 1, characterized in that: The multi-selection mode circuit includes: MOS tubes M1a to M7a, wherein: The drain of M1a serves as a bias current input terminal of the multi-selection mode circuit, the gate of M1a is connected to the drain of M1a and the gate of M2a respectively, the sources of M1a and M2a are grounded, the drain of M2a is connected to the gate and drain of M3a respectively, the gate of M3a is connected to the gate of M4a, the gate of M5a, the gate of M6a and the gate of M7a respectively, the source of M3a, the source of M4a, the source of M5a, the source of M6a and the source of M7a are all connected to a 3.3V voltage, the drain of M4a, the drain of M5a, the drain of M6a and the drain of M7a are respectively connected to a transmission gate control circuit, and the output terminal of the transmission gate control circuit serves as a bias current output terminal of the multi-selection mode circuit.

8. The rail-to-rail input high-speed comparator circuit according to claim 7, characterized in that: The transmission gate control circuit is composed of a pair of MOS tubes, wherein the source of MOS1 is connected to the drain of MOS2 and serves as the input end of the transmission gate control circuit, the gate of MOS1 and the gate of MOS2 serve as the control input end of the transmission gate control circuit respectively, and the drain of MOS1 and the source of MOS2 are connected and serve as the output end of the transmission gate control circuit.

9. A method for implementing a rail-to-rail input high-speed comparator circuit, characterized in that: The following steps are involved: The pre-amplifier circuit amplifies the differential voltages Vin+ and Vin- at the differential input terminals, and outputs voltages V3 and V4 to the latch circuit; The latch circuit latches the output voltages V3 and V4 of the pre-amplifier circuit. When V3 increases and V4 decreases, the output voltage V5 of the latch circuit decreases; when V3 decreases and V4 increases, the output voltage V5 of the latch circuit increases, and V5 is output to the Buck type level conversion circuit. The Buck - type level - conversion circuit converts the 3.3V level V5 output by the Latch latch circuit into 1.2V and outputs it. The multi - selection mode circuit controls and selects the comparator according to the input bias current.

10. The method for implementing a rail-to-rail input high-speed comparator circuit according to claim 9, characterized in that: The multi - selection mode circuit performs the following steps: The comparator inverting - input terminal mode - selection circuit controls and selects eight inverting - input terminals, which are COMP_INM<3:0>, VREF14, VREF24, VREF34, and VREF respectively. The comparator speed mode - selection circuit controls and selects four comparator speeds through the port COMP_MODE<1:0>, and the comparator speeds are high speed, medium speed, low speed, and ultra - low speed respectively. The comparator output - polarity selection circuit controls and selects two comparator output polarities through the port POL_SEL. When POL_SEL is at a high level, when INP>INM, the output is at a high level, and when INP<INM, the output is at a low level. The comparator hysteresis - terminal selection circuit controls and selects four comparator hysteresis - terminals through the port COMP_HYST_SEL[3:0], and the comparator hysteresis - terminals are no hysteresis, low hysteresis, medium hysteresis, and high hysteresis respectively.

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