Link detection method, device, equipment and medium

Abstract

The invention relates to a link detection method, device, equipment and medium, a first converter receives a start enable signal sent by a master controller, generates a start enable packet according to the start enable signal, and outputs the start enable packet and first test data, and a second converter receives the start enable packet and the first test data, and outputs the start enable packet and the first test data to the master controller. When the first converter is a deserializer, starting is carried out according to the starting enabling packet, a detection result of the first link is obtained according to the first test data, second test data is output, the first converter receives the second test data, and a detection result of the second link is obtained according to the second test data. When the first converter is a deserializer, the master control can initiate an enable signal to the deserializer to trigger built-in self-inspection of the deserializer, and when the first converter is a serializer, the master control can also initiate an enable signal to the serializer to trigger built-in self-inspection of the serializer, so that the built-in self-inspection is not only suitable for an application scene that the master control is on one side of the deserializer, but also suitable for an application scene that the master control is on one side of the serializer.

Description

Technical Field

[0001] The present application belongs to the field of data processing technology, and in particular, relates to a link detection method, device, equipment and medium. Background Art

[0002] During prototype verification, product production, system internal testing, and system diagnosis, the connectivity of the link between the serializer and deserializer needs to be functionally tested. The link is generally tested using the built-in self-test (BIST) detection technology.

[0003] In the prior art, the master controller is generally set on the deserializer side. The master controller can only send an enable signal to the deserializer to trigger the deserializer to start the built-in self-test, resulting in the built-in self-test being only applicable to the application scenario where the master controller is on the deserializer side, and is not applicable to the application scenario where the master controller is on the serializer side. Summary of the invention

[0004] The purpose of the present application is to provide a link detection method, apparatus, equipment and medium; the link detection method, apparatus, equipment and medium provided by the present application, when the first converter is a deserializer, the master control can initiate an enable signal to the deserializer to trigger the deserializer to start a built-in self-test, and when the first converter is a serializer, the master control can also initiate an enable signal to the serializer to trigger the serializer to start a built-in self-test, so that the built-in self-test is not only applicable to the application scenario where the master control is on the deserializer side, but also applicable to the application scenario where the master control is on the serializer side.

[0005] The technical solutions provided by this application are as follows: A link detection method, the method comprising: The first converter receives the enable signal sent by the master, generates an enable packet according to the enable signal, and outputs the enable packet and the first test data; The second converter receives the enable packet and the first test data, starts according to the enable packet and obtains a detection result of the first link between the first converter and the second converter according to the first test data, and outputs second test data, wherein the first converter is a serializer or a deserializer, and the second converter is a deserializer or a serializer corresponding to the first converter; The first converter receives the second test data, and obtains a detection result of a second link between the first converter and the second converter according to the second test data.

[0006] Optionally, the method further comprises: The first converter receives a shutdown enable signal sent by the master control, stops sending the first test data according to the shutdown enable signal, and generates and outputs a shutdown enable packet; The second converter receives the shutdown enable packet and stops sending the second test data according to the shutdown enable packet.

[0007] Optionally, the method further comprises: The first converter sends a first test data packet having a required sending duration of a second preset duration within a first preset duration; receiving a first feedback signal sent by the second converter according to the received first test data packet, and adjusting the first preset duration and / or the second preset duration according to the first feedback signal, so that the adjusted sending rate is less than and close to the theoretical maximum bandwidth rate of the first link; The actual maximum bandwidth rate of the first link is obtained according to the adjusted first preset duration and the second preset duration.

[0008] Optionally, the method further comprises: The second converter sends a second test data packet having a required sending duration of a fourth preset duration within a third preset duration; receiving a second feedback signal sent by the first converter according to the received second test data packet, and adjusting the third preset duration and / or the fourth preset duration according to the second feedback signal, so that the adjusted sending rate is less than and close to the theoretical maximum bandwidth rate of the second link; The actual maximum bandwidth rate of the second link is obtained according to the adjusted third preset time length and fourth preset time length.

[0009] The present application also provides a link detection device, the link detection device comprising a first converter and a second converter, wherein: The first converter is used to receive the enable signal sent by the master, generate an enable packet according to the enable signal, and output the enable packet and the first test data; The second converter is used to receive the enable packet and the first test data, start according to the enable packet and obtain the detection result of the first link between the first converter and the second converter according to the first test data, and output the second test data, wherein the first converter is a serializer or a deserializer, and the second converter is a deserializer or a serializer corresponding to the first converter; The first converter is further configured to receive the second test data and obtain a detection result of a second link between the first converter and the second converter according to the second test data.

[0010] Optionally, The first converter is further used to receive a shutdown enable signal sent by the master control, stop sending the first test data according to the shutdown enable signal, and generate and output a shutdown enable packet; The second converter is further configured to receive the shutdown enable packet and stop sending the second test data according to the shutdown enable packet.

[0011] Optionally, The first converter is further configured to send a first test data packet whose required sending duration is a second preset duration within a first preset duration, receive a first feedback signal sent by the second converter according to the received first test data packet, and adjust the first preset duration and / or the second preset duration according to the first feedback signal so that the adjusted sending rate is less than and close to the theoretical maximum bandwidth rate of the first link, and obtain the actual maximum bandwidth rate of the first link according to the adjusted first preset duration and second preset duration; The second converter is further configured to receive a first test data packet and send a first feedback signal according to the received first test data packet.

[0012] Optionally, The second converter is further configured to send a second test data packet whose required sending duration is a fourth preset duration within a third preset duration, receive a second feedback signal sent by the first converter according to the received second test data packet, and adjust the third preset duration and / or the fourth preset duration according to the second feedback signal so that the adjusted sending rate is less than and close to the theoretical maximum bandwidth rate of the second link, and obtain the actual maximum bandwidth rate of the second link according to the adjusted third preset duration and fourth preset duration; The first converter is further configured to receive a second test data packet and send a second feedback signal according to the received second test data packet.

[0013] The present application also provides a link detection device, comprising: a processor, a memory, and a communication bus; The communication bus is used to realize the connection and communication between the processor and the memory; The processor is used to execute the link detection program stored in the memory to implement the steps of any of the link detection methods described above.

[0014] The present application also provides a readable storage medium, in which computer executable instructions are stored. When the computer executable instructions are loaded and executed by a processor, the steps of the link detection method as described in any one of the above items are implemented.

[0015] Compared with the prior art, the present application provides a link detection method, device, equipment and medium, which receives an enable signal sent by a master control through a first converter, generates an enable packet according to the enable signal, and outputs the enable packet and the first test data. The second converter receives the enable packet and the first test data, starts according to the enable packet and obtains the detection result of the first link between the first converter and the second converter according to the first test data, and outputs the second test data, wherein the first converter is a serializer or a deserializer, and the second converter is a deserializer or a serializer corresponding to the first converter. The first converter receives the second test data and obtains the detection result of the second link between the first converter and the second converter according to the second test data. In the present application, when the first converter is a deserializer, the master control can initiate an enable signal to the deserializer to trigger the deserializer to start a built-in self-test. When the first converter is a serializer, the master control can also initiate an enable signal to the serializer to trigger the serializer to start a built-in self-test, so that the built-in self-test is not only applicable to the application scenario where the master control is on the deserializer side, but also to the application scenario where the master control is on the serializer side. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0017] Figure 1 A schematic diagram of a link detection method provided in an embodiment of the present application; Figure 2 A schematic diagram of the structure of a link detection device provided in an embodiment of the present invention; Figure 3 A schematic diagram of the structure of a link detection device provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0018] In order to enable those skilled in the art to better understand the technical solutions in this application, the technical solutions in the embodiments of this application will be clearly and completely described below. Obviously, the described embodiments are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0019] It should be noted that when an element is referred to as being "fixed on" or "set on" another element, it can be directly on the other element or indirectly set on the other element; when an element is referred to as being "connected to" another element, it can be directly connected to the other element or indirectly connected to the other element.

[0020] It should be understood that the terms "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0021] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, "multiple" and "several" mean two or more, unless otherwise clearly and specifically defined.

[0022] It should be noted that the structures, proportions, sizes, etc. illustrated in the drawings of this specification are only used to match the contents disclosed in the specification for people familiar with this technology to understand and read, and are not used to limit the conditions under which this application can be implemented. Therefore, they have no substantive technical significance. Any structural modification, change in proportional relationship or adjustment of size should still fall within the scope of the technical content disclosed in this application without affecting the effects and purposes that can be achieved by this application.

[0023] like Figure 1 As shown, an embodiment of the present application provides a link detection method, the method comprising: S11, the first converter receives the enable signal sent by the master, generates an enable packet according to the enable signal, and outputs the enable packet and the first test data; In this embodiment, the first converter can be a serializer or a deserializer, the enable packet can be a BIST enable packet, i.e., a built-in self-test enable packet, the first test data can be a test pattern or a test file, etc. The first converter receives the enable signal sent by the master control, starts the built-in self-test according to the enable signal, generates an enable packet, and outputs the enable packet and the first test data to the second converter.

[0024] S12, the second converter receives the enable packet and the first test data, starts according to the enable packet and obtains the detection result of the first link between the first converter and the second converter according to the first test data, and outputs the second test data, wherein the first converter is a serializer or a deserializer, and the second converter is a deserializer or a serializer corresponding to the first converter; In this embodiment, the first link is a forward link or a reverse link. If the first converter is a serializer, the second converter is a deserializer and the first link is a forward link. If the first converter is a deserializer, the second converter is a serializer and the first link is a reverse link. The second test data can be a test pattern or a test file, etc. The second converter receives the enable packet and the first test data sent by the first converter, and parses the received enable packet to obtain the parsed enable data, starts the built-in self-test according to the parsed enable data, and compares the received first test data with the benchmark data pre-stored in the second converter to obtain the detection result of the first link between the first converter and the second converter, and outputs the second test data to the first converter.

[0025] S13: The first converter receives the second test data, and obtains a detection result of the second link between the first converter and the second converter according to the second test data.

[0026] In this embodiment, the second link is a reverse link or a forward link. If the first converter is a serializer, the second link is a reverse link. If the first converter is a deserializer, the second link is a forward link. The first converter receives the second test data sent by the second converter, and compares the received second test data with the reference data pre-stored in the first converter to obtain the detection result of the second link between the first converter and the second converter.

[0027] In the present application, when the first converter is a serializer, the master control can initiate an enable signal to the serializer to trigger the serializer to start a built-in self-test, and trigger the second converter which is a deserializer to start a built-in self-test, so that the serializer and the deserializer can simultaneously send test data to the opposite end at different rates, and verify the test data sent by the opposite end to obtain the detection results of the first link and the second link between the serializer and the deserializer; when the first converter is a deserializer, the master control can initiate an enable signal to the deserializer to trigger the deserializer to start a built-in self-test, and trigger the second converter which is a serializer to start a built-in self-test, so that the deserializer and the serializer can simultaneously send test data to the opposite end at different rates, and verify the test data sent by the opposite end to obtain the detection results of the second link and the first link between the deserializer and the serializer, so that the built-in self-test is not only applicable to the application scenario where the master control is on the deserializer side, but also to the application scenario where the master control is on the serializer side.

[0028] Compared with the prior art, the present application provides a link detection method, device, equipment and medium, which receives an enable signal sent by a master control through a first converter, generates an enable packet according to the enable signal, and outputs the enable packet and the first test data. The second converter receives the enable packet and the first test data, starts according to the enable packet and obtains the detection result of the first link between the first converter and the second converter according to the first test data, and outputs the second test data, wherein the first converter is a serializer or a deserializer, and the second converter is a deserializer or a serializer corresponding to the first converter. The first converter receives the second test data and obtains the detection result of the second link between the first converter and the second converter according to the second test data. In the present application, when the first converter is a deserializer, the master control can initiate an enable signal to the deserializer to trigger the deserializer to start a built-in self-test. When the first converter is a serializer, the master control can also initiate an enable signal to the serializer to trigger the serializer to start a built-in self-test, so that the built-in self-test is not only applicable to the application scenario where the master control is on the deserializer side, but also to the application scenario where the master control is on the serializer side.

[0029] As an implementation manner, in the embodiment of the present application, the method further includes: S21, the first converter receives a shutdown enable signal sent by the master control, stops sending the first test data according to the shutdown enable signal, and generates and outputs a shutdown enable packet; In this embodiment, the shutdown enable packet can be a BIST shutdown enable packet, that is, a built-in self-test shutdown enable packet. After receiving the shutdown enable signal sent by the master control, the first converter triggers the stop of the built-in self-test, stops sending the first test data to the second converter according to the received shutdown enable signal, generates a shutdown enable packet, and sends the generated shutdown enable packet to the second converter.

[0030] S22: The second converter receives the shutdown enable packet, and stops sending the second test data according to the shutdown enable packet.

[0031] In this embodiment, the second converter receives the shutdown enable packet sent by the first converter, parses the received shutdown enable packet to obtain the parsed shutdown data, and stops sending the second test data to the first converter according to the parsed shutdown data.

[0032] As an implementation manner, in the embodiment of the present application, the method further includes: S31, the first converter sends a first test data packet with a required sending duration of a second preset duration within a first preset duration; In this embodiment, the first preset duration and the second preset duration are pre-set durations, which can be set according to actual scenario requirements. The first test data packet can be a data packet including one or more first test data. The first converter sends the first test data packet with a required sending duration of the second preset duration within the first preset duration. Specifically, it can be: every M1 clock cycles, the first test data packet with a required sending duration of N1 clock cycles is sent to the second converter, wherein M1 and N1 are both positive integers greater than 1 and N1 is less than M1; the sending duration is the time required to send the test packet.

[0033] S32, receiving a first feedback signal sent by the second converter according to the received first test data packet, and adjusting the first preset duration and / or the second preset duration according to the first feedback signal, so that the adjusted sending rate is less than and close to the theoretical maximum bandwidth rate of the first link; In this embodiment, the first feedback signal includes a first sub-feedback signal and a second sub-feedback signal. After receiving the first test data packet, the second converter will compare it with the pre-stored benchmark data. If the comparison is correct, the first sub-feedback signal will be sent to the first converter. After receiving a first sub-feedback signal sent by the second converter, the first converter adjusts the value of the second preset time length to switch the gear of the sending rate of the first test data packet. When the sending rate of the first test data packet sent by the first converter is greater than the theoretical maximum bandwidth rate of the first link, the second converter will feed back a second sub-feedback signal to the first converter. After receiving the second sub-feedback signal, the first converter will adjust the value of the first preset time length so that the adjusted sending rate is less than and close to the theoretical maximum bandwidth rate of the first link. Specifically, it may be that after receiving the first test data packet, the second converter compares it with the pre-stored benchmark data. If the comparison is correct, a comparison correct signal is sent to the first converter. After receiving the comparison correct signal sent by the second converter, the first converter keeps M1 unchanged and adjusts the value of N1 to switch the gear of the sending rate of the first test data packet. When the sending rate of the first test data packet sent by the first converter is greater than the theoretical maximum bandwidth rate of the first link, the second converter feeds back a rate reduction signal to the first converter. After receiving the rate reduction signal, the first converter keeps N1 unchanged and adjusts the value of M1 so that the adjusted sending rate is less than and close to the theoretical maximum bandwidth rate of the first link. When the first converter sends When the sending rate of the first test data packet is greater than the theoretical maximum bandwidth rate of the first link, the second converter can be controlled to feed back a "busy" level signal, i.e., a high level signal, which is pulled high for a period of time, to the first converter. After receiving the "busy" level signal, the counter for counting the M1 value will be immediately paused, and the counter will continue counting after the "busy" level signal disappears. Since the calculator for counting the M1 value is paused for a period of time, it is equivalent to that the M1 value becomes larger, and N1 remains unchanged. The sending rate of the first test data packet can be effectively reduced, and the adjusted sending rate of the first test data packet can be made less than and close to the theoretical maximum bandwidth rate of the first link, so that the first link can be fully loaded with data without packet loss.

[0034] S33: Obtain an actual maximum bandwidth rate of the first link according to the adjusted first preset duration and the second preset duration.

[0035] In this embodiment, the actual maximum bandwidth rate of the first link between the first converter and the second converter may be obtained according to the adjusted first preset time length and the adjusted second preset time length.

[0036] As an implementation manner, in the embodiment of the present application, the method further includes: S41, the second converter sends a second test data packet with a required sending duration of a fourth preset duration within a third preset duration; In this embodiment, the third preset duration and the fourth preset duration are pre-set durations, which can be set according to actual scenario requirements. The second test data packet can be a data packet including one or more second test data. The second converter sends the second test data packet of the fourth preset duration within the third preset duration. Specifically, it can be: every M2 clock cycles, the second test data packet with a required sending duration of N2 clock cycles is sent to the first converter, wherein M2 and N2 are positive integers greater than 1 and N2 is less than M2; the sending duration is the time required to send the test packet.

[0037] S42, receiving a second feedback signal sent by the first converter according to the received second test data packet, and adjusting the third preset duration and / or the fourth preset duration according to the second feedback signal, so that the adjusted sending rate is less than and close to the theoretical maximum bandwidth rate of the second link; In this embodiment, the second feedback signal includes a third sub-feedback signal and a fourth sub-feedback signal. After receiving the second test data packet, the first converter will compare it with the pre-stored benchmark data. If the comparison is correct, a third sub-feedback signal will be sent to the second converter. After receiving the third sub-feedback signal sent by the first converter, the second converter adjusts the value of the fourth preset time length to switch the gear of the sending rate of the second test data packet. When the sending rate of the second test data packet sent by the second converter is greater than the theoretical maximum bandwidth rate of the second link, the first converter will feed back a fourth sub-feedback signal to the second converter. After receiving the fourth sub-feedback signal, the second converter will adjust the value of the third preset time length so that the adjusted sending rate is less than and close to the theoretical maximum bandwidth rate of the second link. Specifically, it may be that after receiving the second test data packet, the first converter compares it with the pre-stored benchmark data. If the comparison is correct, the first converter sends a comparison correct signal to the second converter. After receiving the comparison correct signal sent by the first converter, the second converter keeps M2 unchanged and adjusts the value of N2 to switch the gear of the sending rate of the second test data packet. When the sending rate of the second test data packet sent by the second converter is greater than the theoretical maximum bandwidth rate of the second link, the first converter feeds back a rate reduction signal to the second converter. After receiving the rate reduction signal, the first converter keeps N2 unchanged and adjusts the value of M2 so that the adjusted sending rate is less than and close to the theoretical maximum bandwidth rate of the second link. When the second converter sends When the sending rate of the second test data packet is greater than the theoretical maximum bandwidth rate of the second link, the first converter can be controlled to feed back a "busy" level signal, i.e., a high level signal, which is pulled high for a period of time, to the second converter. After receiving the "busy" level signal, the counter for counting the M2 value will be paused immediately, and the calculator will continue counting after the "busy" level signal disappears. Since the calculator for counting the M2 value is paused for a period of time, it is equivalent to that the M2 value becomes larger, while N2 remains unchanged. The sending rate of the second test data packet can be effectively reduced, and the adjusted sending rate of the second test data packet can be made less than and close to the theoretical maximum bandwidth rate of the second link, so that the second link can be fully loaded with data without packet loss.

[0038] S43: Obtain an actual maximum bandwidth rate of the second link according to the adjusted third preset duration and fourth preset duration.

[0039] In this embodiment, the actual maximum bandwidth rate of the second link between the first converter and the second converter may be obtained according to the adjusted third preset time length and the adjusted fourth preset time length.

[0040] like Figure 2 As shown, the present application also provides a link detection device, the link detection device includes a first converter and a second converter, wherein: The first converter 21 is used to receive the enable signal sent by the master, generate an enable packet according to the enable signal, and output the enable packet and the first test data; The second converter 22 is used to receive the enable packet and the first test data, start according to the enable packet and obtain the detection result of the first link between the first converter and the second converter according to the first test data, and output the second test data, wherein the first converter is a serializer or a deserializer, and the second converter is a deserializer or a serializer corresponding to the first converter; The first converter 21 is further configured to receive second test data and obtain a detection result of a second link between the first converter and the second converter according to the second test data.

[0041] As an implementation mode, in the examples of the present application, The first converter is further used to receive a shutdown enable signal sent by the master control, stop sending the first test data according to the shutdown enable signal, and generate and output a shutdown enable packet; The second converter is further used to receive the shutdown enable packet and stop sending the second test data according to the shutdown enable packet.

[0042] As an implementation mode, in the examples of the present application, The first converter is further configured to send a first test data packet whose required sending duration is a second preset duration within a first preset duration, receive a first feedback signal sent by the second converter according to the received first test data packet, and adjust the first preset duration and / or the second preset duration according to the first feedback signal so that the adjusted sending rate is less than and close to the theoretical maximum bandwidth rate of the first link, and obtain the actual maximum bandwidth rate of the first link according to the adjusted first preset duration and the second preset duration; The second converter is further configured to receive a first test data packet and send a first feedback signal according to the received first test data packet.

[0043] As an implementation mode, in the examples of the present application, The second converter is further configured to send a second test data packet whose required sending duration is a fourth preset duration within a third preset duration, receive a second feedback signal sent by the first converter according to the received second test data packet, and adjust the third preset duration and / or the fourth preset duration according to the second feedback signal so that the adjusted sending rate is less than and close to the theoretical maximum bandwidth rate of the second link, and obtain the actual maximum bandwidth rate of the second link according to the adjusted third preset duration and fourth preset duration; The first converter is further configured to receive a second test data packet and send a second feedback signal according to the received second test data packet.

[0044] like Figure 3 As shown, the present application also provides a link detection device, including: a processor 31, a memory 32 and a communication bus 33; A communication bus 33, used to realize connection and communication between the processor 31 and the memory 32; The processor 31 is used to execute the link detection program stored in the memory 32 to implement the steps of any one of the above link detection methods.

[0045] The present application also provides a readable storage medium, in which computer executable instructions are stored. When the computer executable instructions are loaded and executed by a processor, the steps of any of the above-mentioned link detection methods are implemented.

[0046] It should be understood that the use of "system", "device", "unit" and / or "module" in this application is only a method for distinguishing multiple components, elements, parts, parts or assemblies at multiple levels. However, if other words can achieve the same purpose, the word can be replaced by other expressions.

[0047] The embodiments in this specification are described in a progressive manner, and each embodiment focuses on the For other embodiments, the same or similar parts of each embodiment can be referenced to each other.

[0048] The above description of the disclosed embodiments enables those skilled in the art to implement or use the present application. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to the embodiments shown herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A link detection method, characterized in that: The method comprises: The first converter receives the enable signal sent by the master, generates an enable packet according to the enable signal, and outputs the enable packet and the first test data; The second converter receives the enable packet and the first test data, starts according to the enable packet and obtains a detection result of the first link between the first converter and the second converter according to the first test data, and outputs second test data, wherein the first converter is a serializer or a deserializer, and the second converter is a deserializer or a serializer corresponding to the first converter; The first converter receives the second test data, and obtains a detection result of a second link between the first converter and the second converter according to the second test data.

2. The link detection method according to claim 1, characterized in that: The method further comprises: The first converter receives a shutdown enable signal sent by the master control, stops sending the first test data according to the shutdown enable signal, and generates and outputs a shutdown enable packet; The second converter receives the shutdown enable packet and stops sending the second test data according to the shutdown enable packet.

3. The link detection method according to claim 1 or 2, characterized in that: The method further comprises: The first converter sends a first test data packet having a required sending duration of a second preset duration within a first preset duration; receiving a first feedback signal sent by the second converter according to the received first test data packet, and adjusting the first preset duration and / or the second preset duration according to the first feedback signal, so that the adjusted sending rate is less than and close to the theoretical maximum bandwidth rate of the first link; The actual maximum bandwidth rate of the first link is obtained according to the adjusted first preset duration and the second preset duration.

4. The link detection method according to claim 1 or 2, characterized in that: The method further comprises: The second converter sends a second test data packet having a required sending duration of a fourth preset duration within a third preset duration; receiving a second feedback signal sent by the first converter according to the received second test data packet, and adjusting the third preset duration and / or the fourth preset duration according to the second feedback signal, so that the adjusted sending rate is less than and close to the theoretical maximum bandwidth rate of the second link; The actual maximum bandwidth rate of the second link is obtained according to the adjusted third preset time length and fourth preset time length.

5. A link detection device, characterized in that: The link detection device comprises a first converter and a second converter, wherein: The first converter is used to receive the enable signal sent by the master, generate an enable packet according to the enable signal, and output the enable packet and the first test data; The second converter is used to receive the enable packet and the first test data, start according to the enable packet and obtain the detection result of the first link between the first converter and the second converter according to the first test data, and output the second test data, wherein the first converter is a serializer or a deserializer, and the second converter is a deserializer or a serializer corresponding to the first converter; The first converter is further configured to receive the second test data and obtain a detection result of a second link between the first converter and the second converter according to the second test data.

6. The link detection device according to claim 5, characterized in that: The first converter is further used to receive a shutdown enable signal sent by the master control, stop sending the first test data according to the shutdown enable signal, and generate and output a shutdown enable packet; The second converter is further configured to receive the shutdown enable packet and stop sending the second test data according to the shutdown enable packet.

7. The link detection device according to claim 5 or 6, characterized in that: The first converter is further configured to send a first test data packet whose required sending duration is a second preset duration within a first preset duration, receive a first feedback signal sent by the second converter according to the received first test data packet, and adjust the first preset duration and / or the second preset duration according to the first feedback signal so that the adjusted sending rate is less than and close to the theoretical maximum bandwidth rate of the first link, and obtain the actual maximum bandwidth rate of the first link according to the adjusted first preset duration and second preset duration; The second converter is further configured to receive a first test data packet and send a first feedback signal according to the received first test data packet.

8. The link detection device according to claim 5 or 6, characterized in that: The second converter is further configured to send a second test data packet whose required sending duration is a fourth preset duration within a third preset duration, receive a second feedback signal sent by the first converter according to the received second test data packet, and adjust the third preset duration and / or the fourth preset duration according to the second feedback signal so that the adjusted sending rate is less than and close to the theoretical maximum bandwidth rate of the second link, and obtain the actual maximum bandwidth rate of the second link according to the adjusted third preset duration and fourth preset duration; The first converter is further configured to receive a second test data packet and send a second feedback signal according to the received second test data packet.

9. A link detection device, characterized in that: include: processor, memory, and communication bus; The communication bus is used to realize the connection and communication between the processor and the memory; The processor is used to execute the link detection program stored in the memory to implement the steps of the link detection method according to any one of claims 1 to 4.

10. A readable storage medium, characterized in that: The readable storage medium stores computer executable instructions, and when the computer executable instructions are loaded and executed by the processor, the steps of the link detection method according to any one of claims 1 to 4 are implemented.

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