Power management integrated circuit and power management system

Abstract

The invention discloses a power management integrated circuit and a power management system. The power management integrated circuit is welded on a printed circuit board and comprises a first output stage circuit and a second output stage circuit, in the discrete configuration, the first and second current inflow pins of the first and second output stage circuits are respectively welded to the first and second inflow printed conductors that are not directly electrically connected, and the first and second current outflow pins of the first and second output stage circuits are respectively welded to the first and second outflow printed conductors that are not directly electrically connected. In the combined configuration, the first and second current inflow pins are both welded to a common inflow printed wire for electrical connection, and the first and second current outflow pins are both welded to a common outflow printed wire for electrical connection, so that the first and second elements are connected in parallel, and the first and second output stage circuits are combined into a combined output stage circuit. A common output power is generated.

Description

Technical Field

[0001] The present invention relates to a power management integrated circuit and a power management system, and in particular to a power management integrated circuit and a power management system which can save printed circuit board space and meet different power requirements at the same time. Background Art

[0002] Figure 1A and Figure 1B 1 is a circuit block diagram showing a known power management system. A conventional power management system 10 includes a power management integrated circuit 11 (11') and a printed circuit board 12 (12'). The power management integrated circuit 11 (11') is a product in the form of an integrated circuit package. When the power management system 10 needs to provide different output power supplies in different combinations for different platform applications, the appearance and circuit layout of the power management integrated circuit 11 (11') and the printed circuit board 12 (12') must be substantially the same to facilitate production and reduce manufacturing costs. Figure 1A and Figure 1B The power management system 10 is shown arranged in a topology design.

[0003] like Figure 1A and Figure 1B As shown, when the power management system 10 needs to provide two different power supplies or a single power supply for two different platforms, considering the production process of the power management integrated circuit 11 (11') and the printed circuit board 12 (12'), additional costs need to be paid in the spatial layout to obtain application flexibility.

[0004] In such Figure 1A In the platform shown, the power management system 10 includes a power management integrated circuit 11 and a printed circuit board 12. The power management system 10 provides a first output power supply and a second output power supply; wherein the first output power supply includes a first output voltage Vout1 and a first output current Iout1; wherein the second output power supply includes a second output voltage Vout2 and a second output current Iout2. For example, the upper limit of the first output current Iout1 is 7A, and the upper limit of the second output current Iout2 is 3A. On the other hand, in the case of Figure 1B In the platform shown, the power management system 10 provides output power, wherein the output power includes an output voltage Vout and an output current Iout. For example, the upper limit of the output current Iout is 10 A. That is, the power management system 10 having substantially the same appearance and circuit layout can provide different power combinations for two different platforms.

[0005] like Figure 1AAs shown, the power management system 10 platform requires two output power supplies, for example, the first output power supply has an output voltage Vout1 and needs to provide an output current Iout1 with an upper limit of 7A, and the second output power supply has an output voltage Vout2 and needs to provide an output current Iout2 with an upper limit of 3A. Figure 1B The power management system platform shown only requires one output power supply, for example, the output power supply has an output voltage Vout and needs to provide an output current Iout with an upper limit of 10A.

[0006] like Figure 1A As shown, the power management integrated circuit 11 includes a step-down circuit 101a and a step-down circuit 101b, which are used to provide a first output power and a second output power respectively; Figure 1B As shown, the power management integrated circuit 11' includes a buck circuit 101c for providing output power. In order to meet the above conditions, and to keep the arrangement and circuit layout of other circuits in the power management integrated circuits 11 and 11' roughly the same, and the arrangement of other circuits and lines in the printed circuit boards 12 and 12' roughly the same, the traditional method is to place the smaller buck circuit 101a in the space reserved for the larger buck circuit 101c, so that it can not only meet the application of the output current with an upper limit of 7A, but also meet the application of the output current with an upper limit of 10A, such as Figure 1A However, this will cause a problem, that is, it will be necessary to reserve unnecessary idle space to meet the application with an upper limit of 10A, such as Figure 1A When the power management system 10 only needs to provide output power with an output voltage Vout and an output current Iout with an upper limit of 10A, only one step-down circuit 101c is needed, as shown in FIG. Figure 1B As shown, Figure 1A The space for placing the step-down circuit 101 b cannot be utilized at all and becomes idle space, which increases the space cost of the entire integrated circuit and the printed circuit board.

[0007] In view of the above shortcomings of the prior art, the present invention proposes a power management integrated circuit and a power management system that can save printed circuit board space and simultaneously meet different power requirements. Summary of the invention

[0008] In one aspect, the present invention provides a power management integrated circuit, which is soldered on a printed circuit board. The power management integrated circuit includes: a first output stage circuit; and a second output stage circuit; wherein in a discrete configuration, a first current inflow pin of the first output stage circuit and a second current inflow pin of the second output stage circuit are respectively soldered to a first inflow printed conductor and a second inflow printed conductor of the printed circuit board that are not directly electrically connected to each other, a first current outflow pin of the first output stage circuit and a second current outflow pin of the second output stage circuit are respectively soldered to a first outflow printed conductor and a second outflow printed conductor of the printed circuit board that are not directly electrically connected to each other, and a first element and a second element are respectively used to generate a first output power corresponding to the first current outflow pin and a second output power corresponding to the second current outflow pin according to a first input power corresponding to the first current inflow pin and a second input power corresponding to the second current inflow pin. , the current upper limits of the first output power supply and the second output power supply are respectively a first maximum output current and a second maximum output current; wherein in a combined configuration, the first current inflow pin and the second current inflow pin are both soldered to a common inflow printed wire of the printed circuit board and electrically connected, and the first current outflow pin and the second current outflow pin are both soldered to a common outflow printed wire of the printed circuit board and electrically connected, so that the first element is connected in parallel with the second element, and then the first output stage circuit and the second output stage circuit are combined into a combined output stage circuit to generate a common output power supply, wherein the current upper limit of the common output power supply is the sum of the first maximum output current and the second maximum output current; wherein a first current inflow end and a first current outflow end of the first element correspond to the first current inflow pin and the first current outflow pin, and a second current inflow end and a second current outflow end of the second element correspond to the second current inflow pin and the second current outflow pin.

[0009] In another aspect, the present invention provides a power management system, comprising a power management integrated circuit and a printed circuit board, wherein the power management integrated circuit is soldered on the printed circuit board, and the power management integrated circuit comprises: a first output stage circuit; and a second output stage circuit; wherein in a discrete configuration, a first current inflow pin of the first output stage circuit and a second current inflow pin of the second output stage circuit are respectively soldered to a first inflow printed conductor and a second inflow printed conductor of the printed circuit board that are not directly electrically connected to each other, a first current outflow pin of the first output stage circuit and a second current outflow pin of the second output stage circuit are respectively soldered to a first outflow printed conductor and a second outflow printed conductor of the printed circuit board that are not directly electrically connected to each other, and a first element and a second element are respectively used to generate a first output power corresponding to the first current outflow pin and a second output power corresponding to the second current inflow pin according to a first input power corresponding to the first current inflow pin and a second input power corresponding to the second current inflow pin. A second output power supply with two current outflow pins, the current upper limits of the first output power supply and the second output power supply are respectively a first maximum output current and a second maximum output current; wherein in a combined configuration, the first current inflow pin and the second current inflow pin are both soldered to a common inflow printed conductor of the printed circuit board and electrically connected, and the first current outflow pin and the second current outflow pin are both soldered to a common outflow printed conductor of the printed circuit board and electrically connected, so that the first element and the second element are connected in parallel, and then the first output stage circuit and the second output stage circuit are combined into a combined output stage circuit to generate a common output power supply, wherein the current upper limit of the common output power supply is the sum of the first maximum output current and the second maximum output current; wherein a first current inflow end and a first current outflow end of the first element correspond to the first current inflow pin and the first current outflow pin, and a second current inflow end and a second current outflow end of the second element correspond to the second current inflow pin and the second current outflow pin.

[0010] In one embodiment, the common inflow printed conductor and the common outflow printed conductor are both located below the integrated circuit and between the integrated circuit and the printed circuit board.

[0011] In one embodiment, the common inflow printed conductor and / or the common outflow printed conductor are located on the uppermost layer of the printed circuit board.

[0012] In one embodiment, the first current inflow pin and the second current inflow pin are located on the same plane, so that the common inflow printed conductor is located on the top layer of the printed circuit board, and / or the first current outflow pin and the second current outflow pin are located on the same plane, so that the common outflow printed conductor is located on the top layer of the printed circuit board.

[0013] In one embodiment, the first current inflow pin and the second current inflow pin are located on both sides of the integrated circuit in a width direction and the first current inflow pin and the second current inflow pin are aligned with each other in a length direction, so that the common inflow printed conductor is located on the top layer of the printed circuit board, and / or, the first current outflow pin and the second current outflow pin are located on both sides of the integrated circuit in the width direction and the first current outflow pin and the second current outflow pin are aligned with each other in the length direction, so that the common outflow printed conductor is located on the top layer of the printed circuit board.

[0014] In one embodiment, the common inflow printed conductor is aligned with the first current inflow pin and the second current inflow pin in the length direction, and / or the common outflow printed conductor is aligned with the first current outflow pin and the second current outflow pin in the length direction.

[0015] In one embodiment, the first output stage circuit and the second output stage circuit are a linear power conversion circuit, wherein: in the discrete configuration, the first element and the second element correspond to a first transistor and a second transistor, and the first output power and the second output power are generated in a linear regulation manner according to a first feedback signal and a second feedback signal of the first output power and the second output power, respectively; and in the combined configuration, the first element and the second element are connected in parallel to form a common transistor, and the common output power is generated in a linear regulation manner according to a common feedback signal of the common output power.

[0016] In one embodiment, the first output stage circuit and the second output stage circuit are a switching output stage circuit, wherein: in the discrete configuration, the first element and the second element correspondingly include an upper bridge switch and a lower bridge switch of the switching output stage circuit, a driving circuit for driving the upper bridge switch or the lower bridge switch, and / or a current detection circuit, for controlling the switching of a corresponding first inductor and a corresponding second inductor according to a first feedback signal and a second feedback signal of the first output power supply and the second output power supply, respectively, to generate the first output power supply and the second output power supply; and in the combined configuration, the first element and the second element control the switching of a corresponding inductor according to a common feedback signal of the common output power supply to generate the common output power supply.

[0017] In one embodiment, in the discrete configuration, the first current inflow pin and the first current outflow pin are electrically connected to a first input voltage and a first switching node through the first inflow printed wire and the first outflow printed wire, and the second current inflow pin and the second current outflow pin are electrically connected to a second output voltage and a second switching node through the second inflow printed wire and the second outflow printed wire; and in the combined configuration, the first current inflow pin and the first current outflow pin are electrically connected to a common input voltage and a common switching node through the common inflow printed wire and the common outflow printed wire, and the second current inflow pin and the second current outflow pin are electrically connected to the common input voltage and the common switching node through the common inflow printed wire and the common outflow printed wire.

[0018] The advantages of the present invention are that the power management integrated circuit of the present invention can save printed circuit board space and can meet different power requirements at the same time.

[0019] The following is a detailed description through specific embodiments to make it easier to understand the purpose, technical content, characteristics and effects achieved by the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1A and Figure 1B is a circuit block diagram showing a known power management system.

[0021] Figure 2A and Figure 2B FIG. 4 is a circuit block diagram showing a power management system according to an embodiment of the present invention.

[0022] Figure 3A and Figure 3B FIG. 1 is a bottom view showing a power management system according to an embodiment of the present invention.

[0023] Figure 4A and Figure 4B According to the present invention Figure 3A In the illustrated embodiment, cross-sectional views are taken along line AA and line BB respectively.

[0024] Figure 4C and Figure 4D According to the present invention Figure 3B In the illustrated embodiment, cross-sectional views are taken along line AA and line BB respectively.

[0025] Figure 5A and Figure 5B FIG. 4 is a bottom view showing a power management system according to another embodiment of the present invention.

[0026] Figure 6 FIG. 4 is a circuit diagram showing a power management integrated circuit according to an embodiment of the present invention.

[0027] Figure 7 FIG. 4 is a circuit diagram showing a power management integrated circuit according to another embodiment of the present invention.

[0028] Explanation of symbols in the figure

[0029] 10, 20: Power management system

[0030] 11, 11', 21, 21': Power Management Integrated Circuit

[0031] 12, 12', 22, 22': Printed Circuit Board

[0032] 101a, 101b, 101c: Buck circuit

[0033] 201a: First output stage circuit

[0034] 201b: Second output stage circuit

[0035] 203: Control circuit

[0036] DU1, DU2, DL1, DL2: drive circuit

[0037] L, L1, L2: Inductor

[0038] LX1, LX2: Switching nodes

[0039] Pboot1, Pboot2: driver pins

[0040] Pgnd: Ground pin

[0041] Psw1, Pvout1: The first current outflow pin

[0042] Psw2, Pvout2: Second current outflow pin

[0043] Pvin1: The first current flows into the pin

[0044] Pvin2: Second current flow pin

[0045] Q1: First transistor

[0046] Q2: Second transistor

[0047] QL1, QL2: lower bridge switch

[0048] QU1, QU2: upper bridge switch

[0049] Tin1: First inflow printed wire

[0050] Tin2: Second inflow printed wire

[0051] Tins: Commonly flow into printed conductors

[0052] Tout1: First outgoing printed conductor

[0053] Tout2: Second outgoing printed conductor

[0054] Touts: Common outflow printed conductors

[0055] Tsw1, Tsw2: Current outflow end

[0056] Tvin1, Tvin2: Current inflow terminal

[0057] Vout: (common) output power

[0058] Vout1: first output power

[0059] Vout2: Second output power supply DETAILED DESCRIPTION

[0060] The drawings in the present invention are all schematic, and are mainly intended to show the coupling relationship between various circuits and the relationship between various signal waveforms. The circuits, signal waveforms and frequencies are not drawn according to scale.

[0061] Figure 2A and Figure 2B FIG. 1 is a circuit block diagram showing a power management system according to an embodiment of the present invention. Figure 2A and Figure 2B As shown, the power management system 20 of the present invention includes a power management integrated circuit 21 (21') and a printed circuit board 22 (22'). The power management integrated circuit 21 (21') is a product in the form of an integrated circuit package, including a first output stage circuit 201a and a second output stage circuit 201b. The first output stage circuit 201a includes a first component, and the second output stage circuit 201b includes a second component. The first output stage circuit 201a and the second output stage circuit 201b are integrated into the power management integrated circuit 21 (21'). Figure 2A represents a discrete configuration, while Figure 2B Indicates a merged configuration. Figure 2A In the discrete configuration shown, the first output stage circuit 201a and one end of the inductor L1 are coupled to the switching node LX1, and the other end of the inductor L1 is coupled to the first output power Vout1, and the second output stage circuit 201b and the inductor L2 are coupled to the switching node LX2, and the other end of the inductor L2 is coupled to the second output power Vout2. In the combined configuration, the switching nodes LX1 and LX2 are coupled through PCB wires to form a switching node LX, which is further coupled to the inductor L.

[0062] Figure 3A and Figure 3B FIG. 1 is a bottom view showing a power management system according to an embodiment of the present invention. Figure 4A and Figure 4B According to the present invention Figure 3A In the illustrated embodiment, cross-sectional views are taken along line AA and line BB respectively. Figure 4C and Figure 4D According to the present invention Figure 3B In the illustrated embodiment, cross-sectional views are taken along line AA and line BB respectively. Figure 3A and Figure 4A and Figure 4B represents a discrete configuration, while Figure 3B and Figure 4C and Figure 4D In this embodiment, the first output stage circuit 201a and the second output stage circuit 201b are switching output stage circuits.

[0063] like Figure 3A and Figure 4A and Figure 4B As shown, in a discrete configuration, the first current inflow pin Pvin1 of the first output stage circuit 201a and the second current inflow pin Pvin2 of the second output stage circuit 201b are respectively soldered to the first inflow printed wire Tin1 and the second inflow printed wire Tin2 of the printed circuit board 22 which are not directly electrically connected to each other, and the first current outflow pin Psw1 of the first output stage circuit 201a and the second current outflow pin Psw2 of the second output stage circuit 201b are respectively soldered to the first outflow printed wire Tout1 and the second outflow printed wire Tout2 of the printed circuit board 22 which are not directly electrically connected to each other. The first element and the second element are respectively used to generate the first output power Vout1 and the second output power Vout2 according to the first input power and the second input power, and the current upper limits of the first output power Vout1 and the second output power Vout2 are respectively the first maximum output current and the second maximum output current.

[0064] like Figure 3B and Figure 4C and Figure 4DAs shown, in the combined configuration, the first current inflow pin Pvin1 of the first output stage circuit 201a and the second current inflow pin Pvin2 of the second output stage circuit 201b are both soldered to the common inflow printed conductor Tins of the printed circuit board 22' and electrically connected, and the first current outflow pin Psw1 of the first output stage circuit 201a and the second current outflow pin Psw2 of the second output stage circuit 201b are both soldered to the common outflow printed conductor Touts of the printed circuit board 22' and electrically connected, so that the first element is connected in parallel with the second element, thereby combining the first output stage circuit 201a and the second output stage circuit 201b into a combined output stage circuit to generate a common output power supply Vout. The upper limit of the current of the common output power supply is the sum of the first maximum output current and the second maximum output current. Please refer to Figure 6 The current inflow end Tvin1 and the current outflow end Tsw1 of the first element correspond to the first current inflow pin Pvin1 and the first current outflow pin Psw1 respectively, and the current inflow end Tvin2 and the current outflow end Tsw2 of the second element correspond to the second current inflow pin Pvin2 and the second current outflow pin Psw2 respectively.

[0065] like Figure 3B and Figure 4C and Figure 4D As shown, in the combined configuration, the first current inflow pin Pvin1 and the second current inflow pin Pvin2 are located on the same plane, so that the common inflow printed conductor Tins is located on the top layer of the printed circuit board 22', and / or, the first current outflow pin Psw1 and the second current outflow pin Psw2 are located on the same plane, so that the common outflow printed conductor Touts is located on the top layer of the printed circuit board 22'.

[0066] like Figure 3B As shown, in the combined configuration, the first current inflow pin Pvin1 and the second current inflow pin Pvin2 are located on both sides of the integrated circuit 21' in the width direction and the first current inflow pin Pvin1 and the second current inflow pin Pvin2 are aligned with each other in the length direction, so that the common inflow printed conductor Tins is located on the top layer of the printed circuit board 22', and / or, the first current outflow pin Psw1 and the second current outflow pin Psw2 are located on both sides of the integrated circuit 21' in the width direction and the first current outflow pin Psw1 and the second current outflow pin Psw2 are aligned with each other in the length direction, so that the common outflow printed conductor Touts is located on the top layer of the printed circuit board 22'.

[0067] like Figure 3BAs shown, the common inflow printed conductor Tins is aligned with the first current inflow pin Pvin1 and the second current inflow pin Pvin2 in the length direction, and / or the common outflow printed conductor Touts is aligned with the first current outflow pin Psw1 and the second current outflow pin Psw2 in the length direction.

[0068] At Figure 3A and Figure 4A and Figure 4B In the discrete configuration shown, the first current inflow pin Pvin1 and the first current outflow pin Psw1 are electrically connected to the first input voltage and the first switching node through the first inflow printed conductor Tin1 and the first outflow printed conductor Tout1, and the second current inflow pin Pvin2 and the second current outflow pin Psw2 are electrically connected to the second input voltage and the second switching node through the second inflow printed conductor Tin2 and the second outflow printed conductor Tout2.

[0069] At Figure 3B and Figure 4C and Figure 4D In the combined configuration shown, the first current inflow pin Pvin1 and the first current outflow pin Psw1 are electrically connected to a common input voltage and a common switching node via a common inflow printed wire Tins and a common outflow printed wire Touts, and the second current inflow pin Pvin2 and the second current outflow pin Psw2 are electrically connected to a common input voltage and a common switching node via a common inflow printed wire Tins and a common outflow printed wire Touts. In one embodiment, the driving pins Pboot1 and Pboot2 may also be coupled via a common printed wire.

[0070] like Figure 3B and Figure 4C and Figure 4D As shown, in the combined configuration, the first element and the second element control the switching of the corresponding inductor L according to the common feedback signal of the common output power Vout to generate the common output power Vout.

[0071] Figure 4A and Figure 4B According to an embodiment of the present invention, Figure 3A Cross-sectional views taken along line AA and line BB. Figure 4B and Figure 4D According to an embodiment of the present invention, Figure 3B The cross-sectional view taken along line AA and line BB. Figure 3A-3B and Figure 4A-4D As shown, the integrated circuit 21 (21') is soldered on the printed circuit board 22 (22'). Figure 4C and Figure 4DAs shown, the common inflow printed conductors Tins and the common outflow printed conductors Touts are both located below the integrated circuit 21 and between the integrated circuit 21 and the printed circuit board 22. The common inflow printed conductors Tins and / or the common outflow printed conductors Touts are located on the top layer of the printed circuit board 22.

[0072] Figure 5A and Figure 5B FIG. 2 is a bottom view showing a power management system according to another embodiment of the present invention. In this embodiment, the first output stage circuit 201a and the second output stage circuit 201b are, for example, linear power conversion circuits. Figure 3A and Figure 3B The embodiment is similar to the embodiment of FIG. 1 , except that the embodiment does not have inductors L1 and L2, and the first current outflow pin of the embodiment is Pvout1, and the second current outflow pin is Pvout2. The remaining components are similar to Figure 3A and Figure 3B , so the detailed description is omitted.

[0073] Figure 6 FIG. 1 is a circuit diagram showing a power management integrated circuit according to an embodiment of the present invention. In this embodiment, the first output stage circuit 201a and the second output stage circuit 201b are switching output stage circuits. Figure 6 As shown, the first element and the second element may correspond to the upper bridge switches QU1, QU2 and the lower bridge switches QL1, QL2 of the switching output stage circuit, respectively, to drive the driving circuits DU1, DU2, DL1, DL2 and / or the current detection circuits (not shown) of the upper bridge switches QU1, QU2 or the lower bridge switches QL1, QL2. The control circuit 203 generates an operation signal to the driving circuits DU1, DL1, DU2 and DL2. Figure 6 As shown, one end of the lower bridge switch QL1 is coupled to the upper bridge switch QU1 at the current outflow terminal Tsw1, and the other end of the lower bridge switch QL1 is coupled to the ground pin Pgnd. Figure 6 As shown, in a discrete configuration, the first element and the second element are used to control the switching of the corresponding inductor L1 and the inductor L2 according to the first feedback signal and the second feedback signal of the first output power Vout1 and the second output power Vout2 respectively to generate the first output power Vout1 and the second output power Vout2.

[0074] Figure 7 FIG. 2 is a circuit diagram showing a power management integrated circuit according to another embodiment of the present invention. In this embodiment, the first output stage circuit 201a and the second output stage circuit 201b are linear power conversion circuits. Figure 7 As shown, the first element and the second element may be a first transistor Q1 and a second transistor Q2. Figure 7As shown, in a discrete configuration, the first transistor Q1 and the second transistor Q2 generate the first output power Vout1 and the second output power Vout2 in a linear regulation manner according to the first feedback signal and the second feedback signal of the first output power Vout1 and the second output power Vout2 respectively.

[0075] like Figure 5A and Figure 5B As shown, in the combined configuration, the first element and the second element are connected in parallel to form a common transistor, and the common output power Vout is generated in a linear regulation manner according to a common feedback signal of the common output power Vout.

[0076] As described above, the present invention can save printed circuit board space and meet different power requirements at the same time by coupling the first current inflow pin and the second current inflow pin, for example, by soldering them to a common inflow printed conductor of the printed circuit board, and coupling the first current outflow pin and the second current outflow pin, for example, by soldering them to a common outflow printed conductor of the printed circuit board.

[0077] The present invention has been described above with respect to the preferred embodiment, but the above description is only to make it easy for those skilled in the art to understand the content of the present invention, and is not used to limit the widest scope of the rights of the present invention. The various embodiments described are not limited to individual applications, but can also be used in combination. For example, two or more embodiments can be used in combination, and part of the components in one embodiment can also be used to replace the corresponding components in another embodiment. In addition, under the same spirit of the present invention, those skilled in the art can think of various equivalent changes and various combinations. For example, the present invention refers to "processing or calculating or generating an output result according to a certain signal", which is not limited to the signal itself, but also includes, when necessary, converting the signal to voltage and current, current and voltage, and / or ratio conversion, and then processing or calculating according to the converted signal to generate an output result. It can be seen that under the same spirit of the present invention, those skilled in the art can think of various equivalent changes and various combinations, and there are many combinations, which are not listed one by one here. Therefore, the scope of the present invention should cover the above and all other equivalent changes.

Claims

1. A power management integrated circuit, soldered on a printed circuit board, the power management integrated circuit comprising: a first output stage circuit; and a second output stage circuit; wherein in a discrete configuration, a first current inflow pin of the first output stage circuit and a second current inflow pin of the second output stage circuit are respectively soldered to a first inflow printed conductor and a second inflow printed conductor that are not directly electrically connected to each other of the printed circuit board, a first current outflow pin of the first output stage circuit and a second current outflow pin of the second output stage circuit are respectively soldered to a first outflow printed conductor and a second outflow printed conductor that are not directly electrically connected to each other of the printed circuit board, and a first element and a second element are respectively used to generate a first output power corresponding to the first current outflow pin and a second output power corresponding to the second current outflow pin according to a first input power corresponding to the first current inflow pin and a second input power corresponding to the second current inflow pin, and the current upper limits of the first output power and the second output power are respectively a first maximum output current and a second maximum output current; Wherein, in a combined configuration, the first current inflow pin and the second current inflow pin are both soldered to a common inflow printed conductor of the printed circuit board and electrically connected, and the first current outflow pin and the second current outflow pin are both soldered to a common outflow printed conductor of the printed circuit board and electrically connected, so that the first element is connected in parallel with the second element, and the first output stage circuit and the second output stage circuit are combined into a combined output stage circuit to generate a common output power supply, wherein the current upper limit of the common output power supply is the sum of the first maximum output current and the second maximum output current; A first current inflow end and a first current outflow end of the first element correspond to the first current inflow pin and the first current outflow pin, and a second current inflow end and a second current outflow end of the second element correspond to the second current inflow pin and the second current outflow pin.

2. The power management integrated circuit as claimed in claim 1, wherein: The common inflow printed conductor and the common outflow printed conductor are both located below the integrated circuit and between the integrated circuit and the printed circuit board.

3. The power management integrated circuit as claimed in claim 2, wherein: The common inflow printed conductor and / or the common outflow printed conductor are located on the uppermost layer of the printed circuit board.

4. The power management integrated circuit as claimed in claim 3, wherein: The first current inflow pin and the second current inflow pin are located on the same plane, so that the common inflow printed conductor is located on the top layer of the printed circuit board, and / or the first current outflow pin and the second current outflow pin are located on the same plane, so that the common outflow printed conductor is located on the top layer of the printed circuit board.

5. The power management integrated circuit as claimed in claim 4, wherein: The first current inflow pin and the second current inflow pin are located on both sides of the integrated circuit in a width direction and the first current inflow pin and the second current inflow pin are aligned with each other in a length direction, so that the common inflow printed conductor is located on the top layer of the printed circuit board, and / or, the first current outflow pin and the second current outflow pin are located on both sides of the integrated circuit in the width direction and the first current outflow pin and the second current outflow pin are aligned with each other in the length direction, so that the common outflow printed conductor is located on the top layer of the printed circuit board.

6. The power management integrated circuit as claimed in claim 5, wherein: The common inflow printed conductor is aligned with the first current inflow pin and the second current inflow pin in the length direction, and / or the common outflow printed conductor is aligned with the first current outflow pin and the second current outflow pin in the length direction.

7. The power management integrated circuit as claimed in claim 1, wherein: The first output stage circuit and the second output stage circuit are a linear power conversion circuit, wherein: In the discrete configuration, the first element and the second element correspond to a first transistor and a second transistor, respectively generating the first output power and the second output power in a linear regulation manner according to a first feedback signal and a second feedback signal of the first output power and the second output power; and In the combined configuration, the first element and the second element are connected in parallel to form a common transistor, and the common output power is generated in a linear regulation manner according to a common feedback signal of the common output power.

8. The power management integrated circuit as claimed in claim 1, wherein: The first output stage circuit and the second output stage circuit are a switching output stage circuit, wherein: In the discrete configuration, the first component and the second component respectively include an upper bridge switch and a lower bridge switch of the switching output stage circuit, a driving circuit for driving the upper bridge switch or the lower bridge switch, and / or a current detection circuit, for controlling the switching of a corresponding first inductor and a corresponding second inductor according to a first feedback signal and a second feedback signal of the first output power and the second output power, respectively, to generate the first output power and the second output power; and In the combined configuration, the first element and the second element control the switching of a corresponding inductor according to a common feedback signal of the common output power to generate the common output power.

9. The power management integrated circuit of claim 8, wherein: In the discrete configuration, the first current inflow pin and the first current outflow pin are electrically connected to a first input voltage and a first switching node through the first inflow printed wire and the first outflow printed wire, and the second current inflow pin and the second current outflow pin are electrically connected to a second output voltage and a second switching node through the second inflow printed wire and the second outflow printed wire; as well as In the combined configuration, the first current inflow pin and the first current outflow pin are electrically connected to a common input voltage and a common switching node through the common inflow printed wire and the common outflow printed wire, and the second current inflow pin and the second current outflow pin are electrically connected to the common input voltage and the common switching node through the common inflow printed wire and the common outflow printed wire. 10 . A power management system, comprising the power management integrated circuit as claimed in any one of claims 1 to 9 and the printed circuit board.

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