Semiconductor device and manufacturing method thereof
By designing alternately arranged in the three-dimensional memory device, stacking of insulating layers and word plane conductors, and setting up a vertical columnar structure, including conductive cores, internal electrodes and OTS layers, the problem that existing memory devices are difficult to achieve high component density and small size in a limited space, achieving high efficiency and high density memory effects.
Patent Information
- Application Number
- CN202311298982.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2023-09-11
- Filing Date
- 2023-10-09
- Publication Date
- 2025-03-11
AI Technical Summary
Existing three-dimensional memory devices are difficult to achieve high component density and small size in limited space, and cannot meet the needs of small-volume and large-capacity memory.
A semiconductor device is designed, including a stack of an insulating layer and a word plane conductor arranged in the stack, including a conductive core, an inner electrode and a bidirectional threshold switch (OTS) layer. The outer electrode is arranged between the OTS layer and the word plane conductor, and the material is selected to achieve good junction resistance performance.
Through this design, high component density and small size memory devices are realized, the efficiency and capacity of the memory are improved, and the needs of small volume and large capacity are met.
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Figure CN119603973A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to a semiconductor device and a method for manufacturing the same. Background Art
[0002] In recent years, with the evolution of the structure of semiconductor devices, the storage capacity of these semiconductor devices has also increased. Memory devices are often used in storage components of electronic products such as digital cameras, mobile phones, computers, etc. With the expansion of application fields, the demand for memory devices is also developing towards small size and large capacity. In order to meet these needs, a high component density and small size memory device and a corresponding manufacturing method are needed.
[0003] In order to increase the capacity of memory in a limited space, a three-dimensional (3D) memory has been developed. In some 3D memory technologies, vertical channel structures are set in each operating area (block) and arranged in rows. In each operating area, multiple horizontal word lines are formed by stacking conductor layers. These word lines intersect these vertical channel structures in the operating area. Therefore, this type of 3D memory is also called a gate-all-around memory cell. Summary of the invention
[0004] One aspect of the present disclosure provides a semiconductor device, comprising a stack of insulating layers and word plane conductors arranged alternately, a vertical columnar structure disposed in the stack, and an external electrode. The vertical columnar structure comprises a conductive core, an inner electrode, and an ovonic threshold switch (OTS) layer, wherein the inner electrode is disposed on a side wall of the conductive core, the OTS layer is disposed on a side wall of the inner electrode, and the inner electrode is located between the conductive core and the OTS layer. The external electrode is disposed between the OTS layer and the word plane conductor, wherein the resistance of the material of the word plane conductor is lower than the resistance of the material of the external electrode.
[0005] In some embodiments, the external electrode directly contacts the OTS layer and the word plane conductor.
[0006] In some embodiments, the material of the word plane conductor includes TiN, W, Al, Cu, TaN, Ru, Co, WN or a combination thereof, and the material of the external electrode includes TiN, carbon, graphene, doped carbon, WN, TaN, or W.
[0007] In some embodiments, the resistance of the material of the conductive core is less than the resistance of the material of the inner electrode.
[0008] In some embodiments, the material of the conductive core includes TiN, W, Al, Cu, TaN, Ru, Co, WN or a combination thereof, and the material of the inner electrode includes TiN, carbon, graphene, doped carbon, WN, TaN, or W.
[0009] In some embodiments, the inner electrode is continuously disposed on the sidewall and bottom surface of the conductive core, the OTS layer is continuously disposed on the sidewall and bottom surface of the inner electrode, and the sidewall of the insulating layer directly contacts the OTS layer.
[0010] In some embodiments, the inner electrode is continuously disposed on the sidewall and bottom surface of the conductive core, the OTS layer comprises a plurality of OTS segments, the OTS segments are disposed on the sidewall of the inner electrode, the sidewall of the insulating layer directly contacts the inner electrode, and the OTS segments are separated by the insulating layer.
[0011] Another aspect of the present disclosure provides a method for manufacturing a semiconductor device, comprising the following steps: forming a stack including alternating insulating layers and word plane conductors, and forming a vertical columnar structure in the stack, the vertical columnar structure including a conductive core, an inner electrode, and an ovonic threshold switch (OTS) layer, the inner electrode being disposed on a sidewall of the conductive core, the OTS layer being disposed on a sidewall of the inner electrode, and the inner electrode being located between the conductive core and the OTS layer. The method further comprises forming an outer electrode between the OTS layer and the word plane conductor, wherein the resistance of a material of the word plane conductor is lower than the resistance of a material of the outer electrode.
[0012] In some embodiments, the step of forming a stack including alternating insulating layers and word-plane conductors includes: forming a stack including alternating insulating layers and sacrificial layers; and replacing the sacrificial layers with word-plane conductors.
[0013] In some embodiments, the step of forming an external electrode between the OTS layer and the word-plane conductor includes: recessing the word-plane conductor so that the side surface of the word-plane conductor is recessed inward from the side surface of the insulating layer; depositing electrode material on the side surface of the word-plane conductor and the side surface of the insulating layer; and removing the protruding portion of the electrode material, wherein the remaining electrode material serves as the external electrode, and the side surface of the external electrode is aligned with the side surface of the insulating layer.
[0014] The semiconductor device provided by the present disclosure is an OTS type memory device, which requires a set / reset current to flow through a vertical columnar structure and a word plane to complete the operation. The materials of the inner electrode and the outer electrode adjacent to the OTS layer are selected to have good junction resistance performance, and the materials of the conductive core in the vertical columnar structure and the word plane conductor are selected to have low resistance. In this way, the performance of the semiconductor device can be improved. BRIEF DESCRIPTION OF THE DRAWINGS
[0015] To make the purpose, features, advantages and embodiments of the present disclosure more clearly understood, the detailed description of the accompanying drawings is as follows:
[0016] Figure 1 is a perspective view of a semiconductor device according to some embodiments of the present disclosure.
[0017] Figure 2 For along Figure 1 Top view of plane AA in .
[0018] Figure 3 For along Figure 2 Cross-sectional view of plane BB in FIG.
[0019] Figures 4 to 10 2 are cross-sectional views of a method for manufacturing a semiconductor device at different manufacturing stages according to some embodiments of the present disclosure.
[0020] Fig.11 are cross-sectional views of semiconductor devices according to other embodiments of the present disclosure.
[0021] Fig.12 and Fig.13 2 are cross-sectional views of a method for manufacturing a semiconductor device at different manufacturing stages according to some embodiments of the present disclosure.
[0022] Description of Reference Numerals
[0023] 100, 100A: Semiconductor device
[0024] 110: Insulation layer
[0025] 120, 120a: Word plane conductor
[0026] 130, 130a, 130b, 130c, 130A: External electrodes
[0027] 130': Electrode material
[0028] 140: Covering layer
[0029] 150: Holes
[0030] 160: Interval
[0031] 170: Sacrificial Layer
[0032] 200: Vertical columnar structure
[0033] 210: Conductive core
[0034] 210': Conductive material
[0035] 220: Inner electrode
[0036] 220': Another electrode material
[0037] 230,230A: OTS layer
[0038] 230': OTS material
[0039] 232: OTS segment
[0040] AA,BB: plane
[0041] S1, S2, S3, S4: side surface DETAILED DESCRIPTION
[0042] The spirit of the present disclosure will be clearly illustrated below with accompanying drawings and detailed descriptions. Any person having ordinary knowledge in the technical field can make changes and modifications based on the techniques taught by the present disclosure after understanding the preferred embodiments of the present disclosure, without departing from the spirit and scope of the present disclosure.
[0043] Reference Figures 1 to 3 ,in Figure 1 is a perspective view of a semiconductor device according to some embodiments of the present disclosure, Figure 2 For along Figure 1 The top view of plane AA in Figure 3 It is along the Figure 2 A cross-sectional view of plane BB in FIG. The semiconductor device 100 of some embodiments of the present disclosure is related to a gate-all-around memory cell, and in particular, to an ovonic threshold switch (OTS) memory cell. The semiconductor device 100 includes a stack of a plurality of alternately stacked insulating layers 110 and word-plane conductors 120, the stack being formed on a substrate. The semiconductor device 100 also includes a plurality of vertical columnar structures 200 passing through the stack of insulating layers 110 and word-plane conductors 120, and an external electrode 130 disposed between the vertical columnar structures 200 and the word-plane conductors 120. The semiconductor device 100 also includes a capping layer 140 disposed on the uppermost insulating layer 110 and on the upper surface of the vertical columnar structure 200.
[0044] Each vertical columnar structure 200 includes a conductive core 210, an inner electrode 220, and an ovonic threshold switch (OTS) layer 230, wherein the inner electrode 220 covers the sidewall and bottom surface of the conductive core 210, the OTS layer 230 covers the sidewall and bottom surface of the inner electrode 220, and the inner electrode 220 is located between the conductive core 210 and the OTS layer 230. In some embodiments, the conductive core 210 is Figure 2 ) has a circular cross section, the inner electrode 220 and the OTS layer 230 are in the top view (such as Figure 2) each having a circular cross section. The inner electrode 220 and the OTS layer 230 are in the cross-sectional view (eg Figure 3 ) each having a U-shaped cross-section.
[0045] The external electrodes 130 are disposed on the same plane (i.e., the same word plane) as the corresponding word plane conductors 120. In other words, each external electrode 130 and the corresponding word plane conductor 120 are sandwiched between adjacent insulating layers 110. The external electrodes 130 surround the sidewalls of each vertical columnar structure 200. Each external electrode 130 is disposed on the same plane (i.e., the same word plane) as the corresponding word plane conductors 120. Figure 2 ) each having a circular cross-section, and the external electrodes 130 in different word planes are separated from each other. In other words, the external electrodes 130 in different word planes are not connected to each other and the external electrodes 130 in different word planes are separated by at least one insulating layer 110. The external electrode 130 is an OTS layer 230 that directly contacts each vertical columnar structure 200.
[0046] Preferably, the material of the outer electrode 130 is different from the material of the plane conductor 120, and the material of the conductive core 210 is also different from the material of the inner electrode 220, so that the electrical properties of the outer electrode 130 are different from the electrical properties of the plane conductor 120, and the electrical properties of the conductive core 210 are also different from the electrical properties of the inner electrode 220.
[0047] For example, the resistance of the word plane conductor 120 is lower than the resistance of the outer electrodes 130, and the separated outer electrodes 130 are configured to provide a better junction resistance performance between the OTS layer 230 and the word plane conductor 120. In addition, the resistance of the conductive core 210 is lower than the resistance of the inner electrode 220, and the inner electrode 220 is configured to provide a better junction resistance performance between the OTS layer 230 and the conductive core 210.
[0048] The semiconductor device 100 is an OTS type memory cell, which is a current-type device that requires a set / reset current to pass between the vertical columnar structure 200 and the word plane conductor 120 to complete operation. The semiconductor device 100 in the present disclosure uses different material combinations to provide lower resistance and better junction resistance performance, respectively. In this way, the performance of the semiconductor device 100 can be improved.
[0049] Reference Figures 4 to 10 ,in Figures 4 to 10 1 is a cross-sectional view of a method for manufacturing a semiconductor device according to some embodiments of the present disclosure at different manufacturing stages. Figure 4As shown, the method begins with making a stack including an insulating layer 110 and a digit plane conductor 120. The insulating layer 110 and the digit plane conductor 120 are alternately stacked. In some embodiments, the thickness of the insulating layer 110 and the digit plane conductor 120 can be the same or different.
[0050] In some embodiments, the stack of the insulating layer 110 and the word-plane conductor 120 is formed on a substrate, such as a silicon substrate. In other embodiments, the stack of the insulating layer 110 and the word-plane conductor 120 is formed on a substrate having a semiconductor element, such as a substrate having a complementary metal oxide semiconductor (CMOS) or other suitable circuits.
[0051] The insulating layer 110 is an oxide layer, such as a silicon oxide layer, and the word plane conductor 120 is made of a material having a low resistance. For example, the low resistance material of the word plane conductor 120 may include TiN, W, Al, Cu, TaN, Ru, Co, WN or a combination thereof. The insulating layer 110 and the word plane conductor 120 may be formed by any suitable deposition process, such as atomic layer deposition (ALD).
[0052] Reference Figure 5 , a plurality of holes 150 are formed in the stack of the insulating layer 110 and the word plane conductor 120. The holes 150 may be formed by an etching process, and the etching process stops at the bottom insulating layer 110. In some embodiments, a patterned mask layer may be formed on the stack of the insulating layer 110 and the word plane conductor 120, and the portion of the stack of the insulating layer 110 and the word plane conductor 120 not covered by the patterned mask layer may be removed in the etching process to form the holes 150. The patterned mask layer may then be removed after the holes 150 are formed. In some embodiments, the bottom insulating layer 110 may have a thicker thickness so that the bottom of the hole 150 may stop in the bottom insulating layer 110.
[0053] Reference Figure 6 , an etching process is performed to remove a portion of the word-plane conductor 120, so that the word-plane conductor 120 is recessed inward relative to the insulating layer 110. More specifically, the etching process has a high etching selectivity between the insulating layer 110 and the word-plane conductor 120, and the etching rate of the word-plane conductor 120 is much greater than the etching rate of the insulating layer 110. In this way, the side surface S1 of the insulating layer 110 will protrude laterally from the side surface S2 of the word-plane conductor 120, so that a plurality of spaces 160 are formed between the insulating layer 110. In some embodiments, the side surface S2 of each word-plane conductor 120 can be flat, concave, or convex, depending on the selected etching process.
[0054] Reference Figure 7 , the electrode material 130' is deposited on Figure 6 In some embodiments, the electrode material 130' is conformally deposited on the side surface S1 of the insulating layer 110 and the side surface S2 of the word plane conductor 120, and the electrode material 130' at least fills the gap 160 (such as Figure 6 shown).
[0055] The material of the electrode material 130' is different from the material of the word plane conductor 120. More specifically, the material of the electrode material 130' is also a conductor, but the resistance of the word plane conductor 120 is lower than the resistance of the electrode material 130'. The material of the electrode material 130' is selected to provide a material with good junction resistance performance between the OTS layer and the word plane conductor 120. For example, the material of the electrode material 130' can be TiN, carbon, graphene, doped carbon, WN, TaN, or W.
[0056] Reference Figure 8 , an etching process is performed to remove the protruding portion of the electrode material 130' (eg Figure 7 ), and the remaining electrode material 130' serves as the external electrode 130. In some embodiments, the etching process for removing the protruding portion of the electrode material 130' is an anisotropic etching process, such as reactive ion etching (RIE), and a portion of the insulating layer 110 may also be removed in this etching process.
[0057] After the etching process is completed, the external electrode 130 only exists in the space 160 (see FIG. Figure 6 ), and the side surface S1 of the insulating layer 110 is aligned with the side surface S3 of the external electrode 130. After the etching process of removing the electrode material 130', the bottom insulating layer 110 is exposed through the hole 150 again.
[0058] Reference Fig. 9 , the OTS material 230' is conformally deposited in the hole 150 (see Figure 8 ), and another electrode material 220' is conformally deposited on the OTS material 230'. Then, a conductive material 210' is deposited to fill the hole 150. In some embodiments, the hole 150 is completely filled with the conductive material 210' without any gaps therein.
[0059] The material of the OTS material 230' includes a chalcogenide that can be used as a bidirectional threshold switch, such as As2Se3, ZnTe or GeSe, etc. In some embodiments, the material of the OTS material 230' can be a combination of a chalcogenide and other elements, such as a chalcogenide and Te, Se, Ge, Si, As, Ti, S, Sb and a combination thereof.
[0060] The material of the other electrode material 220' is different from the material of the conductive material 210'. More specifically, the material of the other electrode material 220' is also conductive, but the resistance of the conductive material 210' is lower than the resistance of the other electrode material 220'.
[0061] For example, the material of the conductive material 210' may include TiN, W, Al, Cu, TaN, Ru, Co, WN or a combination thereof. The material of the other electrode material 220' is selected to provide a material that can provide a good junction resistance performance between the OTS material 230' and the conductive material 210'. For example, the material of the other electrode material 220' may be TiN, carbon, graphene, doped carbon, WN, TaN, W.
[0062] Reference Fig.10 , a polishing process is performed to remove the excess portions of the conductive material 210', the other electrode material 220', and the OTS material 230' (see Fig. 9 ). The polishing process may be a chemical mechanical polishing (CMP) process, and the polishing process stops at the topmost insulating layer 110. Thus, after the polishing process, a plurality of vertical columnar structures 200 are defined in the holes. Next, a capping layer 140 is deposited on the vertical columnar structures 200 and the topmost insulating layer 110 to seal the memory array.
[0063] Each vertical columnar structure 200 comprises a conductive core 210, an inner electrode 220 and an OTS layer 230, wherein the inner electrode 220 directly contacts the sidewall and bottom surface of the conductive core 210, and the OTS layer 230 directly contacts the sidewall and bottom surface of the inner electrode 220. The outer electrode 130 and the word plane conductor 120 together serve as the gate structure of the vertical columnar structure 200, thereby forming a memory cell with a full-surround gate.
[0064] The material of the word plane conductor 120 and the conductive core 210 is selected to have a low resistance, so that the set / reset current flowing through the semiconductor device 100 can be reduced. The material of the word plane conductor 120 and the conductive core 210 may include TiN, W, Al, Cu, TaN, Ru, Co, WN or a combination thereof. In some embodiments, the material of the word plane conductor 120 may be the same as the material of the conductive core 210. In some other embodiments, the material of the word plane conductor 120 may be different from the material of the conductive core 210.
[0065] The materials of the inner electrode 220 and the outer electrode 130 are selected to provide good junction resistance performance between the conductive core 210 and the OTS layer 230 or between the OTS layer 230 and the word plane conductor 120, so that the OTS characteristics of the semiconductor device 100 can be improved. The materials of the inner electrode 220 and the outer electrode 130 can be TiN, carbon, graphene, doped carbon, WN, TaN, or W. In some embodiments, the material of the outer electrode 130 can be the same as the material of the inner electrode 220. In some other embodiments, the material of the outer electrode 130 can be different from the material of the inner electrode 220.
[0066] like Fig.10 As shown, the external electrodes 130 are separated from each other. For example, the external electrode 130a and the external electrode 130b located in the same word plane are physically separated by the word plane conductor 120a. The external electrodes 130a, the external electrodes 130b and the word plane conductor 120a located in the same word plane are electrically connected to each other. In addition, the external electrodes 130a and the external electrodes 130c located in different word planes are physically and electrically separated by at least one insulating layer 110. Each external electrode 130 directly contacts the OTS layer 230 in the corresponding vertical columnar structure 200. Each insulating layer 110 also directly contacts the OTS layer 230 in the corresponding vertical columnar structure 200.
[0067] Reference Fig.11 , which is a cross-sectional view of a semiconductor device according to some other embodiments of the present disclosure. The semiconductor device 100A is mainly different from the semiconductor device 100 in that the OTS layer 230A of each vertical columnar structure 200 in the semiconductor device 100A is divided into a plurality of OTS segments 232. More specifically, the external electrode 130A is further recessed inward from the insulating layer 110, and the OTS segment 232 fills the space between the external electrode 130A and the insulating layer 110.
[0068] The side surface S3 of the external electrode 130A is recessed inward relative to the side surface S1 of the insulating layer 110, and the side surface S4 of the OTS segment 232 is aligned with the side surface S1 of the insulating layer 110. The OTS segments 232 are separated from each other. The OTS segments 232 located in different word planes are physically and electrically separated by the insulating layer 110. The OTS segments 232 located in the same word plane are physically separated by the word plane conductor 120 and the external electrode 130A.
[0069] The inner electrode 220 directly and continuously contacts the sidewall and bottom surface of the conductive core 210, and the bottom surface of the inner electrode 220 directly contacts the bottommost insulating layer 110 without an OTS layer 230A therebetween. Each OTS segment 232 directly contacts the inner electrode 220 of the corresponding vertical columnar structure 200. Each insulating layer 110 directly contacts the inner electrode 220 of the corresponding vertical columnar structure 200.
[0070] Reference Fig.12 and Fig.13 , Fig.12 and Fig.13 1 is a cross-sectional view of a method for manufacturing a semiconductor device according to some embodiments of the present disclosure at different stages of manufacturing. In some embodiments, the word plane conductor 120 can also be manufactured by a gate replacement process. In the case where the word plane conductor 120 is manufactured by a gate replacement process, such as Figure 4 The stack shown is a stack including an insulating layer 110 and a sacrificial layer 170, wherein the material of the insulating layer 110 is different from the material of the sacrificial layer 170. For example, the material of the insulating layer 110 may be an oxide, such as silicon oxide, and the material of the sacrificial layer 170 may be a nitride, such as silicon nitride. The sacrificial layer 170 is further replaced by a word plane conductor 120, such as Fig.13 The process of replacing the sacrificial layer 170 with the word plane conductor 120 is performed after the vertical columnar structure 200 is completed.
[0071] The semiconductor device provided by the present disclosure is an OTS type memory device, which requires a set / reset current to flow through a vertical columnar structure and a word plane to complete the operation. The materials of the inner electrode and the outer electrode adjacent to the OTS layer are selected to have good junction resistance performance, and the materials of the conductive core in the vertical columnar structure and the word plane conductor are selected to have low resistance. In this way, the performance of the semiconductor device can be improved.
[0072] Although the present disclosure has been disclosed as above by way of embodiments, it is not intended to limit the present disclosure. Any person skilled in the art may make various changes and modifications without departing from the spirit and scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be determined by the scope of the appended claims.
Claims
1. A semiconductor device comprising: a stack comprising a plurality of insulating layers and a plurality of word plane conductors arranged alternately; a vertical columnar structure disposed in the stack, the vertical columnar structure comprising a conductive core, an inner electrode, and an ovonic threshold switch (OTS) layer, the inner electrode being disposed on a side wall of the conductive core, the OTS layer being disposed on a side wall of the inner electrode, and the inner electrode being located between the conductive core and the OTS layer; and A plurality of external electrodes are disposed between the OTS layer and the word plane conductors, wherein the resistance of the material of the word plane conductors is lower than the resistance of the material of the external electrodes. 2 . The semiconductor device according to claim 1 , wherein the external electrodes directly contact the OTS layer and the word-plane conductors.
3. The semiconductor device according to claim 1, wherein the material of the word plane conductors comprises TiN, W, Al, Cu, TaN, Ru, Co, WN or a combination thereof, and the material of the external electrodes comprises TiN, carbon, graphene, doped carbon, WN, TaN, or W. 4 . The semiconductor device according to claim 1 , wherein a resistance value of a material of the conductive core is smaller than a resistance value of a material of the inner electrode.
5. The semiconductor device according to claim 4, wherein the material of the conductive core comprises TiN, W, Al, Cu, TaN, Ru, Co, WN or a combination thereof, and the material of the inner electrode comprises TiN, carbon, graphene-doped carbon, WN, TaN, or W.
6. The semiconductor device according to claim 1, wherein the inner electrode is continuously disposed on the side wall and a bottom surface of the conductive core, the OTS layer is continuously disposed on the side wall and a bottom surface of the inner electrode, and the side walls of the insulating layers directly contact the OTS layer.
7. The semiconductor device according to claim 1, wherein the inner electrode is continuously disposed on the side wall and a bottom surface of the conductive core, the OTS layer comprises a plurality of OTS segments, the OTS segments are disposed on the side wall of the inner electrode, the side walls of the insulating layers directly contact the inner electrode, and the OTS segments are separated by a plurality of insulating layers.
8. A method for manufacturing a semiconductor device, comprising the following steps: forming a stack comprising a plurality of insulating layers and a plurality of word plane conductors arranged alternately; forming a vertical columnar structure in the stack, the vertical columnar structure comprising a conductive core, an inner electrode, and an ovonic threshold switch (OTS) layer, the inner electrode being disposed on a side wall of the conductive core, the OTS layer being disposed on a side wall of the inner electrode, and the inner electrode being located between the conductive core and the OTS layer; and A plurality of external electrodes are formed between the OTS layer and the word plane conductors, wherein the resistance of the material of the word plane conductors is lower than the resistance of the material of the external electrodes.
9. The method of manufacturing a semiconductor device according to claim 8, wherein the step of forming a stack including a plurality of insulating layers and a plurality of word-plane conductors arranged alternately comprises: forming a stack comprising the insulating layers and the sacrificial layers arranged alternately; and The sacrificial layers are replaced with the word plane conductors.
10. The method for manufacturing a semiconductor device according to claim 8, wherein the step of forming a plurality of external electrodes between the OTS layer and the word plane conductors comprises: recessing the word-plane conductors so that the side surfaces of the word-plane conductors are recessed inward from the side surfaces of the insulating layers; Depositing an electrode material on the side surfaces of the word-plane conductors and the side surfaces of the insulating layers; and The protruding portion of the electrode material is removed, wherein the remaining electrode material serves as the external electrodes, and the side surfaces of the external electrodes are aligned with the side surfaces of the insulating layers.